2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 1.096187 # Number of seconds simulated
4 sim_ticks 1096186990500 # Number of ticks simulated
5 final_tick 1096186990500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 245276 # Simulator instruction rate (inst/s)
8 host_op_rate 264248 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 174074375 # Simulator tick rate (ticks/s)
10 host_mem_usage 310916 # Number of bytes of host memory used
11 host_seconds 6297.23 # Real time elapsed on the host
12 sim_insts 1544563087 # Number of instructions simulated
13 sim_ops 1664032480 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 131551936 # Number of bytes read from this memory
17 system.physmem.bytes_read::total 131551936 # Number of bytes read from this memory
18 system.physmem.bytes_inst_read::cpu.inst 50432 # Number of instructions bytes read from this memory
19 system.physmem.bytes_inst_read::total 50432 # Number of instructions bytes read from this memory
20 system.physmem.bytes_written::writebacks 66968384 # Number of bytes written to this memory
21 system.physmem.bytes_written::total 66968384 # Number of bytes written to this memory
22 system.physmem.num_reads::cpu.inst 2055499 # Number of read requests responded to by this memory
23 system.physmem.num_reads::total 2055499 # Number of read requests responded to by this memory
24 system.physmem.num_writes::writebacks 1046381 # Number of write requests responded to by this memory
25 system.physmem.num_writes::total 1046381 # Number of write requests responded to by this memory
26 system.physmem.bw_read::cpu.inst 120008664 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_read::total 120008664 # Total read bandwidth from this memory (bytes/s)
28 system.physmem.bw_inst_read::cpu.inst 46007 # Instruction read bandwidth from this memory (bytes/s)
29 system.physmem.bw_inst_read::total 46007 # Instruction read bandwidth from this memory (bytes/s)
30 system.physmem.bw_write::writebacks 61092117 # Write bandwidth from this memory (bytes/s)
31 system.physmem.bw_write::total 61092117 # Write bandwidth from this memory (bytes/s)
32 system.physmem.bw_total::writebacks 61092117 # Total bandwidth to/from this memory (bytes/s)
33 system.physmem.bw_total::cpu.inst 120008664 # Total bandwidth to/from this memory (bytes/s)
34 system.physmem.bw_total::total 181100781 # Total bandwidth to/from this memory (bytes/s)
35 system.physmem.readReqs 2055499 # Number of read requests accepted
36 system.physmem.writeReqs 1046381 # Number of write requests accepted
37 system.physmem.readBursts 2055499 # Number of DRAM read bursts, including those serviced by the write queue
38 system.physmem.writeBursts 1046381 # Number of DRAM write bursts, including those merged in the write queue
39 system.physmem.bytesReadDRAM 131465088 # Total number of bytes read from DRAM
40 system.physmem.bytesReadWrQ 86848 # Total number of bytes read from write queue
41 system.physmem.bytesWritten 66966784 # Total number of bytes written to DRAM
42 system.physmem.bytesReadSys 131551936 # Total read bytes from the system interface side
43 system.physmem.bytesWrittenSys 66968384 # Total written bytes from the system interface side
44 system.physmem.servicedByWrQ 1357 # Number of DRAM read bursts serviced by the write queue
45 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
46 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
47 system.physmem.perBankRdBursts::0 127914 # Per bank write bursts
48 system.physmem.perBankRdBursts::1 125107 # Per bank write bursts
49 system.physmem.perBankRdBursts::2 122280 # Per bank write bursts
50 system.physmem.perBankRdBursts::3 124254 # Per bank write bursts
51 system.physmem.perBankRdBursts::4 123262 # Per bank write bursts
52 system.physmem.perBankRdBursts::5 123345 # Per bank write bursts
53 system.physmem.perBankRdBursts::6 123865 # Per bank write bursts
54 system.physmem.perBankRdBursts::7 124190 # Per bank write bursts
55 system.physmem.perBankRdBursts::8 131999 # Per bank write bursts
56 system.physmem.perBankRdBursts::9 134064 # Per bank write bursts
57 system.physmem.perBankRdBursts::10 132428 # Per bank write bursts
58 system.physmem.perBankRdBursts::11 133673 # Per bank write bursts
59 system.physmem.perBankRdBursts::12 133725 # Per bank write bursts
60 system.physmem.perBankRdBursts::13 133862 # Per bank write bursts
61 system.physmem.perBankRdBursts::14 129895 # Per bank write bursts
62 system.physmem.perBankRdBursts::15 130279 # Per bank write bursts
63 system.physmem.perBankWrBursts::0 65789 # Per bank write bursts
64 system.physmem.perBankWrBursts::1 64087 # Per bank write bursts
65 system.physmem.perBankWrBursts::2 62403 # Per bank write bursts
66 system.physmem.perBankWrBursts::3 62885 # Per bank write bursts
67 system.physmem.perBankWrBursts::4 62820 # Per bank write bursts
68 system.physmem.perBankWrBursts::5 62979 # Per bank write bursts
69 system.physmem.perBankWrBursts::6 64285 # Per bank write bursts
70 system.physmem.perBankWrBursts::7 65232 # Per bank write bursts
71 system.physmem.perBankWrBursts::8 67082 # Per bank write bursts
72 system.physmem.perBankWrBursts::9 67588 # Per bank write bursts
73 system.physmem.perBankWrBursts::10 67303 # Per bank write bursts
74 system.physmem.perBankWrBursts::11 67613 # Per bank write bursts
75 system.physmem.perBankWrBursts::12 67020 # Per bank write bursts
76 system.physmem.perBankWrBursts::13 67468 # Per bank write bursts
77 system.physmem.perBankWrBursts::14 66169 # Per bank write bursts
78 system.physmem.perBankWrBursts::15 65633 # Per bank write bursts
79 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
80 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
81 system.physmem.totGap 1096186902500 # Total gap between requests
82 system.physmem.readPktSize::0 0 # Read request sizes (log2)
83 system.physmem.readPktSize::1 0 # Read request sizes (log2)
84 system.physmem.readPktSize::2 0 # Read request sizes (log2)
85 system.physmem.readPktSize::3 0 # Read request sizes (log2)
86 system.physmem.readPktSize::4 0 # Read request sizes (log2)
87 system.physmem.readPktSize::5 0 # Read request sizes (log2)
88 system.physmem.readPktSize::6 2055499 # Read request sizes (log2)
89 system.physmem.writePktSize::0 0 # Write request sizes (log2)
90 system.physmem.writePktSize::1 0 # Write request sizes (log2)
91 system.physmem.writePktSize::2 0 # Write request sizes (log2)
92 system.physmem.writePktSize::3 0 # Write request sizes (log2)
93 system.physmem.writePktSize::4 0 # Write request sizes (log2)
94 system.physmem.writePktSize::5 0 # Write request sizes (log2)
95 system.physmem.writePktSize::6 1046381 # Write request sizes (log2)
96 system.physmem.rdQLenPdf::0 1922421 # What read queue length does an incoming req see
97 system.physmem.rdQLenPdf::1 131703 # What read queue length does an incoming req see
98 system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see
99 system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
100 system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
128 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
129 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
130 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
131 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
132 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::15 31796 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::16 33166 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::17 57030 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::18 60853 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::19 61386 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::20 61606 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::21 61543 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::22 61534 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::23 61519 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::24 61592 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::25 61559 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::26 61622 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::27 61936 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::28 62305 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::29 61675 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::30 62790 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::31 61332 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::32 61028 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::33 81 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::34 8 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
192 system.physmem.bytesPerActivate::samples 1916158 # Bytes accessed per row activation
193 system.physmem.bytesPerActivate::mean 103.556187 # Bytes accessed per row activation
194 system.physmem.bytesPerActivate::gmean 81.764224 # Bytes accessed per row activation
195 system.physmem.bytesPerActivate::stdev 125.552714 # Bytes accessed per row activation
196 system.physmem.bytesPerActivate::0-127 1491113 77.82% 77.82% # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::128-255 305811 15.96% 93.78% # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::256-383 52727 2.75% 96.53% # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::384-511 21051 1.10% 97.63% # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::512-639 13077 0.68% 98.31% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::640-767 6875 0.36% 98.67% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::768-895 5570 0.29% 98.96% # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::896-1023 4107 0.21% 99.17% # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::1024-1151 15827 0.83% 100.00% # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::total 1916158 # Bytes accessed per row activation
206 system.physmem.rdPerTurnAround::samples 61021 # Reads before turning the bus around for writes
207 system.physmem.rdPerTurnAround::mean 33.615247 # Reads before turning the bus around for writes
208 system.physmem.rdPerTurnAround::stdev 160.737468 # Reads before turning the bus around for writes
209 system.physmem.rdPerTurnAround::0-1023 60978 99.93% 99.93% # Reads before turning the bus around for writes
210 system.physmem.rdPerTurnAround::1024-2047 19 0.03% 99.96% # Reads before turning the bus around for writes
211 system.physmem.rdPerTurnAround::2048-3071 9 0.01% 99.98% # Reads before turning the bus around for writes
212 system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.99% # Reads before turning the bus around for writes
213 system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes
214 system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes
215 system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes
216 system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes
217 system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes
218 system.physmem.rdPerTurnAround::total 61021 # Reads before turning the bus around for writes
219 system.physmem.wrPerTurnAround::samples 61021 # Writes before turning the bus around for reads
220 system.physmem.wrPerTurnAround::mean 17.147474 # Writes before turning the bus around for reads
221 system.physmem.wrPerTurnAround::gmean 17.112394 # Writes before turning the bus around for reads
222 system.physmem.wrPerTurnAround::stdev 1.099372 # Writes before turning the bus around for reads
223 system.physmem.wrPerTurnAround::16 27727 45.44% 45.44% # Writes before turning the bus around for reads
224 system.physmem.wrPerTurnAround::17 1223 2.00% 47.44% # Writes before turning the bus around for reads
225 system.physmem.wrPerTurnAround::18 27936 45.78% 93.22% # Writes before turning the bus around for reads
226 system.physmem.wrPerTurnAround::19 3708 6.08% 99.30% # Writes before turning the bus around for reads
227 system.physmem.wrPerTurnAround::20 355 0.58% 99.88% # Writes before turning the bus around for reads
228 system.physmem.wrPerTurnAround::21 59 0.10% 99.98% # Writes before turning the bus around for reads
229 system.physmem.wrPerTurnAround::22 10 0.02% 100.00% # Writes before turning the bus around for reads
230 system.physmem.wrPerTurnAround::23 2 0.00% 100.00% # Writes before turning the bus around for reads
231 system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads
232 system.physmem.wrPerTurnAround::total 61021 # Writes before turning the bus around for reads
233 system.physmem.totQLat 38533876500 # Total ticks spent queuing
234 system.physmem.totMemAccLat 77049039000 # Total ticks spent from burst creation until serviced by the DRAM
235 system.physmem.totBusLat 10270710000 # Total ticks spent in databus transfers
236 system.physmem.avgQLat 18759.11 # Average queueing delay per DRAM burst
237 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
238 system.physmem.avgMemAccLat 37509.11 # Average memory access latency per DRAM burst
239 system.physmem.avgRdBW 119.93 # Average DRAM read bandwidth in MiByte/s
240 system.physmem.avgWrBW 61.09 # Average achieved write bandwidth in MiByte/s
241 system.physmem.avgRdBWSys 120.01 # Average system read bandwidth in MiByte/s
242 system.physmem.avgWrBWSys 61.09 # Average system write bandwidth in MiByte/s
243 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
244 system.physmem.busUtil 1.41 # Data bus utilization in percentage
245 system.physmem.busUtilRead 0.94 # Data bus utilization in percentage for reads
246 system.physmem.busUtilWrite 0.48 # Data bus utilization in percentage for writes
247 system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
248 system.physmem.avgWrQLen 24.88 # Average write queue length when enqueuing
249 system.physmem.readRowHits 777772 # Number of row buffer hits during reads
250 system.physmem.writeRowHits 406558 # Number of row buffer hits during writes
251 system.physmem.readRowHitRate 37.86 # Row buffer hit rate for reads
252 system.physmem.writeRowHitRate 38.85 # Row buffer hit rate for writes
253 system.physmem.avgGap 353394.36 # Average gap between requests
254 system.physmem.pageHitRate 38.20 # Row buffer hit rate, read and write combined
255 system.physmem.memoryStateTime::IDLE 306608104500 # Time in different power states
256 system.physmem.memoryStateTime::REF 36603840000 # Time in different power states
257 system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
258 system.physmem.memoryStateTime::ACT 752971887000 # Time in different power states
259 system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
260 system.physmem.actEnergy::0 7068978000 # Energy for activate commands per rank (pJ)
261 system.physmem.actEnergy::1 7417161360 # Energy for activate commands per rank (pJ)
262 system.physmem.preEnergy::0 3857081250 # Energy for precharge commands per rank (pJ)
263 system.physmem.preEnergy::1 4047062250 # Energy for precharge commands per rank (pJ)
264 system.physmem.readEnergy::0 7754580600 # Energy for read commands per rank (pJ)
265 system.physmem.readEnergy::1 8267360400 # Energy for read commands per rank (pJ)
266 system.physmem.writeEnergy::0 3307910400 # Energy for write commands per rank (pJ)
267 system.physmem.writeEnergy::1 3472476480 # Energy for write commands per rank (pJ)
268 system.physmem.refreshEnergy::0 71597111040 # Energy for refresh commands per rank (pJ)
269 system.physmem.refreshEnergy::1 71597111040 # Energy for refresh commands per rank (pJ)
270 system.physmem.actBackEnergy::0 413628192720 # Energy for active background per rank (pJ)
271 system.physmem.actBackEnergy::1 422690389875 # Energy for active background per rank (pJ)
272 system.physmem.preBackEnergy::0 294876051750 # Energy for precharge background per rank (pJ)
273 system.physmem.preBackEnergy::1 286926756000 # Energy for precharge background per rank (pJ)
274 system.physmem.totalEnergy::0 802089905760 # Total energy per rank (pJ)
275 system.physmem.totalEnergy::1 804418317405 # Total energy per rank (pJ)
276 system.physmem.averagePower::0 731.713906 # Core power per rank (mW)
277 system.physmem.averagePower::1 733.838021 # Core power per rank (mW)
278 system.membus.trans_dist::ReadReq 1255486 # Transaction distribution
279 system.membus.trans_dist::ReadResp 1255486 # Transaction distribution
280 system.membus.trans_dist::Writeback 1046381 # Transaction distribution
281 system.membus.trans_dist::ReadExReq 800013 # Transaction distribution
282 system.membus.trans_dist::ReadExResp 800013 # Transaction distribution
283 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5157379 # Packet count per connected master and slave (bytes)
284 system.membus.pkt_count::total 5157379 # Packet count per connected master and slave (bytes)
285 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198520320 # Cumulative packet size per connected master and slave (bytes)
286 system.membus.pkt_size::total 198520320 # Cumulative packet size per connected master and slave (bytes)
287 system.membus.snoops 0 # Total snoops (count)
288 system.membus.snoop_fanout::samples 3101880 # Request fanout histogram
289 system.membus.snoop_fanout::mean 0 # Request fanout histogram
290 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
291 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
292 system.membus.snoop_fanout::0 3101880 100.00% 100.00% # Request fanout histogram
293 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
294 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
295 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
296 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
297 system.membus.snoop_fanout::total 3101880 # Request fanout histogram
298 system.membus.reqLayer0.occupancy 12229457500 # Layer occupancy (ticks)
299 system.membus.reqLayer0.utilization 1.1 # Layer utilization (%)
300 system.membus.respLayer1.occupancy 19361348500 # Layer occupancy (ticks)
301 system.membus.respLayer1.utilization 1.8 # Layer utilization (%)
302 system.cpu_clk_domain.clock 500 # Clock period in ticks
303 system.cpu.branchPred.lookups 239650352 # Number of BP lookups
304 system.cpu.branchPred.condPredicted 186306880 # Number of conditional branches predicted
305 system.cpu.branchPred.condIncorrect 14598405 # Number of conditional branches incorrect
306 system.cpu.branchPred.BTBLookups 131764254 # Number of BTB lookups
307 system.cpu.branchPred.BTBHits 121991524 # Number of BTB hits
308 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
309 system.cpu.branchPred.BTBHitPct 92.583171 # BTB Hit Percentage
310 system.cpu.branchPred.usedRAS 15654227 # Number of times the RAS was used to get a target.
311 system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions.
312 system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
313 system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
314 system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
315 system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
316 system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
317 system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
318 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
319 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
320 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
321 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
322 system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
323 system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
324 system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
325 system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
326 system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
327 system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
328 system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
329 system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
330 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
331 system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
332 system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
333 system.cpu.dtb.inst_hits 0 # ITB inst hits
334 system.cpu.dtb.inst_misses 0 # ITB inst misses
335 system.cpu.dtb.read_hits 0 # DTB read hits
336 system.cpu.dtb.read_misses 0 # DTB read misses
337 system.cpu.dtb.write_hits 0 # DTB write hits
338 system.cpu.dtb.write_misses 0 # DTB write misses
339 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
340 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
341 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
342 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
343 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
344 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
345 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
346 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
347 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
348 system.cpu.dtb.read_accesses 0 # DTB read accesses
349 system.cpu.dtb.write_accesses 0 # DTB write accesses
350 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
351 system.cpu.dtb.hits 0 # DTB hits
352 system.cpu.dtb.misses 0 # DTB misses
353 system.cpu.dtb.accesses 0 # DTB accesses
354 system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
355 system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
356 system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
357 system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
358 system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
359 system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
360 system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
361 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
362 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
363 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
364 system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
365 system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
366 system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
367 system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
368 system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
369 system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
370 system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
371 system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
372 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
373 system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
374 system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
375 system.cpu.itb.inst_hits 0 # ITB inst hits
376 system.cpu.itb.inst_misses 0 # ITB inst misses
377 system.cpu.itb.read_hits 0 # DTB read hits
378 system.cpu.itb.read_misses 0 # DTB read misses
379 system.cpu.itb.write_hits 0 # DTB write hits
380 system.cpu.itb.write_misses 0 # DTB write misses
381 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
382 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
383 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
384 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
385 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
386 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
387 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
388 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
389 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
390 system.cpu.itb.read_accesses 0 # DTB read accesses
391 system.cpu.itb.write_accesses 0 # DTB write accesses
392 system.cpu.itb.inst_accesses 0 # ITB inst accesses
393 system.cpu.itb.hits 0 # DTB hits
394 system.cpu.itb.misses 0 # DTB misses
395 system.cpu.itb.accesses 0 # DTB accesses
396 system.cpu.workload.num_syscalls 46 # Number of system calls
397 system.cpu.numCycles 2192373981 # number of cpu cycles simulated
398 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
399 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
400 system.cpu.committedInsts 1544563087 # Number of instructions committed
401 system.cpu.committedOps 1664032480 # Number of ops (including micro ops) committed
402 system.cpu.discardedOps 42081657 # Number of ops (including micro ops) which were discarded before commit
403 system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
404 system.cpu.cpi 1.419414 # CPI: cycles per instruction
405 system.cpu.ipc 0.704516 # IPC: instructions per cycle
406 system.cpu.tickCycles 1808241834 # Number of cycles that the object actually ticked
407 system.cpu.idleCycles 384132147 # Total number of cycles that the object has spent stopped
408 system.cpu.icache.tags.replacements 29 # number of replacements
409 system.cpu.icache.tags.tagsinuse 661.144399 # Cycle average of tags in use
410 system.cpu.icache.tags.total_refs 464861353 # Total number of references to valid blocks.
411 system.cpu.icache.tags.sampled_refs 820 # Sample count of references to valid blocks.
412 system.cpu.icache.tags.avg_refs 566904.089024 # Average number of references to valid blocks.
413 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
414 system.cpu.icache.tags.occ_blocks::cpu.inst 661.144399 # Average occupied blocks per requestor
415 system.cpu.icache.tags.occ_percent::cpu.inst 0.322824 # Average percentage of cache occupancy
416 system.cpu.icache.tags.occ_percent::total 0.322824 # Average percentage of cache occupancy
417 system.cpu.icache.tags.occ_task_id_blocks::1024 791 # Occupied blocks per task id
418 system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id
419 system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id
420 system.cpu.icache.tags.age_task_id_blocks_1024::4 754 # Occupied blocks per task id
421 system.cpu.icache.tags.occ_task_id_percent::1024 0.386230 # Percentage of cache occupancy per task id
422 system.cpu.icache.tags.tag_accesses 929725166 # Number of tag accesses
423 system.cpu.icache.tags.data_accesses 929725166 # Number of data accesses
424 system.cpu.icache.ReadReq_hits::cpu.inst 464861353 # number of ReadReq hits
425 system.cpu.icache.ReadReq_hits::total 464861353 # number of ReadReq hits
426 system.cpu.icache.demand_hits::cpu.inst 464861353 # number of demand (read+write) hits
427 system.cpu.icache.demand_hits::total 464861353 # number of demand (read+write) hits
428 system.cpu.icache.overall_hits::cpu.inst 464861353 # number of overall hits
429 system.cpu.icache.overall_hits::total 464861353 # number of overall hits
430 system.cpu.icache.ReadReq_misses::cpu.inst 820 # number of ReadReq misses
431 system.cpu.icache.ReadReq_misses::total 820 # number of ReadReq misses
432 system.cpu.icache.demand_misses::cpu.inst 820 # number of demand (read+write) misses
433 system.cpu.icache.demand_misses::total 820 # number of demand (read+write) misses
434 system.cpu.icache.overall_misses::cpu.inst 820 # number of overall misses
435 system.cpu.icache.overall_misses::total 820 # number of overall misses
436 system.cpu.icache.ReadReq_miss_latency::cpu.inst 59141749 # number of ReadReq miss cycles
437 system.cpu.icache.ReadReq_miss_latency::total 59141749 # number of ReadReq miss cycles
438 system.cpu.icache.demand_miss_latency::cpu.inst 59141749 # number of demand (read+write) miss cycles
439 system.cpu.icache.demand_miss_latency::total 59141749 # number of demand (read+write) miss cycles
440 system.cpu.icache.overall_miss_latency::cpu.inst 59141749 # number of overall miss cycles
441 system.cpu.icache.overall_miss_latency::total 59141749 # number of overall miss cycles
442 system.cpu.icache.ReadReq_accesses::cpu.inst 464862173 # number of ReadReq accesses(hits+misses)
443 system.cpu.icache.ReadReq_accesses::total 464862173 # number of ReadReq accesses(hits+misses)
444 system.cpu.icache.demand_accesses::cpu.inst 464862173 # number of demand (read+write) accesses
445 system.cpu.icache.demand_accesses::total 464862173 # number of demand (read+write) accesses
446 system.cpu.icache.overall_accesses::cpu.inst 464862173 # number of overall (read+write) accesses
447 system.cpu.icache.overall_accesses::total 464862173 # number of overall (read+write) accesses
448 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses
449 system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses
450 system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses
451 system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses
452 system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses
453 system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses
454 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72124.084146 # average ReadReq miss latency
455 system.cpu.icache.ReadReq_avg_miss_latency::total 72124.084146 # average ReadReq miss latency
456 system.cpu.icache.demand_avg_miss_latency::cpu.inst 72124.084146 # average overall miss latency
457 system.cpu.icache.demand_avg_miss_latency::total 72124.084146 # average overall miss latency
458 system.cpu.icache.overall_avg_miss_latency::cpu.inst 72124.084146 # average overall miss latency
459 system.cpu.icache.overall_avg_miss_latency::total 72124.084146 # average overall miss latency
460 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
461 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
462 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
463 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
464 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
465 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
466 system.cpu.icache.fast_writes 0 # number of fast writes performed
467 system.cpu.icache.cache_copies 0 # number of cache copies performed
468 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 820 # number of ReadReq MSHR misses
469 system.cpu.icache.ReadReq_mshr_misses::total 820 # number of ReadReq MSHR misses
470 system.cpu.icache.demand_mshr_misses::cpu.inst 820 # number of demand (read+write) MSHR misses
471 system.cpu.icache.demand_mshr_misses::total 820 # number of demand (read+write) MSHR misses
472 system.cpu.icache.overall_mshr_misses::cpu.inst 820 # number of overall MSHR misses
473 system.cpu.icache.overall_mshr_misses::total 820 # number of overall MSHR misses
474 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 57178251 # number of ReadReq MSHR miss cycles
475 system.cpu.icache.ReadReq_mshr_miss_latency::total 57178251 # number of ReadReq MSHR miss cycles
476 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 57178251 # number of demand (read+write) MSHR miss cycles
477 system.cpu.icache.demand_mshr_miss_latency::total 57178251 # number of demand (read+write) MSHR miss cycles
478 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 57178251 # number of overall MSHR miss cycles
479 system.cpu.icache.overall_mshr_miss_latency::total 57178251 # number of overall MSHR miss cycles
480 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses
481 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses
482 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses
483 system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses
484 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses
485 system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
486 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69729.574390 # average ReadReq mshr miss latency
487 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69729.574390 # average ReadReq mshr miss latency
488 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69729.574390 # average overall mshr miss latency
489 system.cpu.icache.demand_avg_mshr_miss_latency::total 69729.574390 # average overall mshr miss latency
490 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69729.574390 # average overall mshr miss latency
491 system.cpu.icache.overall_avg_mshr_miss_latency::total 69729.574390 # average overall mshr miss latency
492 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
493 system.cpu.toL2Bus.trans_dist::ReadReq 7336783 # Transaction distribution
494 system.cpu.toL2Bus.trans_dist::ReadResp 7336783 # Transaction distribution
495 system.cpu.toL2Bus.trans_dist::Writeback 3700640 # Transaction distribution
496 system.cpu.toL2Bus.trans_dist::ReadExReq 1890869 # Transaction distribution
497 system.cpu.toL2Bus.trans_dist::ReadExResp 1890869 # Transaction distribution
498 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1640 # Packet count per connected master and slave (bytes)
499 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22154304 # Packet count per connected master and slave (bytes)
500 system.cpu.toL2Bus.pkt_count::total 22155944 # Packet count per connected master and slave (bytes)
501 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52480 # Cumulative packet size per connected master and slave (bytes)
502 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827358208 # Cumulative packet size per connected master and slave (bytes)
503 system.cpu.toL2Bus.pkt_size::total 827410688 # Cumulative packet size per connected master and slave (bytes)
504 system.cpu.toL2Bus.snoops 0 # Total snoops (count)
505 system.cpu.toL2Bus.snoop_fanout::samples 12928292 # Request fanout histogram
506 system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
507 system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
508 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
509 system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
510 system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
511 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
512 system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
513 system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
514 system.cpu.toL2Bus.snoop_fanout::5 12928292 100.00% 100.00% # Request fanout histogram
515 system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
516 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
517 system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
518 system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
519 system.cpu.toL2Bus.snoop_fanout::total 12928292 # Request fanout histogram
520 system.cpu.toL2Bus.reqLayer0.occupancy 10164786000 # Layer occupancy (ticks)
521 system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
522 system.cpu.toL2Bus.respLayer0.occupancy 1391749 # Layer occupancy (ticks)
523 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
524 system.cpu.toL2Bus.respLayer1.occupancy 14185031745 # Layer occupancy (ticks)
525 system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%)
526 system.cpu.l2cache.tags.replacements 2022796 # number of replacements
527 system.cpu.l2cache.tags.tagsinuse 31252.383158 # Cycle average of tags in use
528 system.cpu.l2cache.tags.total_refs 8984119 # Total number of references to valid blocks.
529 system.cpu.l2cache.tags.sampled_refs 2052571 # Sample count of references to valid blocks.
530 system.cpu.l2cache.tags.avg_refs 4.377008 # Average number of references to valid blocks.
531 system.cpu.l2cache.tags.warmup_cycle 58953869250 # Cycle when the warmup percentage was hit.
532 system.cpu.l2cache.tags.occ_blocks::writebacks 14967.342328 # Average occupied blocks per requestor
533 system.cpu.l2cache.tags.occ_blocks::cpu.inst 16285.040830 # Average occupied blocks per requestor
534 system.cpu.l2cache.tags.occ_percent::writebacks 0.456767 # Average percentage of cache occupancy
535 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.496980 # Average percentage of cache occupancy
536 system.cpu.l2cache.tags.occ_percent::total 0.953747 # Average percentage of cache occupancy
537 system.cpu.l2cache.tags.occ_task_id_blocks::1024 29775 # Occupied blocks per task id
538 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id
539 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id
540 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1248 # Occupied blocks per task id
541 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12849 # Occupied blocks per task id
542 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15556 # Occupied blocks per task id
543 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908661 # Percentage of cache occupancy per task id
544 system.cpu.l2cache.tags.tag_accesses 107369776 # Number of tag accesses
545 system.cpu.l2cache.tags.data_accesses 107369776 # Number of data accesses
546 system.cpu.l2cache.ReadReq_hits::cpu.inst 6081291 # number of ReadReq hits
547 system.cpu.l2cache.ReadReq_hits::total 6081291 # number of ReadReq hits
548 system.cpu.l2cache.Writeback_hits::writebacks 3700640 # number of Writeback hits
549 system.cpu.l2cache.Writeback_hits::total 3700640 # number of Writeback hits
550 system.cpu.l2cache.ReadExReq_hits::cpu.inst 1090856 # number of ReadExReq hits
551 system.cpu.l2cache.ReadExReq_hits::total 1090856 # number of ReadExReq hits
552 system.cpu.l2cache.demand_hits::cpu.inst 7172147 # number of demand (read+write) hits
553 system.cpu.l2cache.demand_hits::total 7172147 # number of demand (read+write) hits
554 system.cpu.l2cache.overall_hits::cpu.inst 7172147 # number of overall hits
555 system.cpu.l2cache.overall_hits::total 7172147 # number of overall hits
556 system.cpu.l2cache.ReadReq_misses::cpu.inst 1255492 # number of ReadReq misses
557 system.cpu.l2cache.ReadReq_misses::total 1255492 # number of ReadReq misses
558 system.cpu.l2cache.ReadExReq_misses::cpu.inst 800013 # number of ReadExReq misses
559 system.cpu.l2cache.ReadExReq_misses::total 800013 # number of ReadExReq misses
560 system.cpu.l2cache.demand_misses::cpu.inst 2055505 # number of demand (read+write) misses
561 system.cpu.l2cache.demand_misses::total 2055505 # number of demand (read+write) misses
562 system.cpu.l2cache.overall_misses::cpu.inst 2055505 # number of overall misses
563 system.cpu.l2cache.overall_misses::total 2055505 # number of overall misses
564 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100333400500 # number of ReadReq miss cycles
565 system.cpu.l2cache.ReadReq_miss_latency::total 100333400500 # number of ReadReq miss cycles
566 system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 64526294750 # number of ReadExReq miss cycles
567 system.cpu.l2cache.ReadExReq_miss_latency::total 64526294750 # number of ReadExReq miss cycles
568 system.cpu.l2cache.demand_miss_latency::cpu.inst 164859695250 # number of demand (read+write) miss cycles
569 system.cpu.l2cache.demand_miss_latency::total 164859695250 # number of demand (read+write) miss cycles
570 system.cpu.l2cache.overall_miss_latency::cpu.inst 164859695250 # number of overall miss cycles
571 system.cpu.l2cache.overall_miss_latency::total 164859695250 # number of overall miss cycles
572 system.cpu.l2cache.ReadReq_accesses::cpu.inst 7336783 # number of ReadReq accesses(hits+misses)
573 system.cpu.l2cache.ReadReq_accesses::total 7336783 # number of ReadReq accesses(hits+misses)
574 system.cpu.l2cache.Writeback_accesses::writebacks 3700640 # number of Writeback accesses(hits+misses)
575 system.cpu.l2cache.Writeback_accesses::total 3700640 # number of Writeback accesses(hits+misses)
576 system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1890869 # number of ReadExReq accesses(hits+misses)
577 system.cpu.l2cache.ReadExReq_accesses::total 1890869 # number of ReadExReq accesses(hits+misses)
578 system.cpu.l2cache.demand_accesses::cpu.inst 9227652 # number of demand (read+write) accesses
579 system.cpu.l2cache.demand_accesses::total 9227652 # number of demand (read+write) accesses
580 system.cpu.l2cache.overall_accesses::cpu.inst 9227652 # number of overall (read+write) accesses
581 system.cpu.l2cache.overall_accesses::total 9227652 # number of overall (read+write) accesses
582 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.171123 # miss rate for ReadReq accesses
583 system.cpu.l2cache.ReadReq_miss_rate::total 0.171123 # miss rate for ReadReq accesses
584 system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.423093 # miss rate for ReadExReq accesses
585 system.cpu.l2cache.ReadExReq_miss_rate::total 0.423093 # miss rate for ReadExReq accesses
586 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.222755 # miss rate for demand accesses
587 system.cpu.l2cache.demand_miss_rate::total 0.222755 # miss rate for demand accesses
588 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.222755 # miss rate for overall accesses
589 system.cpu.l2cache.overall_miss_rate::total 0.222755 # miss rate for overall accesses
590 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79915.603206 # average ReadReq miss latency
591 system.cpu.l2cache.ReadReq_avg_miss_latency::total 79915.603206 # average ReadReq miss latency
592 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80656.557768 # average ReadExReq miss latency
593 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80656.557768 # average ReadExReq miss latency
594 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80203.986490 # average overall miss latency
595 system.cpu.l2cache.demand_avg_miss_latency::total 80203.986490 # average overall miss latency
596 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80203.986490 # average overall miss latency
597 system.cpu.l2cache.overall_avg_miss_latency::total 80203.986490 # average overall miss latency
598 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
599 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
600 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
601 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
602 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
603 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
604 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
605 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
606 system.cpu.l2cache.writebacks::writebacks 1046381 # number of writebacks
607 system.cpu.l2cache.writebacks::total 1046381 # number of writebacks
608 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 6 # number of ReadReq MSHR hits
609 system.cpu.l2cache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits
610 system.cpu.l2cache.demand_mshr_hits::cpu.inst 6 # number of demand (read+write) MSHR hits
611 system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits
612 system.cpu.l2cache.overall_mshr_hits::cpu.inst 6 # number of overall MSHR hits
613 system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits
614 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1255486 # number of ReadReq MSHR misses
615 system.cpu.l2cache.ReadReq_mshr_misses::total 1255486 # number of ReadReq MSHR misses
616 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 800013 # number of ReadExReq MSHR misses
617 system.cpu.l2cache.ReadExReq_mshr_misses::total 800013 # number of ReadExReq MSHR misses
618 system.cpu.l2cache.demand_mshr_misses::cpu.inst 2055499 # number of demand (read+write) MSHR misses
619 system.cpu.l2cache.demand_mshr_misses::total 2055499 # number of demand (read+write) MSHR misses
620 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2055499 # number of overall MSHR misses
621 system.cpu.l2cache.overall_mshr_misses::total 2055499 # number of overall MSHR misses
622 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 84544683250 # number of ReadReq MSHR miss cycles
623 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84544683250 # number of ReadReq MSHR miss cycles
624 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 54440940250 # number of ReadExReq MSHR miss cycles
625 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54440940250 # number of ReadExReq MSHR miss cycles
626 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 138985623500 # number of demand (read+write) MSHR miss cycles
627 system.cpu.l2cache.demand_mshr_miss_latency::total 138985623500 # number of demand (read+write) MSHR miss cycles
628 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 138985623500 # number of overall MSHR miss cycles
629 system.cpu.l2cache.overall_mshr_miss_latency::total 138985623500 # number of overall MSHR miss cycles
630 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.171122 # mshr miss rate for ReadReq accesses
631 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171122 # mshr miss rate for ReadReq accesses
632 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.423093 # mshr miss rate for ReadExReq accesses
633 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423093 # mshr miss rate for ReadExReq accesses
634 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.222754 # mshr miss rate for demand accesses
635 system.cpu.l2cache.demand_mshr_miss_rate::total 0.222754 # mshr miss rate for demand accesses
636 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.222754 # mshr miss rate for overall accesses
637 system.cpu.l2cache.overall_mshr_miss_rate::total 0.222754 # mshr miss rate for overall accesses
638 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67340.203913 # average ReadReq mshr miss latency
639 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67340.203913 # average ReadReq mshr miss latency
640 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 68050.069499 # average ReadExReq mshr miss latency
641 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68050.069499 # average ReadExReq mshr miss latency
642 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67616.488016 # average overall mshr miss latency
643 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67616.488016 # average overall mshr miss latency
644 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67616.488016 # average overall mshr miss latency
645 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67616.488016 # average overall mshr miss latency
646 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
647 system.cpu.dcache.tags.replacements 9222736 # number of replacements
648 system.cpu.dcache.tags.tagsinuse 4085.561884 # Cycle average of tags in use
649 system.cpu.dcache.tags.total_refs 624006676 # Total number of references to valid blocks.
650 system.cpu.dcache.tags.sampled_refs 9226832 # Sample count of references to valid blocks.
651 system.cpu.dcache.tags.avg_refs 67.629569 # Average number of references to valid blocks.
652 system.cpu.dcache.tags.warmup_cycle 9704965000 # Cycle when the warmup percentage was hit.
653 system.cpu.dcache.tags.occ_blocks::cpu.inst 4085.561884 # Average occupied blocks per requestor
654 system.cpu.dcache.tags.occ_percent::cpu.inst 0.997452 # Average percentage of cache occupancy
655 system.cpu.dcache.tags.occ_percent::total 0.997452 # Average percentage of cache occupancy
656 system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
657 system.cpu.dcache.tags.age_task_id_blocks_1024::0 280 # Occupied blocks per task id
658 system.cpu.dcache.tags.age_task_id_blocks_1024::1 1316 # Occupied blocks per task id
659 system.cpu.dcache.tags.age_task_id_blocks_1024::2 2439 # Occupied blocks per task id
660 system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id
661 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
662 system.cpu.dcache.tags.tag_accesses 1276393554 # Number of tag accesses
663 system.cpu.dcache.tags.data_accesses 1276393554 # Number of data accesses
664 system.cpu.dcache.ReadReq_hits::cpu.inst 453661018 # number of ReadReq hits
665 system.cpu.dcache.ReadReq_hits::total 453661018 # number of ReadReq hits
666 system.cpu.dcache.WriteReq_hits::cpu.inst 170345536 # number of WriteReq hits
667 system.cpu.dcache.WriteReq_hits::total 170345536 # number of WriteReq hits
668 system.cpu.dcache.LoadLockedReq_hits::cpu.inst 61 # number of LoadLockedReq hits
669 system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits
670 system.cpu.dcache.StoreCondReq_hits::cpu.inst 61 # number of StoreCondReq hits
671 system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
672 system.cpu.dcache.demand_hits::cpu.inst 624006554 # number of demand (read+write) hits
673 system.cpu.dcache.demand_hits::total 624006554 # number of demand (read+write) hits
674 system.cpu.dcache.overall_hits::cpu.inst 624006554 # number of overall hits
675 system.cpu.dcache.overall_hits::total 624006554 # number of overall hits
676 system.cpu.dcache.ReadReq_misses::cpu.inst 7336174 # number of ReadReq misses
677 system.cpu.dcache.ReadReq_misses::total 7336174 # number of ReadReq misses
678 system.cpu.dcache.WriteReq_misses::cpu.inst 2240511 # number of WriteReq misses
679 system.cpu.dcache.WriteReq_misses::total 2240511 # number of WriteReq misses
680 system.cpu.dcache.demand_misses::cpu.inst 9576685 # number of demand (read+write) misses
681 system.cpu.dcache.demand_misses::total 9576685 # number of demand (read+write) misses
682 system.cpu.dcache.overall_misses::cpu.inst 9576685 # number of overall misses
683 system.cpu.dcache.overall_misses::total 9576685 # number of overall misses
684 system.cpu.dcache.ReadReq_miss_latency::cpu.inst 183520141245 # number of ReadReq miss cycles
685 system.cpu.dcache.ReadReq_miss_latency::total 183520141245 # number of ReadReq miss cycles
686 system.cpu.dcache.WriteReq_miss_latency::cpu.inst 101423015250 # number of WriteReq miss cycles
687 system.cpu.dcache.WriteReq_miss_latency::total 101423015250 # number of WriteReq miss cycles
688 system.cpu.dcache.demand_miss_latency::cpu.inst 284943156495 # number of demand (read+write) miss cycles
689 system.cpu.dcache.demand_miss_latency::total 284943156495 # number of demand (read+write) miss cycles
690 system.cpu.dcache.overall_miss_latency::cpu.inst 284943156495 # number of overall miss cycles
691 system.cpu.dcache.overall_miss_latency::total 284943156495 # number of overall miss cycles
692 system.cpu.dcache.ReadReq_accesses::cpu.inst 460997192 # number of ReadReq accesses(hits+misses)
693 system.cpu.dcache.ReadReq_accesses::total 460997192 # number of ReadReq accesses(hits+misses)
694 system.cpu.dcache.WriteReq_accesses::cpu.inst 172586047 # number of WriteReq accesses(hits+misses)
695 system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
696 system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 61 # number of LoadLockedReq accesses(hits+misses)
697 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
698 system.cpu.dcache.StoreCondReq_accesses::cpu.inst 61 # number of StoreCondReq accesses(hits+misses)
699 system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
700 system.cpu.dcache.demand_accesses::cpu.inst 633583239 # number of demand (read+write) accesses
701 system.cpu.dcache.demand_accesses::total 633583239 # number of demand (read+write) accesses
702 system.cpu.dcache.overall_accesses::cpu.inst 633583239 # number of overall (read+write) accesses
703 system.cpu.dcache.overall_accesses::total 633583239 # number of overall (read+write) accesses
704 system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.015914 # miss rate for ReadReq accesses
705 system.cpu.dcache.ReadReq_miss_rate::total 0.015914 # miss rate for ReadReq accesses
706 system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012982 # miss rate for WriteReq accesses
707 system.cpu.dcache.WriteReq_miss_rate::total 0.012982 # miss rate for WriteReq accesses
708 system.cpu.dcache.demand_miss_rate::cpu.inst 0.015115 # miss rate for demand accesses
709 system.cpu.dcache.demand_miss_rate::total 0.015115 # miss rate for demand accesses
710 system.cpu.dcache.overall_miss_rate::cpu.inst 0.015115 # miss rate for overall accesses
711 system.cpu.dcache.overall_miss_rate::total 0.015115 # miss rate for overall accesses
712 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25015.783601 # average ReadReq miss latency
713 system.cpu.dcache.ReadReq_avg_miss_latency::total 25015.783601 # average ReadReq miss latency
714 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45267.805090 # average WriteReq miss latency
715 system.cpu.dcache.WriteReq_avg_miss_latency::total 45267.805090 # average WriteReq miss latency
716 system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29753.840342 # average overall miss latency
717 system.cpu.dcache.demand_avg_miss_latency::total 29753.840342 # average overall miss latency
718 system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29753.840342 # average overall miss latency
719 system.cpu.dcache.overall_avg_miss_latency::total 29753.840342 # average overall miss latency
720 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
721 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
722 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
723 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
724 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
725 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
726 system.cpu.dcache.fast_writes 0 # number of fast writes performed
727 system.cpu.dcache.cache_copies 0 # number of cache copies performed
728 system.cpu.dcache.writebacks::writebacks 3700640 # number of writebacks
729 system.cpu.dcache.writebacks::total 3700640 # number of writebacks
730 system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 211 # number of ReadReq MSHR hits
731 system.cpu.dcache.ReadReq_mshr_hits::total 211 # number of ReadReq MSHR hits
732 system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 349642 # number of WriteReq MSHR hits
733 system.cpu.dcache.WriteReq_mshr_hits::total 349642 # number of WriteReq MSHR hits
734 system.cpu.dcache.demand_mshr_hits::cpu.inst 349853 # number of demand (read+write) MSHR hits
735 system.cpu.dcache.demand_mshr_hits::total 349853 # number of demand (read+write) MSHR hits
736 system.cpu.dcache.overall_mshr_hits::cpu.inst 349853 # number of overall MSHR hits
737 system.cpu.dcache.overall_mshr_hits::total 349853 # number of overall MSHR hits
738 system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7335963 # number of ReadReq MSHR misses
739 system.cpu.dcache.ReadReq_mshr_misses::total 7335963 # number of ReadReq MSHR misses
740 system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1890869 # number of WriteReq MSHR misses
741 system.cpu.dcache.WriteReq_mshr_misses::total 1890869 # number of WriteReq MSHR misses
742 system.cpu.dcache.demand_mshr_misses::cpu.inst 9226832 # number of demand (read+write) MSHR misses
743 system.cpu.dcache.demand_mshr_misses::total 9226832 # number of demand (read+write) MSHR misses
744 system.cpu.dcache.overall_mshr_misses::cpu.inst 9226832 # number of overall MSHR misses
745 system.cpu.dcache.overall_mshr_misses::total 9226832 # number of overall MSHR misses
746 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 168431190255 # number of ReadReq MSHR miss cycles
747 system.cpu.dcache.ReadReq_mshr_miss_latency::total 168431190255 # number of ReadReq MSHR miss cycles
748 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77354259500 # number of WriteReq MSHR miss cycles
749 system.cpu.dcache.WriteReq_mshr_miss_latency::total 77354259500 # number of WriteReq MSHR miss cycles
750 system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 245785449755 # number of demand (read+write) MSHR miss cycles
751 system.cpu.dcache.demand_mshr_miss_latency::total 245785449755 # number of demand (read+write) MSHR miss cycles
752 system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 245785449755 # number of overall MSHR miss cycles
753 system.cpu.dcache.overall_mshr_miss_latency::total 245785449755 # number of overall MSHR miss cycles
754 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.015913 # mshr miss rate for ReadReq accesses
755 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015913 # mshr miss rate for ReadReq accesses
756 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.010956 # mshr miss rate for WriteReq accesses
757 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses
758 system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014563 # mshr miss rate for demand accesses
759 system.cpu.dcache.demand_mshr_miss_rate::total 0.014563 # mshr miss rate for demand accesses
760 system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014563 # mshr miss rate for overall accesses
761 system.cpu.dcache.overall_mshr_miss_rate::total 0.014563 # mshr miss rate for overall accesses
762 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22959.656456 # average ReadReq mshr miss latency
763 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22959.656456 # average ReadReq mshr miss latency
764 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40909.369978 # average WriteReq mshr miss latency
765 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40909.369978 # average WriteReq mshr miss latency
766 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26638.119103 # average overall mshr miss latency
767 system.cpu.dcache.demand_avg_mshr_miss_latency::total 26638.119103 # average overall mshr miss latency
768 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26638.119103 # average overall mshr miss latency
769 system.cpu.dcache.overall_avg_mshr_miss_latency::total 26638.119103 # average overall mshr miss latency
770 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
772 ---------- End Simulation Statistics ----------
projects / gem5.git / blob