2 ---------- Begin Simulation Statistics ----------
3 final_tick 1134079016500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
4 host_inst_rate 227824 # Simulator instruction rate (inst/s)
5 host_mem_usage 293824 # Number of bytes of host memory used
6 host_op_rate 254155 # Simulator op (including micro ops) rate (op/s)
7 host_seconds 6779.62 # Real time elapsed on the host
8 host_tick_rate 167277674 # Simulator tick rate (ticks/s)
9 sim_freq 1000000000000 # Frequency of simulated ticks
10 sim_insts 1544563087 # Number of instructions simulated
11 sim_ops 1723073900 # Number of ops (including micro ops) simulated
12 sim_seconds 1.134079 # Number of seconds simulated
13 sim_ticks 1134079016500 # Number of ticks simulated
14 system.clk_domain.clock 1000 # Clock period in ticks
15 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
16 system.cpu.branchPred.BTBHitPct 87.938151 # BTB Hit Percentage
17 system.cpu.branchPred.BTBHits 122192107 # Number of BTB hits
18 system.cpu.branchPred.BTBLookups 138952327 # Number of BTB lookups
19 system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions.
20 system.cpu.branchPred.condIncorrect 14597136 # Number of conditional branches incorrect
21 system.cpu.branchPred.condPredicted 197361074 # Number of conditional branches predicted
22 system.cpu.branchPred.lookups 250285818 # Number of BP lookups
23 system.cpu.branchPred.usedRAS 13226889 # Number of times the RAS was used to get a target.
24 system.cpu.committedInsts 1544563087 # Number of instructions committed
25 system.cpu.committedOps 1723073900 # Number of ops (including micro ops) committed
26 system.cpu.cpi 1.468479 # CPI: cycles per instruction
27 system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 61 # number of LoadLockedReq accesses(hits+misses)
28 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
29 system.cpu.dcache.LoadLockedReq_hits::cpu.inst 61 # number of LoadLockedReq hits
30 system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits
31 system.cpu.dcache.ReadReq_accesses::cpu.inst 485955700 # number of ReadReq accesses(hits+misses)
32 system.cpu.dcache.ReadReq_accesses::total 485955700 # number of ReadReq accesses(hits+misses)
33 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24973.063686 # average ReadReq miss latency
34 system.cpu.dcache.ReadReq_avg_miss_latency::total 24973.063686 # average ReadReq miss latency
35 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22917.493937 # average ReadReq mshr miss latency
36 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22917.493937 # average ReadReq mshr miss latency
37 system.cpu.dcache.ReadReq_hits::cpu.inst 478618690 # number of ReadReq hits
38 system.cpu.dcache.ReadReq_hits::total 478618690 # number of ReadReq hits
39 system.cpu.dcache.ReadReq_miss_latency::cpu.inst 183227617996 # number of ReadReq miss cycles
40 system.cpu.dcache.ReadReq_miss_latency::total 183227617996 # number of ReadReq miss cycles
41 system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.015098 # miss rate for ReadReq accesses
42 system.cpu.dcache.ReadReq_miss_rate::total 0.015098 # miss rate for ReadReq accesses
43 system.cpu.dcache.ReadReq_misses::cpu.inst 7337010 # number of ReadReq misses
44 system.cpu.dcache.ReadReq_misses::total 7337010 # number of ReadReq misses
45 system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 222 # number of ReadReq MSHR hits
46 system.cpu.dcache.ReadReq_mshr_hits::total 222 # number of ReadReq MSHR hits
47 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 168140794504 # number of ReadReq MSHR miss cycles
48 system.cpu.dcache.ReadReq_mshr_miss_latency::total 168140794504 # number of ReadReq MSHR miss cycles
49 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.015098 # mshr miss rate for ReadReq accesses
50 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015098 # mshr miss rate for ReadReq accesses
51 system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7336788 # number of ReadReq MSHR misses
52 system.cpu.dcache.ReadReq_mshr_misses::total 7336788 # number of ReadReq MSHR misses
53 system.cpu.dcache.StoreCondReq_accesses::cpu.inst 61 # number of StoreCondReq accesses(hits+misses)
54 system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
55 system.cpu.dcache.StoreCondReq_hits::cpu.inst 61 # number of StoreCondReq hits
56 system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
57 system.cpu.dcache.WriteReq_accesses::cpu.inst 172586047 # number of WriteReq accesses(hits+misses)
58 system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
59 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45215.138055 # average WriteReq miss latency
60 system.cpu.dcache.WriteReq_avg_miss_latency::total 45215.138055 # average WriteReq miss latency
61 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40855.687627 # average WriteReq mshr miss latency
62 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40855.687627 # average WriteReq mshr miss latency
63 system.cpu.dcache.WriteReq_hits::cpu.inst 170348428 # number of WriteReq hits
64 system.cpu.dcache.WriteReq_hits::total 170348428 # number of WriteReq hits
65 system.cpu.dcache.WriteReq_miss_latency::cpu.inst 101174252000 # number of WriteReq miss cycles
66 system.cpu.dcache.WriteReq_miss_latency::total 101174252000 # number of WriteReq miss cycles
67 system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012965 # miss rate for WriteReq accesses
68 system.cpu.dcache.WriteReq_miss_rate::total 0.012965 # miss rate for WriteReq accesses
69 system.cpu.dcache.WriteReq_misses::cpu.inst 2237619 # number of WriteReq misses
70 system.cpu.dcache.WriteReq_misses::total 2237619 # number of WriteReq misses
71 system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 346681 # number of WriteReq MSHR hits
72 system.cpu.dcache.WriteReq_mshr_hits::total 346681 # number of WriteReq MSHR hits
73 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77255572250 # number of WriteReq MSHR miss cycles
74 system.cpu.dcache.WriteReq_mshr_miss_latency::total 77255572250 # number of WriteReq MSHR miss cycles
75 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.010956 # mshr miss rate for WriteReq accesses
76 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses
77 system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1890938 # number of WriteReq MSHR misses
78 system.cpu.dcache.WriteReq_mshr_misses::total 1890938 # number of WriteReq MSHR misses
79 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
80 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
81 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
82 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
83 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
84 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
85 system.cpu.dcache.cache_copies 0 # number of cache copies performed
86 system.cpu.dcache.demand_accesses::cpu.inst 658541747 # number of demand (read+write) accesses
87 system.cpu.dcache.demand_accesses::total 658541747 # number of demand (read+write) accesses
88 system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29703.696091 # average overall miss latency
89 system.cpu.dcache.demand_avg_miss_latency::total 29703.696091 # average overall miss latency
90 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26593.373790 # average overall mshr miss latency
91 system.cpu.dcache.demand_avg_mshr_miss_latency::total 26593.373790 # average overall mshr miss latency
92 system.cpu.dcache.demand_hits::cpu.inst 648967118 # number of demand (read+write) hits
93 system.cpu.dcache.demand_hits::total 648967118 # number of demand (read+write) hits
94 system.cpu.dcache.demand_miss_latency::cpu.inst 284401869996 # number of demand (read+write) miss cycles
95 system.cpu.dcache.demand_miss_latency::total 284401869996 # number of demand (read+write) miss cycles
96 system.cpu.dcache.demand_miss_rate::cpu.inst 0.014539 # miss rate for demand accesses
97 system.cpu.dcache.demand_miss_rate::total 0.014539 # miss rate for demand accesses
98 system.cpu.dcache.demand_misses::cpu.inst 9574629 # number of demand (read+write) misses
99 system.cpu.dcache.demand_misses::total 9574629 # number of demand (read+write) misses
100 system.cpu.dcache.demand_mshr_hits::cpu.inst 346903 # number of demand (read+write) MSHR hits
101 system.cpu.dcache.demand_mshr_hits::total 346903 # number of demand (read+write) MSHR hits
102 system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 245396366754 # number of demand (read+write) MSHR miss cycles
103 system.cpu.dcache.demand_mshr_miss_latency::total 245396366754 # number of demand (read+write) MSHR miss cycles
104 system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014012 # mshr miss rate for demand accesses
105 system.cpu.dcache.demand_mshr_miss_rate::total 0.014012 # mshr miss rate for demand accesses
106 system.cpu.dcache.demand_mshr_misses::cpu.inst 9227726 # number of demand (read+write) MSHR misses
107 system.cpu.dcache.demand_mshr_misses::total 9227726 # number of demand (read+write) MSHR misses
108 system.cpu.dcache.fast_writes 0 # number of fast writes performed
109 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
110 system.cpu.dcache.overall_accesses::cpu.inst 658541747 # number of overall (read+write) accesses
111 system.cpu.dcache.overall_accesses::total 658541747 # number of overall (read+write) accesses
112 system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29703.696091 # average overall miss latency
113 system.cpu.dcache.overall_avg_miss_latency::total 29703.696091 # average overall miss latency
114 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26593.373790 # average overall mshr miss latency
115 system.cpu.dcache.overall_avg_mshr_miss_latency::total 26593.373790 # average overall mshr miss latency
116 system.cpu.dcache.overall_hits::cpu.inst 648967118 # number of overall hits
117 system.cpu.dcache.overall_hits::total 648967118 # number of overall hits
118 system.cpu.dcache.overall_miss_latency::cpu.inst 284401869996 # number of overall miss cycles
119 system.cpu.dcache.overall_miss_latency::total 284401869996 # number of overall miss cycles
120 system.cpu.dcache.overall_miss_rate::cpu.inst 0.014539 # miss rate for overall accesses
121 system.cpu.dcache.overall_miss_rate::total 0.014539 # miss rate for overall accesses
122 system.cpu.dcache.overall_misses::cpu.inst 9574629 # number of overall misses
123 system.cpu.dcache.overall_misses::total 9574629 # number of overall misses
124 system.cpu.dcache.overall_mshr_hits::cpu.inst 346903 # number of overall MSHR hits
125 system.cpu.dcache.overall_mshr_hits::total 346903 # number of overall MSHR hits
126 system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 245396366754 # number of overall MSHR miss cycles
127 system.cpu.dcache.overall_mshr_miss_latency::total 245396366754 # number of overall MSHR miss cycles
128 system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014012 # mshr miss rate for overall accesses
129 system.cpu.dcache.overall_mshr_miss_rate::total 0.014012 # mshr miss rate for overall accesses
130 system.cpu.dcache.overall_mshr_misses::cpu.inst 9227726 # number of overall MSHR misses
131 system.cpu.dcache.overall_mshr_misses::total 9227726 # number of overall MSHR misses
132 system.cpu.dcache.tags.age_task_id_blocks_1024::0 257 # Occupied blocks per task id
133 system.cpu.dcache.tags.age_task_id_blocks_1024::1 1280 # Occupied blocks per task id
134 system.cpu.dcache.tags.age_task_id_blocks_1024::2 2489 # Occupied blocks per task id
135 system.cpu.dcache.tags.age_task_id_blocks_1024::3 70 # Occupied blocks per task id
136 system.cpu.dcache.tags.avg_refs 70.327970 # Average number of references to valid blocks.
137 system.cpu.dcache.tags.data_accesses 1326311464 # Number of data accesses
138 system.cpu.dcache.tags.occ_blocks::cpu.inst 4085.294010 # Average occupied blocks per requestor
139 system.cpu.dcache.tags.occ_percent::cpu.inst 0.997386 # Average percentage of cache occupancy
140 system.cpu.dcache.tags.occ_percent::total 0.997386 # Average percentage of cache occupancy
141 system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
142 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
143 system.cpu.dcache.tags.replacements 9223630 # number of replacements
144 system.cpu.dcache.tags.sampled_refs 9227726 # Sample count of references to valid blocks.
145 system.cpu.dcache.tags.tag_accesses 1326311464 # Number of tag accesses
146 system.cpu.dcache.tags.tagsinuse 4085.294010 # Cycle average of tags in use
147 system.cpu.dcache.tags.total_refs 648967240 # Total number of references to valid blocks.
148 system.cpu.dcache.tags.warmup_cycle 10338720250 # Cycle when the warmup percentage was hit.
149 system.cpu.dcache.writebacks::writebacks 3700800 # number of writebacks
150 system.cpu.dcache.writebacks::total 3700800 # number of writebacks
151 system.cpu.discardedOps 51251418 # Number of ops (including micro ops) which were discarded before commit
152 system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
153 system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
154 system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
155 system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
156 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
157 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
158 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
159 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
160 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
161 system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
162 system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
163 system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
164 system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
165 system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
166 system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
167 system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
168 system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
169 system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
170 system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
171 system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
172 system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
173 system.cpu.dtb.accesses 0 # DTB accesses
174 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
175 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
176 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
177 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
178 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
179 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
180 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
181 system.cpu.dtb.hits 0 # DTB hits
182 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
183 system.cpu.dtb.inst_hits 0 # ITB inst hits
184 system.cpu.dtb.inst_misses 0 # ITB inst misses
185 system.cpu.dtb.misses 0 # DTB misses
186 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
187 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
188 system.cpu.dtb.read_accesses 0 # DTB read accesses
189 system.cpu.dtb.read_hits 0 # DTB read hits
190 system.cpu.dtb.read_misses 0 # DTB read misses
191 system.cpu.dtb.write_accesses 0 # DTB write accesses
192 system.cpu.dtb.write_hits 0 # DTB write hits
193 system.cpu.dtb.write_misses 0 # DTB write misses
194 system.cpu.icache.ReadReq_accesses::cpu.inst 468616075 # number of ReadReq accesses(hits+misses)
195 system.cpu.icache.ReadReq_accesses::total 468616075 # number of ReadReq accesses(hits+misses)
196 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71218.824455 # average ReadReq miss latency
197 system.cpu.icache.ReadReq_avg_miss_latency::total 71218.824455 # average ReadReq miss latency
198 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68823.548426 # average ReadReq mshr miss latency
199 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68823.548426 # average ReadReq mshr miss latency
200 system.cpu.icache.ReadReq_hits::cpu.inst 468615249 # number of ReadReq hits
201 system.cpu.icache.ReadReq_hits::total 468615249 # number of ReadReq hits
202 system.cpu.icache.ReadReq_miss_latency::cpu.inst 58826749 # number of ReadReq miss cycles
203 system.cpu.icache.ReadReq_miss_latency::total 58826749 # number of ReadReq miss cycles
204 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses
205 system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses
206 system.cpu.icache.ReadReq_misses::cpu.inst 826 # number of ReadReq misses
207 system.cpu.icache.ReadReq_misses::total 826 # number of ReadReq misses
208 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 56848251 # number of ReadReq MSHR miss cycles
209 system.cpu.icache.ReadReq_mshr_miss_latency::total 56848251 # number of ReadReq MSHR miss cycles
210 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses
211 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses
212 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 826 # number of ReadReq MSHR misses
213 system.cpu.icache.ReadReq_mshr_misses::total 826 # number of ReadReq MSHR misses
214 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
215 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
216 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
217 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
218 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
219 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
220 system.cpu.icache.cache_copies 0 # number of cache copies performed
221 system.cpu.icache.demand_accesses::cpu.inst 468616075 # number of demand (read+write) accesses
222 system.cpu.icache.demand_accesses::total 468616075 # number of demand (read+write) accesses
223 system.cpu.icache.demand_avg_miss_latency::cpu.inst 71218.824455 # average overall miss latency
224 system.cpu.icache.demand_avg_miss_latency::total 71218.824455 # average overall miss latency
225 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68823.548426 # average overall mshr miss latency
226 system.cpu.icache.demand_avg_mshr_miss_latency::total 68823.548426 # average overall mshr miss latency
227 system.cpu.icache.demand_hits::cpu.inst 468615249 # number of demand (read+write) hits
228 system.cpu.icache.demand_hits::total 468615249 # number of demand (read+write) hits
229 system.cpu.icache.demand_miss_latency::cpu.inst 58826749 # number of demand (read+write) miss cycles
230 system.cpu.icache.demand_miss_latency::total 58826749 # number of demand (read+write) miss cycles
231 system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses
232 system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses
233 system.cpu.icache.demand_misses::cpu.inst 826 # number of demand (read+write) misses
234 system.cpu.icache.demand_misses::total 826 # number of demand (read+write) misses
235 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 56848251 # number of demand (read+write) MSHR miss cycles
236 system.cpu.icache.demand_mshr_miss_latency::total 56848251 # number of demand (read+write) MSHR miss cycles
237 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses
238 system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses
239 system.cpu.icache.demand_mshr_misses::cpu.inst 826 # number of demand (read+write) MSHR misses
240 system.cpu.icache.demand_mshr_misses::total 826 # number of demand (read+write) MSHR misses
241 system.cpu.icache.fast_writes 0 # number of fast writes performed
242 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
243 system.cpu.icache.overall_accesses::cpu.inst 468616075 # number of overall (read+write) accesses
244 system.cpu.icache.overall_accesses::total 468616075 # number of overall (read+write) accesses
245 system.cpu.icache.overall_avg_miss_latency::cpu.inst 71218.824455 # average overall miss latency
246 system.cpu.icache.overall_avg_miss_latency::total 71218.824455 # average overall miss latency
247 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68823.548426 # average overall mshr miss latency
248 system.cpu.icache.overall_avg_mshr_miss_latency::total 68823.548426 # average overall mshr miss latency
249 system.cpu.icache.overall_hits::cpu.inst 468615249 # number of overall hits
250 system.cpu.icache.overall_hits::total 468615249 # number of overall hits
251 system.cpu.icache.overall_miss_latency::cpu.inst 58826749 # number of overall miss cycles
252 system.cpu.icache.overall_miss_latency::total 58826749 # number of overall miss cycles
253 system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses
254 system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses
255 system.cpu.icache.overall_misses::cpu.inst 826 # number of overall misses
256 system.cpu.icache.overall_misses::total 826 # number of overall misses
257 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 56848251 # number of overall MSHR miss cycles
258 system.cpu.icache.overall_mshr_miss_latency::total 56848251 # number of overall MSHR miss cycles
259 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses
260 system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
261 system.cpu.icache.overall_mshr_misses::cpu.inst 826 # number of overall MSHR misses
262 system.cpu.icache.overall_mshr_misses::total 826 # number of overall MSHR misses
263 system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id
264 system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id
265 system.cpu.icache.tags.age_task_id_blocks_1024::4 760 # Occupied blocks per task id
266 system.cpu.icache.tags.avg_refs 567330.809927 # Average number of references to valid blocks.
267 system.cpu.icache.tags.data_accesses 937232976 # Number of data accesses
268 system.cpu.icache.tags.occ_blocks::cpu.inst 667.306532 # Average occupied blocks per requestor
269 system.cpu.icache.tags.occ_percent::cpu.inst 0.325833 # Average percentage of cache occupancy
270 system.cpu.icache.tags.occ_percent::total 0.325833 # Average percentage of cache occupancy
271 system.cpu.icache.tags.occ_task_id_blocks::1024 797 # Occupied blocks per task id
272 system.cpu.icache.tags.occ_task_id_percent::1024 0.389160 # Percentage of cache occupancy per task id
273 system.cpu.icache.tags.replacements 29 # number of replacements
274 system.cpu.icache.tags.sampled_refs 826 # Sample count of references to valid blocks.
275 system.cpu.icache.tags.tag_accesses 937232976 # Number of tag accesses
276 system.cpu.icache.tags.tagsinuse 667.306532 # Cycle average of tags in use
277 system.cpu.icache.tags.total_refs 468615249 # Total number of references to valid blocks.
278 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
279 system.cpu.idleCycles 378561103 # Total number of cycles that the CPU has spent unscheduled due to idling
280 system.cpu.ipc 0.680977 # IPC: instructions per cycle
281 system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
282 system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
283 system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
284 system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
285 system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
286 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
287 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
288 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
289 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
290 system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
291 system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
292 system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
293 system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
294 system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
295 system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
296 system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
297 system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
298 system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
299 system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
300 system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
301 system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
302 system.cpu.itb.accesses 0 # DTB accesses
303 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
304 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
305 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
306 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
307 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
308 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
309 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
310 system.cpu.itb.hits 0 # DTB hits
311 system.cpu.itb.inst_accesses 0 # ITB inst accesses
312 system.cpu.itb.inst_hits 0 # ITB inst hits
313 system.cpu.itb.inst_misses 0 # ITB inst misses
314 system.cpu.itb.misses 0 # DTB misses
315 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
316 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
317 system.cpu.itb.read_accesses 0 # DTB read accesses
318 system.cpu.itb.read_hits 0 # DTB read hits
319 system.cpu.itb.read_misses 0 # DTB read misses
320 system.cpu.itb.write_accesses 0 # DTB write accesses
321 system.cpu.itb.write_hits 0 # DTB write hits
322 system.cpu.itb.write_misses 0 # DTB write misses
323 system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1890938 # number of ReadExReq accesses(hits+misses)
324 system.cpu.l2cache.ReadExReq_accesses::total 1890938 # number of ReadExReq accesses(hits+misses)
325 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80530.523230 # average ReadExReq miss latency
326 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80530.523230 # average ReadExReq miss latency
327 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 67904.363586 # average ReadExReq mshr miss latency
328 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67904.363586 # average ReadExReq mshr miss latency
329 system.cpu.l2cache.ReadExReq_hits::cpu.inst 1090908 # number of ReadExReq hits
330 system.cpu.l2cache.ReadExReq_hits::total 1090908 # number of ReadExReq hits
331 system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 64426834500 # number of ReadExReq miss cycles
332 system.cpu.l2cache.ReadExReq_miss_latency::total 64426834500 # number of ReadExReq miss cycles
333 system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.423086 # miss rate for ReadExReq accesses
334 system.cpu.l2cache.ReadExReq_miss_rate::total 0.423086 # miss rate for ReadExReq accesses
335 system.cpu.l2cache.ReadExReq_misses::cpu.inst 800030 # number of ReadExReq misses
336 system.cpu.l2cache.ReadExReq_misses::total 800030 # number of ReadExReq misses
337 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 54325528000 # number of ReadExReq MSHR miss cycles
338 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54325528000 # number of ReadExReq MSHR miss cycles
339 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.423086 # mshr miss rate for ReadExReq accesses
340 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423086 # mshr miss rate for ReadExReq accesses
341 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 800030 # number of ReadExReq MSHR misses
342 system.cpu.l2cache.ReadExReq_mshr_misses::total 800030 # number of ReadExReq MSHR misses
343 system.cpu.l2cache.ReadReq_accesses::cpu.inst 7337614 # number of ReadReq accesses(hits+misses)
344 system.cpu.l2cache.ReadReq_accesses::total 7337614 # number of ReadReq accesses(hits+misses)
345 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79650.729800 # average ReadReq miss latency
346 system.cpu.l2cache.ReadReq_avg_miss_latency::total 79650.729800 # average ReadReq miss latency
347 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67079.515524 # average ReadReq mshr miss latency
348 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67079.515524 # average ReadReq mshr miss latency
349 system.cpu.l2cache.ReadReq_hits::cpu.inst 6081653 # number of ReadReq hits
350 system.cpu.l2cache.ReadReq_hits::total 6081653 # number of ReadReq hits
351 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100038210250 # number of ReadReq miss cycles
352 system.cpu.l2cache.ReadReq_miss_latency::total 100038210250 # number of ReadReq miss cycles
353 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.171167 # miss rate for ReadReq accesses
354 system.cpu.l2cache.ReadReq_miss_rate::total 0.171167 # miss rate for ReadReq accesses
355 system.cpu.l2cache.ReadReq_misses::cpu.inst 1255961 # number of ReadReq misses
356 system.cpu.l2cache.ReadReq_misses::total 1255961 # number of ReadReq misses
357 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits
358 system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits
359 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 84248920000 # number of ReadReq MSHR miss cycles
360 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84248920000 # number of ReadReq MSHR miss cycles
361 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.171167 # mshr miss rate for ReadReq accesses
362 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171167 # mshr miss rate for ReadReq accesses
363 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1255956 # number of ReadReq MSHR misses
364 system.cpu.l2cache.ReadReq_mshr_misses::total 1255956 # number of ReadReq MSHR misses
365 system.cpu.l2cache.Writeback_accesses::writebacks 3700800 # number of Writeback accesses(hits+misses)
366 system.cpu.l2cache.Writeback_accesses::total 3700800 # number of Writeback accesses(hits+misses)
367 system.cpu.l2cache.Writeback_hits::writebacks 3700800 # number of Writeback hits
368 system.cpu.l2cache.Writeback_hits::total 3700800 # number of Writeback hits
369 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
370 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
371 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
372 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
373 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
374 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
375 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
376 system.cpu.l2cache.demand_accesses::cpu.inst 9228552 # number of demand (read+write) accesses
377 system.cpu.l2cache.demand_accesses::total 9228552 # number of demand (read+write) accesses
378 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79993.076210 # average overall miss latency
379 system.cpu.l2cache.demand_avg_miss_latency::total 79993.076210 # average overall miss latency
380 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67400.482299 # average overall mshr miss latency
381 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67400.482299 # average overall mshr miss latency
382 system.cpu.l2cache.demand_hits::cpu.inst 7172561 # number of demand (read+write) hits
383 system.cpu.l2cache.demand_hits::total 7172561 # number of demand (read+write) hits
384 system.cpu.l2cache.demand_miss_latency::cpu.inst 164465044750 # number of demand (read+write) miss cycles
385 system.cpu.l2cache.demand_miss_latency::total 164465044750 # number of demand (read+write) miss cycles
386 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.222786 # miss rate for demand accesses
387 system.cpu.l2cache.demand_miss_rate::total 0.222786 # miss rate for demand accesses
388 system.cpu.l2cache.demand_misses::cpu.inst 2055991 # number of demand (read+write) misses
389 system.cpu.l2cache.demand_misses::total 2055991 # number of demand (read+write) misses
390 system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits
391 system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits
392 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 138574448000 # number of demand (read+write) MSHR miss cycles
393 system.cpu.l2cache.demand_mshr_miss_latency::total 138574448000 # number of demand (read+write) MSHR miss cycles
394 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.222785 # mshr miss rate for demand accesses
395 system.cpu.l2cache.demand_mshr_miss_rate::total 0.222785 # mshr miss rate for demand accesses
396 system.cpu.l2cache.demand_mshr_misses::cpu.inst 2055986 # number of demand (read+write) MSHR misses
397 system.cpu.l2cache.demand_mshr_misses::total 2055986 # number of demand (read+write) MSHR misses
398 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
399 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
400 system.cpu.l2cache.overall_accesses::cpu.inst 9228552 # number of overall (read+write) accesses
401 system.cpu.l2cache.overall_accesses::total 9228552 # number of overall (read+write) accesses
402 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79993.076210 # average overall miss latency
403 system.cpu.l2cache.overall_avg_miss_latency::total 79993.076210 # average overall miss latency
404 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67400.482299 # average overall mshr miss latency
405 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67400.482299 # average overall mshr miss latency
406 system.cpu.l2cache.overall_hits::cpu.inst 7172561 # number of overall hits
407 system.cpu.l2cache.overall_hits::total 7172561 # number of overall hits
408 system.cpu.l2cache.overall_miss_latency::cpu.inst 164465044750 # number of overall miss cycles
409 system.cpu.l2cache.overall_miss_latency::total 164465044750 # number of overall miss cycles
410 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.222786 # miss rate for overall accesses
411 system.cpu.l2cache.overall_miss_rate::total 0.222786 # miss rate for overall accesses
412 system.cpu.l2cache.overall_misses::cpu.inst 2055991 # number of overall misses
413 system.cpu.l2cache.overall_misses::total 2055991 # number of overall misses
414 system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits
415 system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits
416 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 138574448000 # number of overall MSHR miss cycles
417 system.cpu.l2cache.overall_mshr_miss_latency::total 138574448000 # number of overall MSHR miss cycles
418 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.222785 # mshr miss rate for overall accesses
419 system.cpu.l2cache.overall_mshr_miss_rate::total 0.222785 # mshr miss rate for overall accesses
420 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2055986 # number of overall MSHR misses
421 system.cpu.l2cache.overall_mshr_misses::total 2055986 # number of overall MSHR misses
422 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id
423 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id
424 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1208 # Occupied blocks per task id
425 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12891 # Occupied blocks per task id
426 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15554 # Occupied blocks per task id
427 system.cpu.l2cache.tags.avg_refs 4.376215 # Average number of references to valid blocks.
428 system.cpu.l2cache.tags.data_accesses 107378812 # Number of data accesses
429 system.cpu.l2cache.tags.occ_blocks::writebacks 14921.737919 # Average occupied blocks per requestor
430 system.cpu.l2cache.tags.occ_blocks::cpu.inst 16303.939645 # Average occupied blocks per requestor
431 system.cpu.l2cache.tags.occ_percent::writebacks 0.455375 # Average percentage of cache occupancy
432 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.497557 # Average percentage of cache occupancy
433 system.cpu.l2cache.tags.occ_percent::total 0.952932 # Average percentage of cache occupancy
434 system.cpu.l2cache.tags.occ_task_id_blocks::1024 29776 # Occupied blocks per task id
435 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908691 # Percentage of cache occupancy per task id
436 system.cpu.l2cache.tags.replacements 2023282 # number of replacements
437 system.cpu.l2cache.tags.sampled_refs 2053058 # Sample count of references to valid blocks.
438 system.cpu.l2cache.tags.tag_accesses 107378812 # Number of tag accesses
439 system.cpu.l2cache.tags.tagsinuse 31225.677564 # Cycle average of tags in use
440 system.cpu.l2cache.tags.total_refs 8984623 # Total number of references to valid blocks.
441 system.cpu.l2cache.tags.warmup_cycle 62285743250 # Cycle when the warmup percentage was hit.
442 system.cpu.l2cache.writebacks::writebacks 1046478 # number of writebacks
443 system.cpu.l2cache.writebacks::total 1046478 # number of writebacks
444 system.cpu.numCycles 2268158033 # number of cpu cycles simulated
445 system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
446 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
447 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
448 system.cpu.tickCycles 1889596930 # Number of cycles that the CPU actually ticked
449 system.cpu.toL2Bus.data_through_bus 827478528 # Total data (bytes)
450 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1652 # Packet count per connected master and slave (bytes)
451 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22156252 # Packet count per connected master and slave (bytes)
452 system.cpu.toL2Bus.pkt_count::total 22157904 # Packet count per connected master and slave (bytes)
453 system.cpu.toL2Bus.reqLayer0.occupancy 10165476000 # Layer occupancy (ticks)
454 system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
455 system.cpu.toL2Bus.respLayer0.occupancy 1402249 # Layer occupancy (ticks)
456 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
457 system.cpu.toL2Bus.respLayer1.occupancy 14183973746 # Layer occupancy (ticks)
458 system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%)
459 system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
460 system.cpu.toL2Bus.throughput 729648037 # Throughput (bytes/s)
461 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52864 # Cumulative packet size per connected master and slave (bytes)
462 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827425664 # Cumulative packet size per connected master and slave (bytes)
463 system.cpu.toL2Bus.tot_pkt_size::total 827478528 # Cumulative packet size per connected master and slave (bytes)
464 system.cpu.toL2Bus.trans_dist::ReadReq 7337614 # Transaction distribution
465 system.cpu.toL2Bus.trans_dist::ReadResp 7337614 # Transaction distribution
466 system.cpu.toL2Bus.trans_dist::Writeback 3700800 # Transaction distribution
467 system.cpu.toL2Bus.trans_dist::ReadExReq 1890938 # Transaction distribution
468 system.cpu.toL2Bus.trans_dist::ReadExResp 1890938 # Transaction distribution
469 system.cpu.workload.num_syscalls 46 # Number of system calls
470 system.cpu_clk_domain.clock 500 # Clock period in ticks
471 system.membus.data_through_bus 198557696 # Total data (bytes)
472 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5158450 # Packet count per connected master and slave (bytes)
473 system.membus.pkt_count::total 5158450 # Packet count per connected master and slave (bytes)
474 system.membus.reqLayer0.occupancy 12256366000 # Layer occupancy (ticks)
475 system.membus.reqLayer0.utilization 1.1 # Layer utilization (%)
476 system.membus.respLayer1.occupancy 19378736500 # Layer occupancy (ticks)
477 system.membus.respLayer1.utilization 1.7 # Layer utilization (%)
478 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
479 system.membus.throughput 175082770 # Throughput (bytes/s)
480 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198557696 # Cumulative packet size per connected master and slave (bytes)
481 system.membus.tot_pkt_size::total 198557696 # Cumulative packet size per connected master and slave (bytes)
482 system.membus.trans_dist::ReadReq 1255956 # Transaction distribution
483 system.membus.trans_dist::ReadResp 1255956 # Transaction distribution
484 system.membus.trans_dist::Writeback 1046478 # Transaction distribution
485 system.membus.trans_dist::ReadExReq 800030 # Transaction distribution
486 system.membus.trans_dist::ReadExResp 800030 # Transaction distribution
487 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
488 system.physmem.avgGap 365541.37 # Average gap between requests
489 system.physmem.avgMemAccLat 37274.24 # Average memory access latency per DRAM burst
490 system.physmem.avgQLat 18524.24 # Average queueing delay per DRAM burst
491 system.physmem.avgRdBW 115.95 # Average DRAM read bandwidth in MiByte/s
492 system.physmem.avgRdBWSys 116.03 # Average system read bandwidth in MiByte/s
493 system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
494 system.physmem.avgWrBW 59.05 # Average achieved write bandwidth in MiByte/s
495 system.physmem.avgWrBWSys 59.06 # Average system write bandwidth in MiByte/s
496 system.physmem.avgWrQLen 24.80 # Average write queue length when enqueuing
497 system.physmem.busUtil 1.37 # Data bus utilization in percentage
498 system.physmem.busUtilRead 0.91 # Data bus utilization in percentage for reads
499 system.physmem.busUtilWrite 0.46 # Data bus utilization in percentage for writes
500 system.physmem.bw_inst_read::cpu.inst 44808 # Instruction read bandwidth from this memory (bytes/s)
501 system.physmem.bw_inst_read::total 44808 # Instruction read bandwidth from this memory (bytes/s)
502 system.physmem.bw_read::cpu.inst 116026399 # Total read bandwidth from this memory (bytes/s)
503 system.physmem.bw_read::total 116026399 # Total read bandwidth from this memory (bytes/s)
504 system.physmem.bw_total::writebacks 59056372 # Total bandwidth to/from this memory (bytes/s)
505 system.physmem.bw_total::cpu.inst 116026399 # Total bandwidth to/from this memory (bytes/s)
506 system.physmem.bw_total::total 175082770 # Total bandwidth to/from this memory (bytes/s)
507 system.physmem.bw_write::writebacks 59056372 # Write bandwidth from this memory (bytes/s)
508 system.physmem.bw_write::total 59056372 # Write bandwidth from this memory (bytes/s)
509 system.physmem.bytesPerActivate::samples 1917061 # Bytes accessed per row activation
510 system.physmem.bytesPerActivate::mean 103.528140 # Bytes accessed per row activation
511 system.physmem.bytesPerActivate::gmean 81.739842 # Bytes accessed per row activation
512 system.physmem.bytesPerActivate::stdev 125.452866 # Bytes accessed per row activation
513 system.physmem.bytesPerActivate::0-127 1492586 77.86% 77.86% # Bytes accessed per row activation
514 system.physmem.bytesPerActivate::128-255 305285 15.92% 93.78% # Bytes accessed per row activation
515 system.physmem.bytesPerActivate::256-383 52052 2.72% 96.50% # Bytes accessed per row activation
516 system.physmem.bytesPerActivate::384-511 21496 1.12% 97.62% # Bytes accessed per row activation
517 system.physmem.bytesPerActivate::512-639 13307 0.69% 98.31% # Bytes accessed per row activation
518 system.physmem.bytesPerActivate::640-767 7031 0.37% 98.68% # Bytes accessed per row activation
519 system.physmem.bytesPerActivate::768-895 5522 0.29% 98.97% # Bytes accessed per row activation
520 system.physmem.bytesPerActivate::896-1023 4121 0.21% 99.18% # Bytes accessed per row activation
521 system.physmem.bytesPerActivate::1024-1151 15661 0.82% 100.00% # Bytes accessed per row activation
522 system.physmem.bytesPerActivate::total 1917061 # Bytes accessed per row activation
523 system.physmem.bytesReadDRAM 131498944 # Total number of bytes read from DRAM
524 system.physmem.bytesReadSys 131583104 # Total read bytes from the system interface side
525 system.physmem.bytesReadWrQ 84160 # Total number of bytes read from write queue
526 system.physmem.bytesWritten 66972672 # Total number of bytes written to DRAM
527 system.physmem.bytesWrittenSys 66974592 # Total written bytes from the system interface side
528 system.physmem.bytes_inst_read::cpu.inst 50816 # Number of instructions bytes read from this memory
529 system.physmem.bytes_inst_read::total 50816 # Number of instructions bytes read from this memory
530 system.physmem.bytes_read::cpu.inst 131583104 # Number of bytes read from this memory
531 system.physmem.bytes_read::total 131583104 # Number of bytes read from this memory
532 system.physmem.bytes_written::writebacks 66974592 # Number of bytes written to this memory
533 system.physmem.bytes_written::total 66974592 # Number of bytes written to this memory
534 system.physmem.memoryStateTime::IDLE 321867794250 # Time in different power states
535 system.physmem.memoryStateTime::REF 37869260000 # Time in different power states
536 system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
537 system.physmem.memoryStateTime::ACT 774338779750 # Time in different power states
538 system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
539 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
540 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
541 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
542 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
543 system.physmem.num_reads::cpu.inst 2055986 # Number of read requests responded to by this memory
544 system.physmem.num_reads::total 2055986 # Number of read requests responded to by this memory
545 system.physmem.num_writes::writebacks 1046478 # Number of write requests responded to by this memory
546 system.physmem.num_writes::total 1046478 # Number of write requests responded to by this memory
547 system.physmem.pageHitRate 38.18 # Row buffer hit rate, read and write combined
548 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
549 system.physmem.perBankRdBursts::0 127958 # Per bank write bursts
550 system.physmem.perBankRdBursts::1 125105 # Per bank write bursts
551 system.physmem.perBankRdBursts::2 122165 # Per bank write bursts
552 system.physmem.perBankRdBursts::3 124186 # Per bank write bursts
553 system.physmem.perBankRdBursts::4 123280 # Per bank write bursts
554 system.physmem.perBankRdBursts::5 123449 # Per bank write bursts
555 system.physmem.perBankRdBursts::6 123880 # Per bank write bursts
556 system.physmem.perBankRdBursts::7 124388 # Per bank write bursts
557 system.physmem.perBankRdBursts::8 131994 # Per bank write bursts
558 system.physmem.perBankRdBursts::9 133987 # Per bank write bursts
559 system.physmem.perBankRdBursts::10 132463 # Per bank write bursts
560 system.physmem.perBankRdBursts::11 133769 # Per bank write bursts
561 system.physmem.perBankRdBursts::12 133910 # Per bank write bursts
562 system.physmem.perBankRdBursts::13 133839 # Per bank write bursts
563 system.physmem.perBankRdBursts::14 129945 # Per bank write bursts
564 system.physmem.perBankRdBursts::15 130353 # Per bank write bursts
565 system.physmem.perBankWrBursts::0 65810 # Per bank write bursts
566 system.physmem.perBankWrBursts::1 64091 # Per bank write bursts
567 system.physmem.perBankWrBursts::2 62337 # Per bank write bursts
568 system.physmem.perBankWrBursts::3 62824 # Per bank write bursts
569 system.physmem.perBankWrBursts::4 62831 # Per bank write bursts
570 system.physmem.perBankWrBursts::5 62991 # Per bank write bursts
571 system.physmem.perBankWrBursts::6 64303 # Per bank write bursts
572 system.physmem.perBankWrBursts::7 65302 # Per bank write bursts
573 system.physmem.perBankWrBursts::8 67082 # Per bank write bursts
574 system.physmem.perBankWrBursts::9 67591 # Per bank write bursts
575 system.physmem.perBankWrBursts::10 67285 # Per bank write bursts
576 system.physmem.perBankWrBursts::11 67661 # Per bank write bursts
577 system.physmem.perBankWrBursts::12 67090 # Per bank write bursts
578 system.physmem.perBankWrBursts::13 67416 # Per bank write bursts
579 system.physmem.perBankWrBursts::14 66182 # Per bank write bursts
580 system.physmem.perBankWrBursts::15 65652 # Per bank write bursts
581 system.physmem.rdPerTurnAround::samples 60782 # Reads before turning the bus around for writes
582 system.physmem.rdPerTurnAround::mean 33.755668 # Reads before turning the bus around for writes
583 system.physmem.rdPerTurnAround::stdev 161.633297 # Reads before turning the bus around for writes
584 system.physmem.rdPerTurnAround::0-1023 60741 99.93% 99.93% # Reads before turning the bus around for writes
585 system.physmem.rdPerTurnAround::1024-2047 17 0.03% 99.96% # Reads before turning the bus around for writes
586 system.physmem.rdPerTurnAround::2048-3071 11 0.02% 99.98% # Reads before turning the bus around for writes
587 system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.99% # Reads before turning the bus around for writes
588 system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes
589 system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes
590 system.physmem.rdPerTurnAround::12288-13311 1 0.00% 100.00% # Reads before turning the bus around for writes
591 system.physmem.rdPerTurnAround::13312-14335 2 0.00% 100.00% # Reads before turning the bus around for writes
592 system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes
593 system.physmem.rdPerTurnAround::total 60782 # Reads before turning the bus around for writes
594 system.physmem.rdQLenPdf::0 1924013 # What read queue length does an incoming req see
595 system.physmem.rdQLenPdf::1 130641 # What read queue length does an incoming req see
596 system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see
597 system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
598 system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
599 system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
600 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
601 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
602 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
603 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
604 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
605 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
606 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
607 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
608 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
609 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
610 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
611 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
612 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
613 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
614 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
615 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
616 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
617 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
618 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
619 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
620 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
621 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
622 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
623 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
624 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
625 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
626 system.physmem.readBursts 2055986 # Number of DRAM read bursts, including those serviced by the write queue
627 system.physmem.readPktSize::0 0 # Read request sizes (log2)
628 system.physmem.readPktSize::1 0 # Read request sizes (log2)
629 system.physmem.readPktSize::2 0 # Read request sizes (log2)
630 system.physmem.readPktSize::3 0 # Read request sizes (log2)
631 system.physmem.readPktSize::4 0 # Read request sizes (log2)
632 system.physmem.readPktSize::5 0 # Read request sizes (log2)
633 system.physmem.readPktSize::6 2055986 # Read request sizes (log2)
634 system.physmem.readReqs 2055986 # Number of read requests accepted
635 system.physmem.readRowHitRate 37.77 # Row buffer hit rate for reads
636 system.physmem.readRowHits 776076 # Number of row buffer hits during reads
637 system.physmem.servicedByWrQ 1315 # Number of DRAM read bursts serviced by the write queue
638 system.physmem.totBusLat 10273355000 # Total ticks spent in databus transfers
639 system.physmem.totGap 1134078928500 # Total gap between requests
640 system.physmem.totMemAccLat 76586290250 # Total ticks spent from burst creation until serviced by the DRAM
641 system.physmem.totQLat 38061209000 # Total ticks spent queuing
642 system.physmem.wrPerTurnAround::samples 60782 # Writes before turning the bus around for reads
643 system.physmem.wrPerTurnAround::mean 17.216413 # Writes before turning the bus around for reads
644 system.physmem.wrPerTurnAround::gmean 17.182090 # Writes before turning the bus around for reads
645 system.physmem.wrPerTurnAround::stdev 1.086488 # Writes before turning the bus around for reads
646 system.physmem.wrPerTurnAround::16 25426 41.83% 41.83% # Writes before turning the bus around for reads
647 system.physmem.wrPerTurnAround::17 1488 2.45% 44.28% # Writes before turning the bus around for reads
648 system.physmem.wrPerTurnAround::18 29643 48.77% 93.05% # Writes before turning the bus around for reads
649 system.physmem.wrPerTurnAround::19 3806 6.26% 99.31% # Writes before turning the bus around for reads
650 system.physmem.wrPerTurnAround::20 363 0.60% 99.91% # Writes before turning the bus around for reads
651 system.physmem.wrPerTurnAround::21 50 0.08% 99.99% # Writes before turning the bus around for reads
652 system.physmem.wrPerTurnAround::22 4 0.01% 100.00% # Writes before turning the bus around for reads
653 system.physmem.wrPerTurnAround::23 1 0.00% 100.00% # Writes before turning the bus around for reads
654 system.physmem.wrPerTurnAround::27 1 0.00% 100.00% # Writes before turning the bus around for reads
655 system.physmem.wrPerTurnAround::total 60782 # Writes before turning the bus around for reads
656 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
657 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
658 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
659 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
660 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
661 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
662 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
663 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
664 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
665 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
666 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
667 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
668 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
669 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
670 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
671 system.physmem.wrQLenPdf::15 33627 # What write queue length does an incoming req see
672 system.physmem.wrQLenPdf::16 35200 # What write queue length does an incoming req see
673 system.physmem.wrQLenPdf::17 57222 # What write queue length does an incoming req see
674 system.physmem.wrQLenPdf::18 60715 # What write queue length does an incoming req see
675 system.physmem.wrQLenPdf::19 61437 # What write queue length does an incoming req see
676 system.physmem.wrQLenPdf::20 61279 # What write queue length does an incoming req see
677 system.physmem.wrQLenPdf::21 61254 # What write queue length does an incoming req see
678 system.physmem.wrQLenPdf::22 61244 # What write queue length does an incoming req see
679 system.physmem.wrQLenPdf::23 61236 # What write queue length does an incoming req see
680 system.physmem.wrQLenPdf::24 61317 # What write queue length does an incoming req see
681 system.physmem.wrQLenPdf::25 61255 # What write queue length does an incoming req see
682 system.physmem.wrQLenPdf::26 61292 # What write queue length does an incoming req see
683 system.physmem.wrQLenPdf::27 62303 # What write queue length does an incoming req see
684 system.physmem.wrQLenPdf::28 61692 # What write queue length does an incoming req see
685 system.physmem.wrQLenPdf::29 61407 # What write queue length does an incoming req see
686 system.physmem.wrQLenPdf::30 62182 # What write queue length does an incoming req see
687 system.physmem.wrQLenPdf::31 60930 # What write queue length does an incoming req see
688 system.physmem.wrQLenPdf::32 60785 # What write queue length does an incoming req see
689 system.physmem.wrQLenPdf::33 71 # What write queue length does an incoming req see
690 system.physmem.wrQLenPdf::34 8 # What write queue length does an incoming req see
691 system.physmem.wrQLenPdf::35 4 # What write queue length does an incoming req see
692 system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see
693 system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see
694 system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see
695 system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
696 system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
697 system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
698 system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
699 system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
700 system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
701 system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
702 system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
703 system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
704 system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
705 system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
706 system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
707 system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
708 system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
709 system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
710 system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
711 system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
712 system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
713 system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
714 system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
715 system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
716 system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
717 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
718 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
719 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
720 system.physmem.writeBursts 1046478 # Number of DRAM write bursts, including those merged in the write queue
721 system.physmem.writePktSize::0 0 # Write request sizes (log2)
722 system.physmem.writePktSize::1 0 # Write request sizes (log2)
723 system.physmem.writePktSize::2 0 # Write request sizes (log2)
724 system.physmem.writePktSize::3 0 # Write request sizes (log2)
725 system.physmem.writePktSize::4 0 # Write request sizes (log2)
726 system.physmem.writePktSize::5 0 # Write request sizes (log2)
727 system.physmem.writePktSize::6 1046478 # Write request sizes (log2)
728 system.physmem.writeReqs 1046478 # Number of write requests accepted
729 system.physmem.writeRowHitRate 38.99 # Row buffer hit rate for writes
730 system.physmem.writeRowHits 407972 # Number of row buffer hits during writes
731 system.voltage_domain.voltage 1 # Voltage in Volts
733 ---------- End Simulation Statistics ----------
projects / gem5.git / blob