2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.517371 # Number of seconds simulated
4 sim_ticks 517371024000 # Number of ticks simulated
5 final_tick 517371024000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 170437 # Simulator instruction rate (inst/s)
8 host_op_rate 190135 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 57090080 # Simulator tick rate (ticks/s)
10 host_mem_usage 485276 # Number of bytes of host memory used
11 host_seconds 9062.36 # Real time elapsed on the host
12 sim_insts 1544563023 # Number of instructions simulated
13 sim_ops 1723073835 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 48064 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 143734144 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 143782208 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 48064 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 48064 # Number of instructions bytes read from this memory
19 system.physmem.bytes_written::writebacks 70446784 # Number of bytes written to this memory
20 system.physmem.bytes_written::total 70446784 # Number of bytes written to this memory
21 system.physmem.num_reads::cpu.inst 751 # Number of read requests responded to by this memory
22 system.physmem.num_reads::cpu.data 2245846 # Number of read requests responded to by this memory
23 system.physmem.num_reads::total 2246597 # Number of read requests responded to by this memory
24 system.physmem.num_writes::writebacks 1100731 # Number of write requests responded to by this memory
25 system.physmem.num_writes::total 1100731 # Number of write requests responded to by this memory
26 system.physmem.bw_read::cpu.inst 92900 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_read::cpu.data 277816378 # Total read bandwidth from this memory (bytes/s)
28 system.physmem.bw_read::total 277909279 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_inst_read::cpu.inst 92900 # Instruction read bandwidth from this memory (bytes/s)
30 system.physmem.bw_inst_read::total 92900 # Instruction read bandwidth from this memory (bytes/s)
31 system.physmem.bw_write::writebacks 136162987 # Write bandwidth from this memory (bytes/s)
32 system.physmem.bw_write::total 136162987 # Write bandwidth from this memory (bytes/s)
33 system.physmem.bw_total::writebacks 136162987 # Total bandwidth to/from this memory (bytes/s)
34 system.physmem.bw_total::cpu.inst 92900 # Total bandwidth to/from this memory (bytes/s)
35 system.physmem.bw_total::cpu.data 277816378 # Total bandwidth to/from this memory (bytes/s)
36 system.physmem.bw_total::total 414072265 # Total bandwidth to/from this memory (bytes/s)
37 system.physmem.readReqs 2246597 # Total number of read requests seen
38 system.physmem.writeReqs 1100731 # Total number of write requests seen
39 system.physmem.cpureqs 3350452 # Reqs generatd by CPU via cache - shady
40 system.physmem.bytesRead 143782208 # Total number of bytes read from memory
41 system.physmem.bytesWritten 70446784 # Total number of bytes written to memory
42 system.physmem.bytesConsumedRd 143782208 # bytesRead derated as per pkt->getSize()
43 system.physmem.bytesConsumedWr 70446784 # bytesWritten derated as per pkt->getSize()
44 system.physmem.servicedByWrQ 642 # Number of read reqs serviced by write Q
45 system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
46 system.physmem.perBankRdReqs::0 141495 # Track reads on a per bank basis
47 system.physmem.perBankRdReqs::1 139690 # Track reads on a per bank basis
48 system.physmem.perBankRdReqs::2 141603 # Track reads on a per bank basis
49 system.physmem.perBankRdReqs::3 141749 # Track reads on a per bank basis
50 system.physmem.perBankRdReqs::4 142295 # Track reads on a per bank basis
51 system.physmem.perBankRdReqs::5 140068 # Track reads on a per bank basis
52 system.physmem.perBankRdReqs::6 141091 # Track reads on a per bank basis
53 system.physmem.perBankRdReqs::7 140693 # Track reads on a per bank basis
54 system.physmem.perBankRdReqs::8 138519 # Track reads on a per bank basis
55 system.physmem.perBankRdReqs::9 136203 # Track reads on a per bank basis
56 system.physmem.perBankRdReqs::10 140642 # Track reads on a per bank basis
57 system.physmem.perBankRdReqs::11 140693 # Track reads on a per bank basis
58 system.physmem.perBankRdReqs::12 141066 # Track reads on a per bank basis
59 system.physmem.perBankRdReqs::13 139208 # Track reads on a per bank basis
60 system.physmem.perBankRdReqs::14 139271 # Track reads on a per bank basis
61 system.physmem.perBankRdReqs::15 141669 # Track reads on a per bank basis
62 system.physmem.perBankWrReqs::0 69094 # Track writes on a per bank basis
63 system.physmem.perBankWrReqs::1 68448 # Track writes on a per bank basis
64 system.physmem.perBankWrReqs::2 69171 # Track writes on a per bank basis
65 system.physmem.perBankWrReqs::3 69468 # Track writes on a per bank basis
66 system.physmem.perBankWrReqs::4 69338 # Track writes on a per bank basis
67 system.physmem.perBankWrReqs::5 68952 # Track writes on a per bank basis
68 system.physmem.perBankWrReqs::6 69046 # Track writes on a per bank basis
69 system.physmem.perBankWrReqs::7 68406 # Track writes on a per bank basis
70 system.physmem.perBankWrReqs::8 67828 # Track writes on a per bank basis
71 system.physmem.perBankWrReqs::9 66957 # Track writes on a per bank basis
72 system.physmem.perBankWrReqs::10 69534 # Track writes on a per bank basis
73 system.physmem.perBankWrReqs::11 69263 # Track writes on a per bank basis
74 system.physmem.perBankWrReqs::12 69109 # Track writes on a per bank basis
75 system.physmem.perBankWrReqs::13 68653 # Track writes on a per bank basis
76 system.physmem.perBankWrReqs::14 68505 # Track writes on a per bank basis
77 system.physmem.perBankWrReqs::15 68959 # Track writes on a per bank basis
78 system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
79 system.physmem.numWrRetry 3124 # Number of times wr buffer was full causing retry
80 system.physmem.totGap 517370944500 # Total gap between requests
81 system.physmem.readPktSize::0 0 # Categorize read packet sizes
82 system.physmem.readPktSize::1 0 # Categorize read packet sizes
83 system.physmem.readPktSize::2 0 # Categorize read packet sizes
84 system.physmem.readPktSize::3 0 # Categorize read packet sizes
85 system.physmem.readPktSize::4 0 # Categorize read packet sizes
86 system.physmem.readPktSize::5 0 # Categorize read packet sizes
87 system.physmem.readPktSize::6 2246597 # Categorize read packet sizes
88 system.physmem.writePktSize::0 0 # Categorize write packet sizes
89 system.physmem.writePktSize::1 0 # Categorize write packet sizes
90 system.physmem.writePktSize::2 0 # Categorize write packet sizes
91 system.physmem.writePktSize::3 0 # Categorize write packet sizes
92 system.physmem.writePktSize::4 0 # Categorize write packet sizes
93 system.physmem.writePktSize::5 0 # Categorize write packet sizes
94 system.physmem.writePktSize::6 1100731 # Categorize write packet sizes
95 system.physmem.rdQLenPdf::0 1563680 # What read queue length does an incoming req see
96 system.physmem.rdQLenPdf::1 451075 # What read queue length does an incoming req see
97 system.physmem.rdQLenPdf::2 162592 # What read queue length does an incoming req see
98 system.physmem.rdQLenPdf::3 68583 # What read queue length does an incoming req see
99 system.physmem.rdQLenPdf::4 22 # What read queue length does an incoming req see
100 system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
127 system.physmem.wrQLenPdf::0 44125 # What write queue length does an incoming req see
128 system.physmem.wrQLenPdf::1 47135 # What write queue length does an incoming req see
129 system.physmem.wrQLenPdf::2 47739 # What write queue length does an incoming req see
130 system.physmem.wrQLenPdf::3 47809 # What write queue length does an incoming req see
131 system.physmem.wrQLenPdf::4 47829 # What write queue length does an incoming req see
132 system.physmem.wrQLenPdf::5 47835 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::6 47837 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::7 47838 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::8 47840 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::9 47858 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::10 47858 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::11 47858 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::12 47858 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::13 47858 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::14 47858 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::15 47858 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::16 47858 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::17 47858 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::18 47858 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::19 47858 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::20 47857 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::21 47857 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::22 47857 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::23 3733 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::24 723 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::25 119 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::26 49 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::27 29 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::28 23 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::29 21 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::30 20 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::31 18 # What write queue length does an incoming req see
159 system.physmem.totQLat 51812524750 # Total cycles spent in queuing delays
160 system.physmem.totMemAccLat 131293078500 # Sum of mem lat for all requests
161 system.physmem.totBusLat 11229775000 # Total cycles spent in databus access
162 system.physmem.totBankLat 68250778750 # Total cycles spent in bank access
163 system.physmem.avgQLat 23069.26 # Average queueing delay per request
164 system.physmem.avgBankLat 30388.31 # Average bank access latency per request
165 system.physmem.avgBusLat 5000.00 # Average bus latency per request
166 system.physmem.avgMemAccLat 58457.57 # Average memory access latency
167 system.physmem.avgRdBW 277.91 # Average achieved read bandwidth in MB/s
168 system.physmem.avgWrBW 136.16 # Average achieved write bandwidth in MB/s
169 system.physmem.avgConsumedRdBW 277.91 # Average consumed read bandwidth in MB/s
170 system.physmem.avgConsumedWrBW 136.16 # Average consumed write bandwidth in MB/s
171 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
172 system.physmem.busUtil 3.23 # Data bus utilization in percentage
173 system.physmem.avgRdQLen 0.25 # Average read queue length over time
174 system.physmem.avgWrQLen 10.92 # Average write queue length over time
175 system.physmem.readRowHits 827855 # Number of row buffer hits during reads
176 system.physmem.writeRowHits 271156 # Number of row buffer hits during writes
177 system.physmem.readRowHitRate 36.86 # Row buffer hit rate for reads
178 system.physmem.writeRowHitRate 24.63 # Row buffer hit rate for writes
179 system.physmem.avgGap 154562.37 # Average gap between requests
180 system.cpu.branchPred.lookups 303290886 # Number of BP lookups
181 system.cpu.branchPred.condPredicted 249488582 # Number of conditional branches predicted
182 system.cpu.branchPred.condIncorrect 15222231 # Number of conditional branches incorrect
183 system.cpu.branchPred.BTBLookups 174596646 # Number of BTB lookups
184 system.cpu.branchPred.BTBHits 161469311 # Number of BTB hits
185 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
186 system.cpu.branchPred.BTBHitPct 92.481336 # BTB Hit Percentage
187 system.cpu.branchPred.usedRAS 17557313 # Number of times the RAS was used to get a target.
188 system.cpu.branchPred.RASInCorrect 202 # Number of incorrect RAS predictions.
189 system.cpu.dtb.inst_hits 0 # ITB inst hits
190 system.cpu.dtb.inst_misses 0 # ITB inst misses
191 system.cpu.dtb.read_hits 0 # DTB read hits
192 system.cpu.dtb.read_misses 0 # DTB read misses
193 system.cpu.dtb.write_hits 0 # DTB write hits
194 system.cpu.dtb.write_misses 0 # DTB write misses
195 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
196 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
197 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
198 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
199 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
200 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
201 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
202 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
203 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
204 system.cpu.dtb.read_accesses 0 # DTB read accesses
205 system.cpu.dtb.write_accesses 0 # DTB write accesses
206 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
207 system.cpu.dtb.hits 0 # DTB hits
208 system.cpu.dtb.misses 0 # DTB misses
209 system.cpu.dtb.accesses 0 # DTB accesses
210 system.cpu.itb.inst_hits 0 # ITB inst hits
211 system.cpu.itb.inst_misses 0 # ITB inst misses
212 system.cpu.itb.read_hits 0 # DTB read hits
213 system.cpu.itb.read_misses 0 # DTB read misses
214 system.cpu.itb.write_hits 0 # DTB write hits
215 system.cpu.itb.write_misses 0 # DTB write misses
216 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
217 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
218 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
219 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
220 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
221 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
222 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
223 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
224 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
225 system.cpu.itb.read_accesses 0 # DTB read accesses
226 system.cpu.itb.write_accesses 0 # DTB write accesses
227 system.cpu.itb.inst_accesses 0 # ITB inst accesses
228 system.cpu.itb.hits 0 # DTB hits
229 system.cpu.itb.misses 0 # DTB misses
230 system.cpu.itb.accesses 0 # DTB accesses
231 system.cpu.workload.num_syscalls 46 # Number of system calls
232 system.cpu.numCycles 1034742049 # number of cpu cycles simulated
233 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
234 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
235 system.cpu.fetch.icacheStallCycles 298209547 # Number of cycles fetch is stalled on an Icache miss
236 system.cpu.fetch.Insts 2186343540 # Number of instructions fetch has processed
237 system.cpu.fetch.Branches 303290886 # Number of branches that fetch encountered
238 system.cpu.fetch.predictedBranches 179026624 # Number of branches that fetch has predicted taken
239 system.cpu.fetch.Cycles 435120674 # Number of cycles fetch has run and was not squashing or blocked
240 system.cpu.fetch.SquashCycles 87852250 # Number of cycles fetch has spent squashing
241 system.cpu.fetch.BlockedCycles 155399906 # Number of cycles fetch has spent blocked
242 system.cpu.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
243 system.cpu.fetch.PendingTrapStallCycles 380 # Number of stall cycles due to pending traps
244 system.cpu.fetch.CacheLines 288562414 # Number of cache lines fetched
245 system.cpu.fetch.IcacheSquashes 5732154 # Number of outstanding Icache misses that were squashed
246 system.cpu.fetch.rateDist::samples 958634216 # Number of instructions fetched each cycle (Total)
247 system.cpu.fetch.rateDist::mean 2.523474 # Number of instructions fetched each cycle (Total)
248 system.cpu.fetch.rateDist::stdev 3.213325 # Number of instructions fetched each cycle (Total)
249 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
250 system.cpu.fetch.rateDist::0 523513675 54.61% 54.61% # Number of instructions fetched each cycle (Total)
251 system.cpu.fetch.rateDist::1 25518990 2.66% 57.27% # Number of instructions fetched each cycle (Total)
252 system.cpu.fetch.rateDist::2 39095186 4.08% 61.35% # Number of instructions fetched each cycle (Total)
253 system.cpu.fetch.rateDist::3 48349741 5.04% 66.39% # Number of instructions fetched each cycle (Total)
254 system.cpu.fetch.rateDist::4 43010158 4.49% 70.88% # Number of instructions fetched each cycle (Total)
255 system.cpu.fetch.rateDist::5 46440341 4.84% 75.73% # Number of instructions fetched each cycle (Total)
256 system.cpu.fetch.rateDist::6 38425121 4.01% 79.73% # Number of instructions fetched each cycle (Total)
257 system.cpu.fetch.rateDist::7 18710957 1.95% 81.69% # Number of instructions fetched each cycle (Total)
258 system.cpu.fetch.rateDist::8 175570047 18.31% 100.00% # Number of instructions fetched each cycle (Total)
259 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
260 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
261 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
262 system.cpu.fetch.rateDist::total 958634216 # Number of instructions fetched each cycle (Total)
263 system.cpu.fetch.branchRate 0.293108 # Number of branch fetches per cycle
264 system.cpu.fetch.rate 2.112936 # Number of inst fetches per cycle
265 system.cpu.decode.IdleCycles 329763250 # Number of cycles decode is idle
266 system.cpu.decode.BlockedCycles 133666994 # Number of cycles decode is blocked
267 system.cpu.decode.RunCycles 405221512 # Number of cycles decode is running
268 system.cpu.decode.UnblockCycles 20079412 # Number of cycles decode is unblocking
269 system.cpu.decode.SquashCycles 69903048 # Number of cycles decode is squashing
270 system.cpu.decode.BranchResolved 46058380 # Number of times decode resolved a branch
271 system.cpu.decode.BranchMispred 679 # Number of times decode detected a branch misprediction
272 system.cpu.decode.DecodedInsts 2367190993 # Number of instructions handled by decode
273 system.cpu.decode.SquashedInsts 2433 # Number of squashed instructions handled by decode
274 system.cpu.rename.SquashCycles 69903048 # Number of cycles rename is squashing
275 system.cpu.rename.IdleCycles 353304996 # Number of cycles rename is idle
276 system.cpu.rename.BlockCycles 63447183 # Number of cycles rename is blocking
277 system.cpu.rename.serializeStallCycles 15614 # count of cycles rename stalled for serializing inst
278 system.cpu.rename.RunCycles 400231748 # Number of cycles rename is running
279 system.cpu.rename.UnblockCycles 71731627 # Number of cycles rename is unblocking
280 system.cpu.rename.RenamedInsts 2304653779 # Number of instructions processed by rename
281 system.cpu.rename.ROBFullEvents 133097 # Number of times rename has blocked due to ROB full
282 system.cpu.rename.IQFullEvents 5040028 # Number of times rename has blocked due to IQ full
283 system.cpu.rename.LSQFullEvents 58589233 # Number of times rename has blocked due to LSQ full
284 system.cpu.rename.FullRegisterEvents 7 # Number of times there has been no free registers
285 system.cpu.rename.RenamedOperands 2280042978 # Number of destination operands rename has renamed
286 system.cpu.rename.RenameLookups 10643127773 # Number of register rename lookups that rename has made
287 system.cpu.rename.int_rename_lookups 10643124880 # Number of integer rename lookups
288 system.cpu.rename.fp_rename_lookups 2893 # Number of floating rename lookups
289 system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed
290 system.cpu.rename.UndoneMaps 573723048 # Number of HB maps that are undone due to squashing
291 system.cpu.rename.serializingInsts 497 # count of serializing insts renamed
292 system.cpu.rename.tempSerializingInsts 494 # count of temporary serializing insts renamed
293 system.cpu.rename.skidInsts 158827938 # count of insts added to the skid buffer
294 system.cpu.memDep0.insertedLoads 624515157 # Number of loads inserted to the mem dependence unit.
295 system.cpu.memDep0.insertedStores 220983969 # Number of stores inserted to the mem dependence unit.
296 system.cpu.memDep0.conflictingLoads 86332349 # Number of conflicting loads.
297 system.cpu.memDep0.conflictingStores 71315853 # Number of conflicting stores.
298 system.cpu.iq.iqInstsAdded 2201513470 # Number of instructions added to the IQ (excludes non-spec)
299 system.cpu.iq.iqNonSpecInstsAdded 522 # Number of non-speculative instructions added to the IQ
300 system.cpu.iq.iqInstsIssued 2018112827 # Number of instructions issued
301 system.cpu.iq.iqSquashedInstsIssued 4002858 # Number of squashed instructions issued
302 system.cpu.iq.iqSquashedInstsExamined 473886256 # Number of squashed instructions iterated over during squash; mainly for profiling
303 system.cpu.iq.iqSquashedOperandsExamined 1126241029 # Number of squashed operands that are examined and possibly removed from graph
304 system.cpu.iq.iqSquashedNonSpecRemoved 352 # Number of squashed non-spec instructions that were removed
305 system.cpu.iq.issued_per_cycle::samples 958634216 # Number of insts issued each cycle
306 system.cpu.iq.issued_per_cycle::mean 2.105196 # Number of insts issued each cycle
307 system.cpu.iq.issued_per_cycle::stdev 1.906381 # Number of insts issued each cycle
308 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
309 system.cpu.iq.issued_per_cycle::0 277594004 28.96% 28.96% # Number of insts issued each cycle
310 system.cpu.iq.issued_per_cycle::1 151404549 15.79% 44.75% # Number of insts issued each cycle
311 system.cpu.iq.issued_per_cycle::2 161201477 16.82% 61.57% # Number of insts issued each cycle
312 system.cpu.iq.issued_per_cycle::3 119812250 12.50% 74.06% # Number of insts issued each cycle
313 system.cpu.iq.issued_per_cycle::4 123999377 12.94% 87.00% # Number of insts issued each cycle
314 system.cpu.iq.issued_per_cycle::5 73820536 7.70% 94.70% # Number of insts issued each cycle
315 system.cpu.iq.issued_per_cycle::6 38419650 4.01% 98.71% # Number of insts issued each cycle
316 system.cpu.iq.issued_per_cycle::7 9808498 1.02% 99.73% # Number of insts issued each cycle
317 system.cpu.iq.issued_per_cycle::8 2573875 0.27% 100.00% # Number of insts issued each cycle
318 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
319 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
320 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
321 system.cpu.iq.issued_per_cycle::total 958634216 # Number of insts issued each cycle
322 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
323 system.cpu.iq.fu_full::IntAlu 872312 3.66% 3.66% # attempts to use FU when none available
324 system.cpu.iq.fu_full::IntMult 5645 0.02% 3.68% # attempts to use FU when none available
325 system.cpu.iq.fu_full::IntDiv 0 0.00% 3.68% # attempts to use FU when none available
326 system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.68% # attempts to use FU when none available
327 system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.68% # attempts to use FU when none available
328 system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.68% # attempts to use FU when none available
329 system.cpu.iq.fu_full::FloatMult 0 0.00% 3.68% # attempts to use FU when none available
330 system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.68% # attempts to use FU when none available
331 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.68% # attempts to use FU when none available
332 system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.68% # attempts to use FU when none available
333 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.68% # attempts to use FU when none available
334 system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.68% # attempts to use FU when none available
335 system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.68% # attempts to use FU when none available
336 system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.68% # attempts to use FU when none available
337 system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.68% # attempts to use FU when none available
338 system.cpu.iq.fu_full::SimdMult 0 0.00% 3.68% # attempts to use FU when none available
339 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.68% # attempts to use FU when none available
340 system.cpu.iq.fu_full::SimdShift 0 0.00% 3.68% # attempts to use FU when none available
341 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.68% # attempts to use FU when none available
342 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.68% # attempts to use FU when none available
343 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.68% # attempts to use FU when none available
344 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.68% # attempts to use FU when none available
345 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.68% # attempts to use FU when none available
346 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.68% # attempts to use FU when none available
347 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.68% # attempts to use FU when none available
348 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.68% # attempts to use FU when none available
349 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.68% # attempts to use FU when none available
350 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.68% # attempts to use FU when none available
351 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.68% # attempts to use FU when none available
352 system.cpu.iq.fu_full::MemRead 18268766 76.62% 80.30% # attempts to use FU when none available
353 system.cpu.iq.fu_full::MemWrite 4697940 19.70% 100.00% # attempts to use FU when none available
354 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
355 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
356 system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
357 system.cpu.iq.FU_type_0::IntAlu 1236677496 61.28% 61.28% # Type of FU issued
358 system.cpu.iq.FU_type_0::IntMult 926030 0.05% 61.32% # Type of FU issued
359 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued
360 system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.32% # Type of FU issued
361 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued
362 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued
363 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued
364 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued
365 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued
366 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued
367 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued
368 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.32% # Type of FU issued
369 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.32% # Type of FU issued
370 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.32% # Type of FU issued
371 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.32% # Type of FU issued
372 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued
373 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued
374 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued
375 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued
376 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued
377 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued
378 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued
379 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued
380 system.cpu.iq.FU_type_0::SimdFloatCvt 33 0.00% 61.32% # Type of FU issued
381 system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.32% # Type of FU issued
382 system.cpu.iq.FU_type_0::SimdFloatMisc 20 0.00% 61.32% # Type of FU issued
383 system.cpu.iq.FU_type_0::SimdFloatMult 5 0.00% 61.32% # Type of FU issued
384 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued
385 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued
386 system.cpu.iq.FU_type_0::MemRead 587482532 29.11% 90.44% # Type of FU issued
387 system.cpu.iq.FU_type_0::MemWrite 193026708 9.56% 100.00% # Type of FU issued
388 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
389 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
390 system.cpu.iq.FU_type_0::total 2018112827 # Type of FU issued
391 system.cpu.iq.rate 1.950354 # Inst issue rate
392 system.cpu.iq.fu_busy_cnt 23844663 # FU busy when requested
393 system.cpu.iq.fu_busy_rate 0.011815 # FU busy rate (busy events/executed inst)
394 system.cpu.iq.int_inst_queue_reads 5022707128 # Number of integer instruction queue reads
395 system.cpu.iq.int_inst_queue_writes 2675590256 # Number of integer instruction queue writes
396 system.cpu.iq.int_inst_queue_wakeup_accesses 1957438118 # Number of integer instruction queue wakeup accesses
397 system.cpu.iq.fp_inst_queue_reads 263 # Number of floating instruction queue reads
398 system.cpu.iq.fp_inst_queue_writes 556 # Number of floating instruction queue writes
399 system.cpu.iq.fp_inst_queue_wakeup_accesses 103 # Number of floating instruction queue wakeup accesses
400 system.cpu.iq.int_alu_accesses 2041957357 # Number of integer alu accesses
401 system.cpu.iq.fp_alu_accesses 133 # Number of floating point alu accesses
402 system.cpu.iew.lsq.thread0.forwLoads 64629974 # Number of loads that had data forwarded from stores
403 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
404 system.cpu.iew.lsq.thread0.squashedLoads 138588388 # Number of loads squashed
405 system.cpu.iew.lsq.thread0.ignoredResponses 271831 # Number of memory responses ignored because the instruction is squashed
406 system.cpu.iew.lsq.thread0.memOrderViolation 192988 # Number of memory ordering violations
407 system.cpu.iew.lsq.thread0.squashedStores 46136924 # Number of stores squashed
408 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
409 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
410 system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled
411 system.cpu.iew.lsq.thread0.cacheBlocked 4659196 # Number of times an access to memory failed due to the cache being blocked
412 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
413 system.cpu.iew.iewSquashCycles 69903048 # Number of cycles IEW is squashing
414 system.cpu.iew.iewBlockCycles 28888784 # Number of cycles IEW is blocking
415 system.cpu.iew.iewUnblockCycles 1501235 # Number of cycles IEW is unblocking
416 system.cpu.iew.iewDispatchedInsts 2201514122 # Number of instructions dispatched to IQ
417 system.cpu.iew.iewDispSquashedInsts 6139547 # Number of squashed instructions skipped by dispatch
418 system.cpu.iew.iewDispLoadInsts 624515157 # Number of dispatched load instructions
419 system.cpu.iew.iewDispStoreInsts 220983969 # Number of dispatched store instructions
420 system.cpu.iew.iewDispNonSpecInsts 460 # Number of dispatched non-speculative instructions
421 system.cpu.iew.iewIQFullEvents 475783 # Number of times the IQ has become full, causing a stall
422 system.cpu.iew.iewLSQFullEvents 89669 # Number of times the LSQ has become full, causing a stall
423 system.cpu.iew.memOrderViolationEvents 192988 # Number of memory order violations
424 system.cpu.iew.predictedTakenIncorrect 8156378 # Number of branches that were predicted taken incorrectly
425 system.cpu.iew.predictedNotTakenIncorrect 9617829 # Number of branches that were predicted not taken incorrectly
426 system.cpu.iew.branchMispredicts 17774207 # Number of branch mispredicts detected at execute
427 system.cpu.iew.iewExecutedInsts 1988116656 # Number of executed instructions
428 system.cpu.iew.iewExecLoadInsts 573901246 # Number of load instructions executed
429 system.cpu.iew.iewExecSquashedInsts 29996171 # Number of squashed instructions skipped in execute
430 system.cpu.iew.exec_swp 0 # number of swp insts executed
431 system.cpu.iew.exec_nop 130 # number of nop insts executed
432 system.cpu.iew.exec_refs 764045166 # number of memory reference insts executed
433 system.cpu.iew.exec_branches 238330381 # Number of branches executed
434 system.cpu.iew.exec_stores 190143920 # Number of stores executed
435 system.cpu.iew.exec_rate 1.921365 # Inst execution rate
436 system.cpu.iew.wb_sent 1965882705 # cumulative count of insts sent to commit
437 system.cpu.iew.wb_count 1957438221 # cumulative count of insts written-back
438 system.cpu.iew.wb_producers 1296419261 # num instructions producing a value
439 system.cpu.iew.wb_consumers 2061223018 # num instructions consuming a value
440 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
441 system.cpu.iew.wb_rate 1.891716 # insts written-back per cycle
442 system.cpu.iew.wb_fanout 0.628956 # average fanout of values written-back
443 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
444 system.cpu.commit.commitSquashedInsts 478537797 # The number of squashed insts skipped by commit
445 system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards
446 system.cpu.commit.branchMispredicts 15221576 # The number of times a branch was mispredicted
447 system.cpu.commit.committed_per_cycle::samples 888731168 # Number of insts commited each cycle
448 system.cpu.commit.committed_per_cycle::mean 1.938802 # Number of insts commited each cycle
449 system.cpu.commit.committed_per_cycle::stdev 2.727796 # Number of insts commited each cycle
450 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
451 system.cpu.commit.committed_per_cycle::0 401249220 45.15% 45.15% # Number of insts commited each cycle
452 system.cpu.commit.committed_per_cycle::1 192209497 21.63% 66.78% # Number of insts commited each cycle
453 system.cpu.commit.committed_per_cycle::2 72554391 8.16% 74.94% # Number of insts commited each cycle
454 system.cpu.commit.committed_per_cycle::3 35214687 3.96% 78.90% # Number of insts commited each cycle
455 system.cpu.commit.committed_per_cycle::4 19001350 2.14% 81.04% # Number of insts commited each cycle
456 system.cpu.commit.committed_per_cycle::5 30768614 3.46% 84.50% # Number of insts commited each cycle
457 system.cpu.commit.committed_per_cycle::6 20079948 2.26% 86.76% # Number of insts commited each cycle
458 system.cpu.commit.committed_per_cycle::7 11444333 1.29% 88.05% # Number of insts commited each cycle
459 system.cpu.commit.committed_per_cycle::8 106209128 11.95% 100.00% # Number of insts commited each cycle
460 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
461 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
462 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
463 system.cpu.commit.committed_per_cycle::total 888731168 # Number of insts commited each cycle
464 system.cpu.commit.committedInsts 1544563041 # Number of instructions committed
465 system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed
466 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
467 system.cpu.commit.refs 660773814 # Number of memory references committed
468 system.cpu.commit.loads 485926769 # Number of loads committed
469 system.cpu.commit.membars 62 # Number of memory barriers committed
470 system.cpu.commit.branches 213462426 # Number of branches committed
471 system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
472 system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions.
473 system.cpu.commit.function_calls 13665177 # Number of function calls committed.
474 system.cpu.commit.bw_lim_events 106209128 # number cycles where commit BW limit reached
475 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
476 system.cpu.rob.rob_reads 2984133091 # The number of ROB reads
477 system.cpu.rob.rob_writes 4473274350 # The number of ROB writes
478 system.cpu.timesIdled 1017651 # Number of times that the entire CPU went into an idle state and unscheduled itself
479 system.cpu.idleCycles 76107833 # Total number of cycles that the CPU has spent unscheduled due to idling
480 system.cpu.committedInsts 1544563023 # Number of Instructions Simulated
481 system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated
482 system.cpu.committedInsts_total 1544563023 # Number of Instructions Simulated
483 system.cpu.cpi 0.669925 # CPI: Cycles Per Instruction
484 system.cpu.cpi_total 0.669925 # CPI: Total CPI of All Threads
485 system.cpu.ipc 1.492703 # IPC: Instructions Per Cycle
486 system.cpu.ipc_total 1.492703 # IPC: Total IPC of All Threads
487 system.cpu.int_regfile_reads 9956233395 # number of integer regfile reads
488 system.cpu.int_regfile_writes 1937436072 # number of integer regfile writes
489 system.cpu.fp_regfile_reads 98 # number of floating regfile reads
490 system.cpu.fp_regfile_writes 104 # number of floating regfile writes
491 system.cpu.misc_regfile_reads 737527238 # number of misc regfile reads
492 system.cpu.misc_regfile_writes 124 # number of misc regfile writes
493 system.cpu.icache.replacements 22 # number of replacements
494 system.cpu.icache.tagsinuse 625.709575 # Cycle average of tags in use
495 system.cpu.icache.total_refs 288561231 # Total number of references to valid blocks.
496 system.cpu.icache.sampled_refs 779 # Sample count of references to valid blocks.
497 system.cpu.icache.avg_refs 370425.200257 # Average number of references to valid blocks.
498 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
499 system.cpu.icache.occ_blocks::cpu.inst 625.709575 # Average occupied blocks per requestor
500 system.cpu.icache.occ_percent::cpu.inst 0.305522 # Average percentage of cache occupancy
501 system.cpu.icache.occ_percent::total 0.305522 # Average percentage of cache occupancy
502 system.cpu.icache.ReadReq_hits::cpu.inst 288561231 # number of ReadReq hits
503 system.cpu.icache.ReadReq_hits::total 288561231 # number of ReadReq hits
504 system.cpu.icache.demand_hits::cpu.inst 288561231 # number of demand (read+write) hits
505 system.cpu.icache.demand_hits::total 288561231 # number of demand (read+write) hits
506 system.cpu.icache.overall_hits::cpu.inst 288561231 # number of overall hits
507 system.cpu.icache.overall_hits::total 288561231 # number of overall hits
508 system.cpu.icache.ReadReq_misses::cpu.inst 1183 # number of ReadReq misses
509 system.cpu.icache.ReadReq_misses::total 1183 # number of ReadReq misses
510 system.cpu.icache.demand_misses::cpu.inst 1183 # number of demand (read+write) misses
511 system.cpu.icache.demand_misses::total 1183 # number of demand (read+write) misses
512 system.cpu.icache.overall_misses::cpu.inst 1183 # number of overall misses
513 system.cpu.icache.overall_misses::total 1183 # number of overall misses
514 system.cpu.icache.ReadReq_miss_latency::cpu.inst 68862000 # number of ReadReq miss cycles
515 system.cpu.icache.ReadReq_miss_latency::total 68862000 # number of ReadReq miss cycles
516 system.cpu.icache.demand_miss_latency::cpu.inst 68862000 # number of demand (read+write) miss cycles
517 system.cpu.icache.demand_miss_latency::total 68862000 # number of demand (read+write) miss cycles
518 system.cpu.icache.overall_miss_latency::cpu.inst 68862000 # number of overall miss cycles
519 system.cpu.icache.overall_miss_latency::total 68862000 # number of overall miss cycles
520 system.cpu.icache.ReadReq_accesses::cpu.inst 288562414 # number of ReadReq accesses(hits+misses)
521 system.cpu.icache.ReadReq_accesses::total 288562414 # number of ReadReq accesses(hits+misses)
522 system.cpu.icache.demand_accesses::cpu.inst 288562414 # number of demand (read+write) accesses
523 system.cpu.icache.demand_accesses::total 288562414 # number of demand (read+write) accesses
524 system.cpu.icache.overall_accesses::cpu.inst 288562414 # number of overall (read+write) accesses
525 system.cpu.icache.overall_accesses::total 288562414 # number of overall (read+write) accesses
526 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
527 system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
528 system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
529 system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
530 system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
531 system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
532 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58209.636517 # average ReadReq miss latency
533 system.cpu.icache.ReadReq_avg_miss_latency::total 58209.636517 # average ReadReq miss latency
534 system.cpu.icache.demand_avg_miss_latency::cpu.inst 58209.636517 # average overall miss latency
535 system.cpu.icache.demand_avg_miss_latency::total 58209.636517 # average overall miss latency
536 system.cpu.icache.overall_avg_miss_latency::cpu.inst 58209.636517 # average overall miss latency
537 system.cpu.icache.overall_avg_miss_latency::total 58209.636517 # average overall miss latency
538 system.cpu.icache.blocked_cycles::no_mshrs 195 # number of cycles access was blocked
539 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
540 system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked
541 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
542 system.cpu.icache.avg_blocked_cycles::no_mshrs 65 # average number of cycles each access was blocked
543 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
544 system.cpu.icache.fast_writes 0 # number of fast writes performed
545 system.cpu.icache.cache_copies 0 # number of cache copies performed
546 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 404 # number of ReadReq MSHR hits
547 system.cpu.icache.ReadReq_mshr_hits::total 404 # number of ReadReq MSHR hits
548 system.cpu.icache.demand_mshr_hits::cpu.inst 404 # number of demand (read+write) MSHR hits
549 system.cpu.icache.demand_mshr_hits::total 404 # number of demand (read+write) MSHR hits
550 system.cpu.icache.overall_mshr_hits::cpu.inst 404 # number of overall MSHR hits
551 system.cpu.icache.overall_mshr_hits::total 404 # number of overall MSHR hits
552 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 779 # number of ReadReq MSHR misses
553 system.cpu.icache.ReadReq_mshr_misses::total 779 # number of ReadReq MSHR misses
554 system.cpu.icache.demand_mshr_misses::cpu.inst 779 # number of demand (read+write) MSHR misses
555 system.cpu.icache.demand_mshr_misses::total 779 # number of demand (read+write) MSHR misses
556 system.cpu.icache.overall_mshr_misses::cpu.inst 779 # number of overall MSHR misses
557 system.cpu.icache.overall_mshr_misses::total 779 # number of overall MSHR misses
558 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46813500 # number of ReadReq MSHR miss cycles
559 system.cpu.icache.ReadReq_mshr_miss_latency::total 46813500 # number of ReadReq MSHR miss cycles
560 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46813500 # number of demand (read+write) MSHR miss cycles
561 system.cpu.icache.demand_mshr_miss_latency::total 46813500 # number of demand (read+write) MSHR miss cycles
562 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46813500 # number of overall MSHR miss cycles
563 system.cpu.icache.overall_mshr_miss_latency::total 46813500 # number of overall MSHR miss cycles
564 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
565 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses
566 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
567 system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses
568 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
569 system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses
570 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60094.351733 # average ReadReq mshr miss latency
571 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60094.351733 # average ReadReq mshr miss latency
572 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60094.351733 # average overall mshr miss latency
573 system.cpu.icache.demand_avg_mshr_miss_latency::total 60094.351733 # average overall mshr miss latency
574 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60094.351733 # average overall mshr miss latency
575 system.cpu.icache.overall_avg_mshr_miss_latency::total 60094.351733 # average overall mshr miss latency
576 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
577 system.cpu.l2cache.replacements 2213910 # number of replacements
578 system.cpu.l2cache.tagsinuse 31531.957469 # Cycle average of tags in use
579 system.cpu.l2cache.total_refs 9247495 # Total number of references to valid blocks.
580 system.cpu.l2cache.sampled_refs 2243685 # Sample count of references to valid blocks.
581 system.cpu.l2cache.avg_refs 4.121566 # Average number of references to valid blocks.
582 system.cpu.l2cache.warmup_cycle 20448147251 # Cycle when the warmup percentage was hit.
583 system.cpu.l2cache.occ_blocks::writebacks 14435.927117 # Average occupied blocks per requestor
584 system.cpu.l2cache.occ_blocks::cpu.inst 20.343245 # Average occupied blocks per requestor
585 system.cpu.l2cache.occ_blocks::cpu.data 17075.687107 # Average occupied blocks per requestor
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592 system.cpu.l2cache.ReadReq_hits::total 6290268 # number of ReadReq hits
593 system.cpu.l2cache.Writeback_hits::writebacks 3781695 # number of Writeback hits
594 system.cpu.l2cache.Writeback_hits::total 3781695 # number of Writeback hits
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596 system.cpu.l2cache.ReadExReq_hits::total 1066899 # number of ReadExReq hits
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601 system.cpu.l2cache.overall_hits::cpu.data 7357140 # number of overall hits
602 system.cpu.l2cache.overall_hits::total 7357167 # number of overall hits
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607 system.cpu.l2cache.ReadExReq_misses::total 826653 # number of ReadExReq misses
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612 system.cpu.l2cache.overall_misses::cpu.data 2245854 # number of overall misses
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618 system.cpu.l2cache.ReadExReq_miss_latency::total 70488863500 # number of ReadExReq miss cycles
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623 system.cpu.l2cache.overall_miss_latency::cpu.data 184275172500 # number of overall miss cycles
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628 system.cpu.l2cache.Writeback_accesses::writebacks 3781695 # number of Writeback accesses(hits+misses)
629 system.cpu.l2cache.Writeback_accesses::total 3781695 # number of Writeback accesses(hits+misses)
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631 system.cpu.l2cache.ReadExReq_accesses::total 1893552 # number of ReadExReq accesses(hits+misses)
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637 system.cpu.l2cache.overall_accesses::total 9603773 # number of overall (read+write) accesses
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639 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184086 # miss rate for ReadReq accesses
640 system.cpu.l2cache.ReadReq_miss_rate::total 0.184165 # miss rate for ReadReq accesses
641 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436562 # miss rate for ReadExReq accesses
642 system.cpu.l2cache.ReadExReq_miss_rate::total 0.436562 # miss rate for ReadExReq accesses
643 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965340 # miss rate for demand accesses
644 system.cpu.l2cache.demand_miss_rate::cpu.data 0.233870 # miss rate for demand accesses
645 system.cpu.l2cache.demand_miss_rate::total 0.233930 # miss rate for demand accesses
646 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965340 # miss rate for overall accesses
647 system.cpu.l2cache.overall_miss_rate::cpu.data 0.233870 # miss rate for overall accesses
648 system.cpu.l2cache.overall_miss_rate::total 0.233930 # miss rate for overall accesses
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650 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80176.316815 # average ReadReq miss latency
651 system.cpu.l2cache.ReadReq_avg_miss_latency::total 80166.081201 # average ReadReq miss latency
652 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85270.196201 # average ReadExReq miss latency
653 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85270.196201 # average ReadExReq miss latency
654 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60849.069149 # average overall miss latency
655 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82051.269806 # average overall miss latency
656 system.cpu.l2cache.demand_avg_miss_latency::total 82044.172855 # average overall miss latency
657 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60849.069149 # average overall miss latency
658 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82051.269806 # average overall miss latency
659 system.cpu.l2cache.overall_avg_miss_latency::total 82044.172855 # average overall miss latency
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661 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
662 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
663 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
664 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
665 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
666 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
667 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
668 system.cpu.l2cache.writebacks::writebacks 1100731 # number of writebacks
669 system.cpu.l2cache.writebacks::total 1100731 # number of writebacks
670 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
671 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits
672 system.cpu.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits
673 system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
674 system.cpu.l2cache.demand_mshr_hits::cpu.data 8 # number of demand (read+write) MSHR hits
675 system.cpu.l2cache.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits
676 system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
677 system.cpu.l2cache.overall_mshr_hits::cpu.data 8 # number of overall MSHR hits
678 system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits
679 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 751 # number of ReadReq MSHR misses
680 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1419193 # number of ReadReq MSHR misses
681 system.cpu.l2cache.ReadReq_mshr_misses::total 1419944 # number of ReadReq MSHR misses
682 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 826653 # number of ReadExReq MSHR misses
683 system.cpu.l2cache.ReadExReq_mshr_misses::total 826653 # number of ReadExReq MSHR misses
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689 system.cpu.l2cache.overall_mshr_misses::total 2246597 # number of overall MSHR misses
690 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 36118599 # number of ReadReq MSHR miss cycles
691 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 96162576934 # number of ReadReq MSHR miss cycles
692 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 96198695533 # number of ReadReq MSHR miss cycles
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694 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60228963949 # number of ReadExReq MSHR miss cycles
695 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 36118599 # number of demand (read+write) MSHR miss cycles
696 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156391540883 # number of demand (read+write) MSHR miss cycles
697 system.cpu.l2cache.demand_mshr_miss_latency::total 156427659482 # number of demand (read+write) MSHR miss cycles
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699 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156391540883 # number of overall MSHR miss cycles
700 system.cpu.l2cache.overall_mshr_miss_latency::total 156427659482 # number of overall MSHR miss cycles
701 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964056 # mshr miss rate for ReadReq accesses
702 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184085 # mshr miss rate for ReadReq accesses
703 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184164 # mshr miss rate for ReadReq accesses
704 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436562 # mshr miss rate for ReadExReq accesses
705 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436562 # mshr miss rate for ReadExReq accesses
706 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964056 # mshr miss rate for demand accesses
707 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233869 # mshr miss rate for demand accesses
708 system.cpu.l2cache.demand_mshr_miss_rate::total 0.233929 # mshr miss rate for demand accesses
709 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964056 # mshr miss rate for overall accesses
710 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233869 # mshr miss rate for overall accesses
711 system.cpu.l2cache.overall_mshr_miss_rate::total 0.233929 # mshr miss rate for overall accesses
712 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 48094.006658 # average ReadReq mshr miss latency
713 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67758.632500 # average ReadReq mshr miss latency
714 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67748.231996 # average ReadReq mshr miss latency
715 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72858.822201 # average ReadExReq mshr miss latency
716 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72858.822201 # average ReadExReq mshr miss latency
717 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 48094.006658 # average overall mshr miss latency
718 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69635.914877 # average overall mshr miss latency
719 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69628.713776 # average overall mshr miss latency
720 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 48094.006658 # average overall mshr miss latency
721 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69635.914877 # average overall mshr miss latency
722 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69628.713776 # average overall mshr miss latency
723 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
724 system.cpu.dcache.replacements 9598898 # number of replacements
725 system.cpu.dcache.tagsinuse 4088.019682 # Cycle average of tags in use
726 system.cpu.dcache.total_refs 656099070 # Total number of references to valid blocks.
727 system.cpu.dcache.sampled_refs 9602994 # Sample count of references to valid blocks.
728 system.cpu.dcache.avg_refs 68.322345 # Average number of references to valid blocks.
729 system.cpu.dcache.warmup_cycle 3440663000 # Cycle when the warmup percentage was hit.
730 system.cpu.dcache.occ_blocks::cpu.data 4088.019682 # Average occupied blocks per requestor
731 system.cpu.dcache.occ_percent::cpu.data 0.998052 # Average percentage of cache occupancy
732 system.cpu.dcache.occ_percent::total 0.998052 # Average percentage of cache occupancy
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734 system.cpu.dcache.ReadReq_hits::total 489051603 # number of ReadReq hits
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736 system.cpu.dcache.WriteReq_hits::total 167047341 # number of WriteReq hits
737 system.cpu.dcache.LoadLockedReq_hits::cpu.data 65 # number of LoadLockedReq hits
738 system.cpu.dcache.LoadLockedReq_hits::total 65 # number of LoadLockedReq hits
739 system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
740 system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
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742 system.cpu.dcache.demand_hits::total 656098944 # number of demand (read+write) hits
743 system.cpu.dcache.overall_hits::cpu.data 656098944 # number of overall hits
744 system.cpu.dcache.overall_hits::total 656098944 # number of overall hits
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746 system.cpu.dcache.ReadReq_misses::total 11478513 # number of ReadReq misses
747 system.cpu.dcache.WriteReq_misses::cpu.data 5538706 # number of WriteReq misses
748 system.cpu.dcache.WriteReq_misses::total 5538706 # number of WriteReq misses
749 system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
750 system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
751 system.cpu.dcache.demand_misses::cpu.data 17017219 # number of demand (read+write) misses
752 system.cpu.dcache.demand_misses::total 17017219 # number of demand (read+write) misses
753 system.cpu.dcache.overall_misses::cpu.data 17017219 # number of overall misses
754 system.cpu.dcache.overall_misses::total 17017219 # number of overall misses
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756 system.cpu.dcache.ReadReq_miss_latency::total 323000428500 # number of ReadReq miss cycles
757 system.cpu.dcache.WriteReq_miss_latency::cpu.data 229631369718 # number of WriteReq miss cycles
758 system.cpu.dcache.WriteReq_miss_latency::total 229631369718 # number of WriteReq miss cycles
759 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 423500 # number of LoadLockedReq miss cycles
760 system.cpu.dcache.LoadLockedReq_miss_latency::total 423500 # number of LoadLockedReq miss cycles
761 system.cpu.dcache.demand_miss_latency::cpu.data 552631798218 # number of demand (read+write) miss cycles
762 system.cpu.dcache.demand_miss_latency::total 552631798218 # number of demand (read+write) miss cycles
763 system.cpu.dcache.overall_miss_latency::cpu.data 552631798218 # number of overall miss cycles
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766 system.cpu.dcache.ReadReq_accesses::total 500530116 # number of ReadReq accesses(hits+misses)
767 system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
768 system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
769 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 68 # number of LoadLockedReq accesses(hits+misses)
770 system.cpu.dcache.LoadLockedReq_accesses::total 68 # number of LoadLockedReq accesses(hits+misses)
771 system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
772 system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
773 system.cpu.dcache.demand_accesses::cpu.data 673116163 # number of demand (read+write) accesses
774 system.cpu.dcache.demand_accesses::total 673116163 # number of demand (read+write) accesses
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776 system.cpu.dcache.overall_accesses::total 673116163 # number of overall (read+write) accesses
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778 system.cpu.dcache.ReadReq_miss_rate::total 0.022933 # miss rate for ReadReq accesses
779 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032092 # miss rate for WriteReq accesses
780 system.cpu.dcache.WriteReq_miss_rate::total 0.032092 # miss rate for WriteReq accesses
781 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044118 # miss rate for LoadLockedReq accesses
782 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044118 # miss rate for LoadLockedReq accesses
783 system.cpu.dcache.demand_miss_rate::cpu.data 0.025281 # miss rate for demand accesses
784 system.cpu.dcache.demand_miss_rate::total 0.025281 # miss rate for demand accesses
785 system.cpu.dcache.overall_miss_rate::cpu.data 0.025281 # miss rate for overall accesses
786 system.cpu.dcache.overall_miss_rate::total 0.025281 # miss rate for overall accesses
787 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28139.570735 # average ReadReq miss latency
788 system.cpu.dcache.ReadReq_avg_miss_latency::total 28139.570735 # average ReadReq miss latency
789 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41459.389561 # average WriteReq miss latency
790 system.cpu.dcache.WriteReq_avg_miss_latency::total 41459.389561 # average WriteReq miss latency
791 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 141166.666667 # average LoadLockedReq miss latency
792 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 141166.666667 # average LoadLockedReq miss latency
793 system.cpu.dcache.demand_avg_miss_latency::cpu.data 32474.859624 # average overall miss latency
794 system.cpu.dcache.demand_avg_miss_latency::total 32474.859624 # average overall miss latency
795 system.cpu.dcache.overall_avg_miss_latency::cpu.data 32474.859624 # average overall miss latency
796 system.cpu.dcache.overall_avg_miss_latency::total 32474.859624 # average overall miss latency
797 system.cpu.dcache.blocked_cycles::no_mshrs 26343962 # number of cycles access was blocked
798 system.cpu.dcache.blocked_cycles::no_targets 1054966 # number of cycles access was blocked
799 system.cpu.dcache.blocked::no_mshrs 1182360 # number of cycles access was blocked
800 system.cpu.dcache.blocked::no_targets 64552 # number of cycles access was blocked
801 system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.280830 # average number of cycles each access was blocked
802 system.cpu.dcache.avg_blocked_cycles::no_targets 16.342886 # average number of cycles each access was blocked
803 system.cpu.dcache.fast_writes 0 # number of fast writes performed
804 system.cpu.dcache.cache_copies 0 # number of cache copies performed
805 system.cpu.dcache.writebacks::writebacks 3781695 # number of writebacks
806 system.cpu.dcache.writebacks::total 3781695 # number of writebacks
807 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3769070 # number of ReadReq MSHR hits
808 system.cpu.dcache.ReadReq_mshr_hits::total 3769070 # number of ReadReq MSHR hits
809 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3645155 # number of WriteReq MSHR hits
810 system.cpu.dcache.WriteReq_mshr_hits::total 3645155 # number of WriteReq MSHR hits
811 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
812 system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
813 system.cpu.dcache.demand_mshr_hits::cpu.data 7414225 # number of demand (read+write) MSHR hits
814 system.cpu.dcache.demand_mshr_hits::total 7414225 # number of demand (read+write) MSHR hits
815 system.cpu.dcache.overall_mshr_hits::cpu.data 7414225 # number of overall MSHR hits
816 system.cpu.dcache.overall_mshr_hits::total 7414225 # number of overall MSHR hits
817 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7709443 # number of ReadReq MSHR misses
818 system.cpu.dcache.ReadReq_mshr_misses::total 7709443 # number of ReadReq MSHR misses
819 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893551 # number of WriteReq MSHR misses
820 system.cpu.dcache.WriteReq_mshr_misses::total 1893551 # number of WriteReq MSHR misses
821 system.cpu.dcache.demand_mshr_misses::cpu.data 9602994 # number of demand (read+write) MSHR misses
822 system.cpu.dcache.demand_mshr_misses::total 9602994 # number of demand (read+write) MSHR misses
823 system.cpu.dcache.overall_mshr_misses::cpu.data 9602994 # number of overall MSHR misses
824 system.cpu.dcache.overall_mshr_misses::total 9602994 # number of overall MSHR misses
825 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 186232562000 # number of ReadReq MSHR miss cycles
826 system.cpu.dcache.ReadReq_mshr_miss_latency::total 186232562000 # number of ReadReq MSHR miss cycles
827 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83589909224 # number of WriteReq MSHR miss cycles
828 system.cpu.dcache.WriteReq_mshr_miss_latency::total 83589909224 # number of WriteReq MSHR miss cycles
829 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 269822471224 # number of demand (read+write) MSHR miss cycles
830 system.cpu.dcache.demand_mshr_miss_latency::total 269822471224 # number of demand (read+write) MSHR miss cycles
831 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 269822471224 # number of overall MSHR miss cycles
832 system.cpu.dcache.overall_mshr_miss_latency::total 269822471224 # number of overall MSHR miss cycles
833 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015403 # mshr miss rate for ReadReq accesses
834 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015403 # mshr miss rate for ReadReq accesses
835 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010972 # mshr miss rate for WriteReq accesses
836 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010972 # mshr miss rate for WriteReq accesses
837 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014266 # mshr miss rate for demand accesses
838 system.cpu.dcache.demand_mshr_miss_rate::total 0.014266 # mshr miss rate for demand accesses
839 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014266 # mshr miss rate for overall accesses
840 system.cpu.dcache.overall_mshr_miss_rate::total 0.014266 # mshr miss rate for overall accesses
841 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24156.422455 # average ReadReq mshr miss latency
842 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24156.422455 # average ReadReq mshr miss latency
843 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44144.524876 # average WriteReq mshr miss latency
844 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44144.524876 # average WriteReq mshr miss latency
845 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28097.744435 # average overall mshr miss latency
846 system.cpu.dcache.demand_avg_mshr_miss_latency::total 28097.744435 # average overall mshr miss latency
847 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28097.744435 # average overall mshr miss latency
848 system.cpu.dcache.overall_avg_mshr_miss_latency::total 28097.744435 # average overall mshr miss latency
849 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
851 ---------- End Simulation Statistics ----------
projects / gem5.git / blob