2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.771783 # Number of seconds simulated
4 sim_ticks 771782683000 # Number of ticks simulated
5 final_tick 771782683000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 140791 # Simulator instruction rate (inst/s)
8 host_op_rate 151681 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 70349895 # Simulator tick rate (ticks/s)
10 host_mem_usage 240068 # Number of bytes of host memory used
11 host_seconds 10970.63 # Real time elapsed on the host
12 sim_insts 1544563023 # Number of instructions simulated
13 sim_ops 1664032415 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 66112 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 238756480 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.l2cache.prefetcher 63336128 # Number of bytes read from this memory
19 system.physmem.bytes_read::total 302158720 # Number of bytes read from this memory
20 system.physmem.bytes_inst_read::cpu.inst 66112 # Number of instructions bytes read from this memory
21 system.physmem.bytes_inst_read::total 66112 # Number of instructions bytes read from this memory
22 system.physmem.bytes_written::writebacks 104900608 # Number of bytes written to this memory
23 system.physmem.bytes_written::total 104900608 # Number of bytes written to this memory
24 system.physmem.num_reads::cpu.inst 1033 # Number of read requests responded to by this memory
25 system.physmem.num_reads::cpu.data 3730570 # Number of read requests responded to by this memory
26 system.physmem.num_reads::cpu.l2cache.prefetcher 989627 # Number of read requests responded to by this memory
27 system.physmem.num_reads::total 4721230 # Number of read requests responded to by this memory
28 system.physmem.num_writes::writebacks 1639072 # Number of write requests responded to by this memory
29 system.physmem.num_writes::total 1639072 # Number of write requests responded to by this memory
30 system.physmem.bw_read::cpu.inst 85661 # Total read bandwidth from this memory (bytes/s)
31 system.physmem.bw_read::cpu.data 309357135 # Total read bandwidth from this memory (bytes/s)
32 system.physmem.bw_read::cpu.l2cache.prefetcher 82064718 # Total read bandwidth from this memory (bytes/s)
33 system.physmem.bw_read::total 391507515 # Total read bandwidth from this memory (bytes/s)
34 system.physmem.bw_inst_read::cpu.inst 85661 # Instruction read bandwidth from this memory (bytes/s)
35 system.physmem.bw_inst_read::total 85661 # Instruction read bandwidth from this memory (bytes/s)
36 system.physmem.bw_write::writebacks 135919878 # Write bandwidth from this memory (bytes/s)
37 system.physmem.bw_write::total 135919878 # Write bandwidth from this memory (bytes/s)
38 system.physmem.bw_total::writebacks 135919878 # Total bandwidth to/from this memory (bytes/s)
39 system.physmem.bw_total::cpu.inst 85661 # Total bandwidth to/from this memory (bytes/s)
40 system.physmem.bw_total::cpu.data 309357135 # Total bandwidth to/from this memory (bytes/s)
41 system.physmem.bw_total::cpu.l2cache.prefetcher 82064718 # Total bandwidth to/from this memory (bytes/s)
42 system.physmem.bw_total::total 527427392 # Total bandwidth to/from this memory (bytes/s)
43 system.physmem.readReqs 4721230 # Number of read requests accepted
44 system.physmem.writeReqs 1639072 # Number of write requests accepted
45 system.physmem.readBursts 4721230 # Number of DRAM read bursts, including those serviced by the write queue
46 system.physmem.writeBursts 1639072 # Number of DRAM write bursts, including those merged in the write queue
47 system.physmem.bytesReadDRAM 301708544 # Total number of bytes read from DRAM
48 system.physmem.bytesReadWrQ 450176 # Total number of bytes read from write queue
49 system.physmem.bytesWritten 104898432 # Total number of bytes written to DRAM
50 system.physmem.bytesReadSys 302158720 # Total read bytes from the system interface side
51 system.physmem.bytesWrittenSys 104900608 # Total written bytes from the system interface side
52 system.physmem.servicedByWrQ 7034 # Number of DRAM read bursts serviced by the write queue
53 system.physmem.mergedWrBursts 11 # Number of DRAM write bursts merged with an existing one
54 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
55 system.physmem.perBankRdBursts::0 296496 # Per bank write bursts
56 system.physmem.perBankRdBursts::1 294922 # Per bank write bursts
57 system.physmem.perBankRdBursts::2 288553 # Per bank write bursts
58 system.physmem.perBankRdBursts::3 293200 # Per bank write bursts
59 system.physmem.perBankRdBursts::4 290519 # Per bank write bursts
60 system.physmem.perBankRdBursts::5 289057 # Per bank write bursts
61 system.physmem.perBankRdBursts::6 284695 # Per bank write bursts
62 system.physmem.perBankRdBursts::7 280747 # Per bank write bursts
63 system.physmem.perBankRdBursts::8 297891 # Per bank write bursts
64 system.physmem.perBankRdBursts::9 303659 # Per bank write bursts
65 system.physmem.perBankRdBursts::10 295750 # Per bank write bursts
66 system.physmem.perBankRdBursts::11 302488 # Per bank write bursts
67 system.physmem.perBankRdBursts::12 303486 # Per bank write bursts
68 system.physmem.perBankRdBursts::13 302338 # Per bank write bursts
69 system.physmem.perBankRdBursts::14 297681 # Per bank write bursts
70 system.physmem.perBankRdBursts::15 292714 # Per bank write bursts
71 system.physmem.perBankWrBursts::0 104090 # Per bank write bursts
72 system.physmem.perBankWrBursts::1 102136 # Per bank write bursts
73 system.physmem.perBankWrBursts::2 99204 # Per bank write bursts
74 system.physmem.perBankWrBursts::3 100079 # Per bank write bursts
75 system.physmem.perBankWrBursts::4 99319 # Per bank write bursts
76 system.physmem.perBankWrBursts::5 99058 # Per bank write bursts
77 system.physmem.perBankWrBursts::6 102867 # Per bank write bursts
78 system.physmem.perBankWrBursts::7 104266 # Per bank write bursts
79 system.physmem.perBankWrBursts::8 105488 # Per bank write bursts
80 system.physmem.perBankWrBursts::9 104503 # Per bank write bursts
81 system.physmem.perBankWrBursts::10 102301 # Per bank write bursts
82 system.physmem.perBankWrBursts::11 102956 # Per bank write bursts
83 system.physmem.perBankWrBursts::12 103260 # Per bank write bursts
84 system.physmem.perBankWrBursts::13 102520 # Per bank write bursts
85 system.physmem.perBankWrBursts::14 104484 # Per bank write bursts
86 system.physmem.perBankWrBursts::15 102507 # Per bank write bursts
87 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
88 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
89 system.physmem.totGap 771782536000 # Total gap between requests
90 system.physmem.readPktSize::0 0 # Read request sizes (log2)
91 system.physmem.readPktSize::1 0 # Read request sizes (log2)
92 system.physmem.readPktSize::2 0 # Read request sizes (log2)
93 system.physmem.readPktSize::3 0 # Read request sizes (log2)
94 system.physmem.readPktSize::4 0 # Read request sizes (log2)
95 system.physmem.readPktSize::5 0 # Read request sizes (log2)
96 system.physmem.readPktSize::6 4721230 # Read request sizes (log2)
97 system.physmem.writePktSize::0 0 # Write request sizes (log2)
98 system.physmem.writePktSize::1 0 # Write request sizes (log2)
99 system.physmem.writePktSize::2 0 # Write request sizes (log2)
100 system.physmem.writePktSize::3 0 # Write request sizes (log2)
101 system.physmem.writePktSize::4 0 # Write request sizes (log2)
102 system.physmem.writePktSize::5 0 # Write request sizes (log2)
103 system.physmem.writePktSize::6 1639072 # Write request sizes (log2)
104 system.physmem.rdQLenPdf::0 2775597 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::1 1044443 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::2 331745 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::3 234202 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::4 153941 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::5 85295 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::6 39428 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::7 23872 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::8 18360 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::9 4183 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::10 1645 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::11 788 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::12 434 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::13 248 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::14 11 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::15 4 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
136 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::15 22873 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::16 24573 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::17 60114 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::18 75847 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::19 85447 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::20 93235 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::21 99435 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::22 103341 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::23 105611 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::24 106420 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::25 106485 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::26 107133 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::27 108359 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::28 110847 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::29 113228 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::30 106323 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::31 103422 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::32 101669 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::33 2755 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::34 1061 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::35 485 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::36 198 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::37 99 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::38 50 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::39 22 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::40 10 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
200 system.physmem.bytesPerActivate::samples 4289012 # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::mean 94.801701 # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::gmean 78.923105 # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::stdev 101.558340 # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::0-127 3414847 79.62% 79.62% # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::128-255 675748 15.76% 95.37% # Bytes accessed per row activation
206 system.physmem.bytesPerActivate::256-383 96615 2.25% 97.63% # Bytes accessed per row activation
207 system.physmem.bytesPerActivate::384-511 35482 0.83% 98.45% # Bytes accessed per row activation
208 system.physmem.bytesPerActivate::512-639 22807 0.53% 98.99% # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::640-767 12154 0.28% 99.27% # Bytes accessed per row activation
210 system.physmem.bytesPerActivate::768-895 7173 0.17% 99.44% # Bytes accessed per row activation
211 system.physmem.bytesPerActivate::896-1023 5164 0.12% 99.56% # Bytes accessed per row activation
212 system.physmem.bytesPerActivate::1024-1151 19022 0.44% 100.00% # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::total 4289012 # Bytes accessed per row activation
214 system.physmem.rdPerTurnAround::samples 98837 # Reads before turning the bus around for writes
215 system.physmem.rdPerTurnAround::mean 47.696531 # Reads before turning the bus around for writes
216 system.physmem.rdPerTurnAround::gmean 32.309771 # Reads before turning the bus around for writes
217 system.physmem.rdPerTurnAround::stdev 98.301255 # Reads before turning the bus around for writes
218 system.physmem.rdPerTurnAround::0-127 95044 96.16% 96.16% # Reads before turning the bus around for writes
219 system.physmem.rdPerTurnAround::128-255 1344 1.36% 97.52% # Reads before turning the bus around for writes
220 system.physmem.rdPerTurnAround::256-383 770 0.78% 98.30% # Reads before turning the bus around for writes
221 system.physmem.rdPerTurnAround::384-511 419 0.42% 98.73% # Reads before turning the bus around for writes
222 system.physmem.rdPerTurnAround::512-639 374 0.38% 99.10% # Reads before turning the bus around for writes
223 system.physmem.rdPerTurnAround::640-767 356 0.36% 99.46% # Reads before turning the bus around for writes
224 system.physmem.rdPerTurnAround::768-895 254 0.26% 99.72% # Reads before turning the bus around for writes
225 system.physmem.rdPerTurnAround::896-1023 146 0.15% 99.87% # Reads before turning the bus around for writes
226 system.physmem.rdPerTurnAround::1024-1151 62 0.06% 99.93% # Reads before turning the bus around for writes
227 system.physmem.rdPerTurnAround::1152-1279 41 0.04% 99.97% # Reads before turning the bus around for writes
228 system.physmem.rdPerTurnAround::1280-1407 8 0.01% 99.98% # Reads before turning the bus around for writes
229 system.physmem.rdPerTurnAround::1408-1535 7 0.01% 99.99% # Reads before turning the bus around for writes
230 system.physmem.rdPerTurnAround::1536-1663 2 0.00% 99.99% # Reads before turning the bus around for writes
231 system.physmem.rdPerTurnAround::1792-1919 1 0.00% 99.99% # Reads before turning the bus around for writes
232 system.physmem.rdPerTurnAround::1920-2047 1 0.00% 99.99% # Reads before turning the bus around for writes
233 system.physmem.rdPerTurnAround::2304-2431 1 0.00% 99.99% # Reads before turning the bus around for writes
234 system.physmem.rdPerTurnAround::2560-2687 3 0.00% 100.00% # Reads before turning the bus around for writes
235 system.physmem.rdPerTurnAround::2944-3071 1 0.00% 100.00% # Reads before turning the bus around for writes
236 system.physmem.rdPerTurnAround::3200-3327 2 0.00% 100.00% # Reads before turning the bus around for writes
237 system.physmem.rdPerTurnAround::3584-3711 1 0.00% 100.00% # Reads before turning the bus around for writes
238 system.physmem.rdPerTurnAround::total 98837 # Reads before turning the bus around for writes
239 system.physmem.wrPerTurnAround::samples 98837 # Writes before turning the bus around for reads
240 system.physmem.wrPerTurnAround::mean 16.583243 # Writes before turning the bus around for reads
241 system.physmem.wrPerTurnAround::gmean 16.550199 # Writes before turning the bus around for reads
242 system.physmem.wrPerTurnAround::stdev 1.089458 # Writes before turning the bus around for reads
243 system.physmem.wrPerTurnAround::16 73410 74.27% 74.27% # Writes before turning the bus around for reads
244 system.physmem.wrPerTurnAround::17 1674 1.69% 75.97% # Writes before turning the bus around for reads
245 system.physmem.wrPerTurnAround::18 18461 18.68% 94.65% # Writes before turning the bus around for reads
246 system.physmem.wrPerTurnAround::19 3603 3.65% 98.29% # Writes before turning the bus around for reads
247 system.physmem.wrPerTurnAround::20 928 0.94% 99.23% # Writes before turning the bus around for reads
248 system.physmem.wrPerTurnAround::21 388 0.39% 99.62% # Writes before turning the bus around for reads
249 system.physmem.wrPerTurnAround::22 174 0.18% 99.80% # Writes before turning the bus around for reads
250 system.physmem.wrPerTurnAround::23 100 0.10% 99.90% # Writes before turning the bus around for reads
251 system.physmem.wrPerTurnAround::24 61 0.06% 99.96% # Writes before turning the bus around for reads
252 system.physmem.wrPerTurnAround::25 27 0.03% 99.99% # Writes before turning the bus around for reads
253 system.physmem.wrPerTurnAround::26 7 0.01% 100.00% # Writes before turning the bus around for reads
254 system.physmem.wrPerTurnAround::27 4 0.00% 100.00% # Writes before turning the bus around for reads
255 system.physmem.wrPerTurnAround::total 98837 # Writes before turning the bus around for reads
256 system.physmem.totQLat 132409571838 # Total ticks spent queuing
257 system.physmem.totMemAccLat 220800746838 # Total ticks spent from burst creation until serviced by the DRAM
258 system.physmem.totBusLat 23570980000 # Total ticks spent in databus transfers
259 system.physmem.avgQLat 28087.41 # Average queueing delay per DRAM burst
260 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
261 system.physmem.avgMemAccLat 46837.41 # Average memory access latency per DRAM burst
262 system.physmem.avgRdBW 390.92 # Average DRAM read bandwidth in MiByte/s
263 system.physmem.avgWrBW 135.92 # Average achieved write bandwidth in MiByte/s
264 system.physmem.avgRdBWSys 391.51 # Average system read bandwidth in MiByte/s
265 system.physmem.avgWrBWSys 135.92 # Average system write bandwidth in MiByte/s
266 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
267 system.physmem.busUtil 4.12 # Data bus utilization in percentage
268 system.physmem.busUtilRead 3.05 # Data bus utilization in percentage for reads
269 system.physmem.busUtilWrite 1.06 # Data bus utilization in percentage for writes
270 system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing
271 system.physmem.avgWrQLen 24.98 # Average write queue length when enqueuing
272 system.physmem.readRowHits 1710867 # Number of row buffer hits during reads
273 system.physmem.writeRowHits 353347 # Number of row buffer hits during writes
274 system.physmem.readRowHitRate 36.29 # Row buffer hit rate for reads
275 system.physmem.writeRowHitRate 21.56 # Row buffer hit rate for writes
276 system.physmem.avgGap 121343.69 # Average gap between requests
277 system.physmem.pageHitRate 32.49 # Row buffer hit rate, read and write combined
278 system.physmem_0.actEnergy 16078381200 # Energy for activate commands per rank (pJ)
279 system.physmem_0.preEnergy 8772926250 # Energy for precharge commands per rank (pJ)
280 system.physmem_0.readEnergy 18081671400 # Energy for read commands per rank (pJ)
281 system.physmem_0.writeEnergy 5255351280 # Energy for write commands per rank (pJ)
282 system.physmem_0.refreshEnergy 50408975760 # Energy for refresh commands per rank (pJ)
283 system.physmem_0.actBackEnergy 410988240855 # Energy for active background per rank (pJ)
284 system.physmem_0.preBackEnergy 102552687000 # Energy for precharge background per rank (pJ)
285 system.physmem_0.totalEnergy 612138233745 # Total energy per rank (pJ)
286 system.physmem_0.averagePower 793.150023 # Core power per rank (mW)
287 system.physmem_0.memoryStateTime::IDLE 168058001250 # Time in different power states
288 system.physmem_0.memoryStateTime::REF 25771460000 # Time in different power states
289 system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
290 system.physmem_0.memoryStateTime::ACT 577951698750 # Time in different power states
291 system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
292 system.physmem_1.actEnergy 16346489040 # Energy for activate commands per rank (pJ)
293 system.physmem_1.preEnergy 8919215250 # Energy for precharge commands per rank (pJ)
294 system.physmem_1.readEnergy 18688846800 # Energy for read commands per rank (pJ)
295 system.physmem_1.writeEnergy 5365504800 # Energy for write commands per rank (pJ)
296 system.physmem_1.refreshEnergy 50408975760 # Energy for refresh commands per rank (pJ)
297 system.physmem_1.actBackEnergy 412404849315 # Energy for active background per rank (pJ)
298 system.physmem_1.preBackEnergy 101310048000 # Energy for precharge background per rank (pJ)
299 system.physmem_1.totalEnergy 613443928965 # Total energy per rank (pJ)
300 system.physmem_1.averagePower 794.841817 # Core power per rank (mW)
301 system.physmem_1.memoryStateTime::IDLE 165993972457 # Time in different power states
302 system.physmem_1.memoryStateTime::REF 25771460000 # Time in different power states
303 system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
304 system.physmem_1.memoryStateTime::ACT 580015821043 # Time in different power states
305 system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
306 system.cpu.branchPred.lookups 286268512 # Number of BP lookups
307 system.cpu.branchPred.condPredicted 223399208 # Number of conditional branches predicted
308 system.cpu.branchPred.condIncorrect 14631885 # Number of conditional branches incorrect
309 system.cpu.branchPred.BTBLookups 157652290 # Number of BTB lookups
310 system.cpu.branchPred.BTBHits 150341382 # Number of BTB hits
311 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
312 system.cpu.branchPred.BTBHitPct 95.362638 # BTB Hit Percentage
313 system.cpu.branchPred.usedRAS 16641174 # Number of times the RAS was used to get a target.
314 system.cpu.branchPred.RASInCorrect 65 # Number of incorrect RAS predictions.
315 system.cpu_clk_domain.clock 500 # Clock period in ticks
316 system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
317 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
318 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
319 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
320 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
321 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
322 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
323 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
324 system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
325 system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
326 system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
327 system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
328 system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
329 system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
330 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
331 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
332 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
333 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
334 system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
335 system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
336 system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
337 system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
338 system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
339 system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
340 system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
341 system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
342 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
343 system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
344 system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
345 system.cpu.dtb.walker.walks 0 # Table walker walks requested
346 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
347 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
348 system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
349 system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
350 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
351 system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
352 system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
353 system.cpu.dtb.inst_hits 0 # ITB inst hits
354 system.cpu.dtb.inst_misses 0 # ITB inst misses
355 system.cpu.dtb.read_hits 0 # DTB read hits
356 system.cpu.dtb.read_misses 0 # DTB read misses
357 system.cpu.dtb.write_hits 0 # DTB write hits
358 system.cpu.dtb.write_misses 0 # DTB write misses
359 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
360 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
361 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
362 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
363 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
364 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
365 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
366 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
367 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
368 system.cpu.dtb.read_accesses 0 # DTB read accesses
369 system.cpu.dtb.write_accesses 0 # DTB write accesses
370 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
371 system.cpu.dtb.hits 0 # DTB hits
372 system.cpu.dtb.misses 0 # DTB misses
373 system.cpu.dtb.accesses 0 # DTB accesses
374 system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
375 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
376 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
377 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
378 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
379 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
380 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
381 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
382 system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
383 system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
384 system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
385 system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
386 system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
387 system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
388 system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
389 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
390 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
391 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
392 system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
393 system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
394 system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
395 system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
396 system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
397 system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
398 system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
399 system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
400 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
401 system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
402 system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
403 system.cpu.itb.walker.walks 0 # Table walker walks requested
404 system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
405 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
406 system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
407 system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
408 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
409 system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
410 system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
411 system.cpu.itb.inst_hits 0 # ITB inst hits
412 system.cpu.itb.inst_misses 0 # ITB inst misses
413 system.cpu.itb.read_hits 0 # DTB read hits
414 system.cpu.itb.read_misses 0 # DTB read misses
415 system.cpu.itb.write_hits 0 # DTB write hits
416 system.cpu.itb.write_misses 0 # DTB write misses
417 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
418 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
419 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
420 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
421 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
422 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
423 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
424 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
425 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
426 system.cpu.itb.read_accesses 0 # DTB read accesses
427 system.cpu.itb.write_accesses 0 # DTB write accesses
428 system.cpu.itb.inst_accesses 0 # ITB inst accesses
429 system.cpu.itb.hits 0 # DTB hits
430 system.cpu.itb.misses 0 # DTB misses
431 system.cpu.itb.accesses 0 # DTB accesses
432 system.cpu.workload.num_syscalls 46 # Number of system calls
433 system.cpu.numCycles 1543565367 # number of cpu cycles simulated
434 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
435 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
436 system.cpu.fetch.icacheStallCycles 13925779 # Number of cycles fetch is stalled on an Icache miss
437 system.cpu.fetch.Insts 2067423618 # Number of instructions fetch has processed
438 system.cpu.fetch.Branches 286268512 # Number of branches that fetch encountered
439 system.cpu.fetch.predictedBranches 166982556 # Number of branches that fetch has predicted taken
440 system.cpu.fetch.Cycles 1514915602 # Number of cycles fetch has run and was not squashing or blocked
441 system.cpu.fetch.SquashCycles 29288421 # Number of cycles fetch has spent squashing
442 system.cpu.fetch.MiscStallCycles 253 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
443 system.cpu.fetch.IcacheWaitRetryStallCycles 919 # Number of stall cycles due to full MSHR
444 system.cpu.fetch.CacheLines 656914213 # Number of cache lines fetched
445 system.cpu.fetch.IcacheSquashes 942 # Number of outstanding Icache misses that were squashed
446 system.cpu.fetch.rateDist::samples 1543486763 # Number of instructions fetched each cycle (Total)
447 system.cpu.fetch.rateDist::mean 1.434983 # Number of instructions fetched each cycle (Total)
448 system.cpu.fetch.rateDist::stdev 1.229356 # Number of instructions fetched each cycle (Total)
449 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
450 system.cpu.fetch.rateDist::0 461116597 29.87% 29.87% # Number of instructions fetched each cycle (Total)
451 system.cpu.fetch.rateDist::1 465422138 30.15% 60.03% # Number of instructions fetched each cycle (Total)
452 system.cpu.fetch.rateDist::2 101389056 6.57% 66.60% # Number of instructions fetched each cycle (Total)
453 system.cpu.fetch.rateDist::3 515558972 33.40% 100.00% # Number of instructions fetched each cycle (Total)
454 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
455 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
456 system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
457 system.cpu.fetch.rateDist::total 1543486763 # Number of instructions fetched each cycle (Total)
458 system.cpu.fetch.branchRate 0.185459 # Number of branch fetches per cycle
459 system.cpu.fetch.rate 1.339382 # Number of inst fetches per cycle
460 system.cpu.decode.IdleCycles 74615169 # Number of cycles decode is idle
461 system.cpu.decode.BlockedCycles 546131714 # Number of cycles decode is blocked
462 system.cpu.decode.RunCycles 850052649 # Number of cycles decode is running
463 system.cpu.decode.UnblockCycles 58043724 # Number of cycles decode is unblocking
464 system.cpu.decode.SquashCycles 14643507 # Number of cycles decode is squashing
465 system.cpu.decode.BranchResolved 42202613 # Number of times decode resolved a branch
466 system.cpu.decode.BranchMispred 760 # Number of times decode detected a branch misprediction
467 system.cpu.decode.DecodedInsts 2037139109 # Number of instructions handled by decode
468 system.cpu.decode.SquashedInsts 52472329 # Number of squashed instructions handled by decode
469 system.cpu.rename.SquashCycles 14643507 # Number of cycles rename is squashing
470 system.cpu.rename.IdleCycles 139680975 # Number of cycles rename is idle
471 system.cpu.rename.BlockCycles 464946049 # Number of cycles rename is blocking
472 system.cpu.rename.serializeStallCycles 14177 # count of cycles rename stalled for serializing inst
473 system.cpu.rename.RunCycles 837873228 # Number of cycles rename is running
474 system.cpu.rename.UnblockCycles 86328827 # Number of cycles rename is unblocking
475 system.cpu.rename.RenamedInsts 1976320354 # Number of instructions processed by rename
476 system.cpu.rename.SquashedInsts 26732336 # Number of squashed instructions processed by rename
477 system.cpu.rename.ROBFullEvents 45128593 # Number of times rename has blocked due to ROB full
478 system.cpu.rename.IQFullEvents 125639 # Number of times rename has blocked due to IQ full
479 system.cpu.rename.LQFullEvents 1500891 # Number of times rename has blocked due to LQ full
480 system.cpu.rename.SQFullEvents 25518898 # Number of times rename has blocked due to SQ full
481 system.cpu.rename.RenamedOperands 1985788047 # Number of destination operands rename has renamed
482 system.cpu.rename.RenameLookups 9127865226 # Number of register rename lookups that rename has made
483 system.cpu.rename.int_rename_lookups 2432787425 # Number of integer rename lookups
484 system.cpu.rename.fp_rename_lookups 124 # Number of floating rename lookups
485 system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed
486 system.cpu.rename.UndoneMaps 310889102 # Number of HB maps that are undone due to squashing
487 system.cpu.rename.serializingInsts 151 # count of serializing insts renamed
488 system.cpu.rename.tempSerializingInsts 141 # count of temporary serializing insts renamed
489 system.cpu.rename.skidInsts 111344488 # count of insts added to the skid buffer
490 system.cpu.memDep0.insertedLoads 542536301 # Number of loads inserted to the mem dependence unit.
491 system.cpu.memDep0.insertedStores 199301557 # Number of stores inserted to the mem dependence unit.
492 system.cpu.memDep0.conflictingLoads 26908887 # Number of conflicting loads.
493 system.cpu.memDep0.conflictingStores 29198248 # Number of conflicting stores.
494 system.cpu.iq.iqInstsAdded 1947883742 # Number of instructions added to the IQ (excludes non-spec)
495 system.cpu.iq.iqNonSpecInstsAdded 210 # Number of non-speculative instructions added to the IQ
496 system.cpu.iq.iqInstsIssued 1857409514 # Number of instructions issued
497 system.cpu.iq.iqSquashedInstsIssued 13500100 # Number of squashed instructions issued
498 system.cpu.iq.iqSquashedInstsExamined 283851537 # Number of squashed instructions iterated over during squash; mainly for profiling
499 system.cpu.iq.iqSquashedOperandsExamined 646881302 # Number of squashed operands that are examined and possibly removed from graph
500 system.cpu.iq.iqSquashedNonSpecRemoved 40 # Number of squashed non-spec instructions that were removed
501 system.cpu.iq.issued_per_cycle::samples 1543486763 # Number of insts issued each cycle
502 system.cpu.iq.issued_per_cycle::mean 1.203385 # Number of insts issued each cycle
503 system.cpu.iq.issued_per_cycle::stdev 1.151093 # Number of insts issued each cycle
504 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
505 system.cpu.iq.issued_per_cycle::0 590762659 38.27% 38.27% # Number of insts issued each cycle
506 system.cpu.iq.issued_per_cycle::1 325764931 21.11% 59.38% # Number of insts issued each cycle
507 system.cpu.iq.issued_per_cycle::2 378272466 24.51% 83.89% # Number of insts issued each cycle
508 system.cpu.iq.issued_per_cycle::3 219653351 14.23% 98.12% # Number of insts issued each cycle
509 system.cpu.iq.issued_per_cycle::4 29027182 1.88% 100.00% # Number of insts issued each cycle
510 system.cpu.iq.issued_per_cycle::5 6174 0.00% 100.00% # Number of insts issued each cycle
511 system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
512 system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
513 system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
514 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
515 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
516 system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
517 system.cpu.iq.issued_per_cycle::total 1543486763 # Number of insts issued each cycle
518 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
519 system.cpu.iq.fu_full::IntAlu 166053840 40.99% 40.99% # attempts to use FU when none available
520 system.cpu.iq.fu_full::IntMult 1992 0.00% 40.99% # attempts to use FU when none available
521 system.cpu.iq.fu_full::IntDiv 0 0.00% 40.99% # attempts to use FU when none available
522 system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.99% # attempts to use FU when none available
523 system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.99% # attempts to use FU when none available
524 system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.99% # attempts to use FU when none available
525 system.cpu.iq.fu_full::FloatMult 0 0.00% 40.99% # attempts to use FU when none available
526 system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.99% # attempts to use FU when none available
527 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.99% # attempts to use FU when none available
528 system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.99% # attempts to use FU when none available
529 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.99% # attempts to use FU when none available
530 system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.99% # attempts to use FU when none available
531 system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.99% # attempts to use FU when none available
532 system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.99% # attempts to use FU when none available
533 system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.99% # attempts to use FU when none available
534 system.cpu.iq.fu_full::SimdMult 0 0.00% 40.99% # attempts to use FU when none available
535 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.99% # attempts to use FU when none available
536 system.cpu.iq.fu_full::SimdShift 0 0.00% 40.99% # attempts to use FU when none available
537 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.99% # attempts to use FU when none available
538 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.99% # attempts to use FU when none available
539 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.99% # attempts to use FU when none available
540 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.99% # attempts to use FU when none available
541 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.99% # attempts to use FU when none available
542 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.99% # attempts to use FU when none available
543 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.99% # attempts to use FU when none available
544 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.99% # attempts to use FU when none available
545 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.99% # attempts to use FU when none available
546 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.99% # attempts to use FU when none available
547 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.99% # attempts to use FU when none available
548 system.cpu.iq.fu_full::MemRead 191416352 47.25% 88.24% # attempts to use FU when none available
549 system.cpu.iq.fu_full::MemWrite 47630536 11.76% 100.00% # attempts to use FU when none available
550 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
551 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
552 system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
553 system.cpu.iq.FU_type_0::IntAlu 1138248479 61.28% 61.28% # Type of FU issued
554 system.cpu.iq.FU_type_0::IntMult 801009 0.04% 61.32% # Type of FU issued
555 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued
556 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued
557 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued
558 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued
559 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued
560 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued
561 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued
562 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued
563 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued
564 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.32% # Type of FU issued
565 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.32% # Type of FU issued
566 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.32% # Type of FU issued
567 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.32% # Type of FU issued
568 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued
569 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued
570 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued
571 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued
572 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued
573 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued
574 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued
575 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued
576 system.cpu.iq.FU_type_0::SimdFloatCvt 26 0.00% 61.32% # Type of FU issued
577 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued
578 system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued
579 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued
580 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued
581 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued
582 system.cpu.iq.FU_type_0::MemRead 532044411 28.64% 89.97% # Type of FU issued
583 system.cpu.iq.FU_type_0::MemWrite 186315567 10.03% 100.00% # Type of FU issued
584 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
585 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
586 system.cpu.iq.FU_type_0::total 1857409514 # Type of FU issued
587 system.cpu.iq.rate 1.203324 # Inst issue rate
588 system.cpu.iq.fu_busy_cnt 405102720 # FU busy when requested
589 system.cpu.iq.fu_busy_rate 0.218101 # FU busy rate (busy events/executed inst)
590 system.cpu.iq.int_inst_queue_reads 5676908390 # Number of integer instruction queue reads
591 system.cpu.iq.int_inst_queue_writes 2231748222 # Number of integer instruction queue writes
592 system.cpu.iq.int_inst_queue_wakeup_accesses 1805707256 # Number of integer instruction queue wakeup accesses
593 system.cpu.iq.fp_inst_queue_reads 221 # Number of floating instruction queue reads
594 system.cpu.iq.fp_inst_queue_writes 208 # Number of floating instruction queue writes
595 system.cpu.iq.fp_inst_queue_wakeup_accesses 66 # Number of floating instruction queue wakeup accesses
596 system.cpu.iq.int_alu_accesses 2262512110 # Number of integer alu accesses
597 system.cpu.iq.fp_alu_accesses 124 # Number of floating point alu accesses
598 system.cpu.iew.lsq.thread0.forwLoads 17814082 # Number of loads that had data forwarded from stores
599 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
600 system.cpu.iew.lsq.thread0.squashedLoads 84229967 # Number of loads squashed
601 system.cpu.iew.lsq.thread0.ignoredResponses 66402 # Number of memory responses ignored because the instruction is squashed
602 system.cpu.iew.lsq.thread0.memOrderViolation 13168 # Number of memory ordering violations
603 system.cpu.iew.lsq.thread0.squashedStores 24454512 # Number of stores squashed
604 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
605 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
606 system.cpu.iew.lsq.thread0.rescheduledLoads 4520775 # Number of loads that were rescheduled
607 system.cpu.iew.lsq.thread0.cacheBlocked 4802645 # Number of times an access to memory failed due to the cache being blocked
608 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
609 system.cpu.iew.iewSquashCycles 14643507 # Number of cycles IEW is squashing
610 system.cpu.iew.iewBlockCycles 25316113 # Number of cycles IEW is blocking
611 system.cpu.iew.iewUnblockCycles 1330365 # Number of cycles IEW is unblocking
612 system.cpu.iew.iewDispatchedInsts 1947884031 # Number of instructions dispatched to IQ
613 system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
614 system.cpu.iew.iewDispLoadInsts 542536301 # Number of dispatched load instructions
615 system.cpu.iew.iewDispStoreInsts 199301557 # Number of dispatched store instructions
616 system.cpu.iew.iewDispNonSpecInsts 148 # Number of dispatched non-speculative instructions
617 system.cpu.iew.iewIQFullEvents 158933 # Number of times the IQ has become full, causing a stall
618 system.cpu.iew.iewLSQFullEvents 1170467 # Number of times the LSQ has become full, causing a stall
619 system.cpu.iew.memOrderViolationEvents 13168 # Number of memory order violations
620 system.cpu.iew.predictedTakenIncorrect 7700956 # Number of branches that were predicted taken incorrectly
621 system.cpu.iew.predictedNotTakenIncorrect 8705023 # Number of branches that were predicted not taken incorrectly
622 system.cpu.iew.branchMispredicts 16405979 # Number of branch mispredicts detected at execute
623 system.cpu.iew.iewExecutedInsts 1827745758 # Number of executed instructions
624 system.cpu.iew.iewExecLoadInsts 516865735 # Number of load instructions executed
625 system.cpu.iew.iewExecSquashedInsts 29663756 # Number of squashed instructions skipped in execute
626 system.cpu.iew.exec_swp 0 # number of swp insts executed
627 system.cpu.iew.exec_nop 79 # number of nop insts executed
628 system.cpu.iew.exec_refs 698617938 # number of memory reference insts executed
629 system.cpu.iew.exec_branches 229554698 # Number of branches executed
630 system.cpu.iew.exec_stores 181752203 # Number of stores executed
631 system.cpu.iew.exec_rate 1.184106 # Inst execution rate
632 system.cpu.iew.wb_sent 1808737138 # cumulative count of insts sent to commit
633 system.cpu.iew.wb_count 1805707322 # cumulative count of insts written-back
634 system.cpu.iew.wb_producers 1169287953 # num instructions producing a value
635 system.cpu.iew.wb_consumers 1689671414 # num instructions consuming a value
636 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
637 system.cpu.iew.wb_rate 1.169829 # insts written-back per cycle
638 system.cpu.iew.wb_fanout 0.692021 # average fanout of values written-back
639 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
640 system.cpu.commit.commitSquashedInsts 257958644 # The number of squashed insts skipped by commit
641 system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards
642 system.cpu.commit.branchMispredicts 14631182 # The number of times a branch was mispredicted
643 system.cpu.commit.committed_per_cycle::samples 1504006174 # Number of insts commited each cycle
644 system.cpu.commit.committed_per_cycle::mean 1.106400 # Number of insts commited each cycle
645 system.cpu.commit.committed_per_cycle::stdev 2.024308 # Number of insts commited each cycle
646 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
647 system.cpu.commit.committed_per_cycle::0 923727407 61.42% 61.42% # Number of insts commited each cycle
648 system.cpu.commit.committed_per_cycle::1 250637926 16.66% 78.08% # Number of insts commited each cycle
649 system.cpu.commit.committed_per_cycle::2 110048306 7.32% 85.40% # Number of insts commited each cycle
650 system.cpu.commit.committed_per_cycle::3 55269063 3.67% 89.07% # Number of insts commited each cycle
651 system.cpu.commit.committed_per_cycle::4 29308073 1.95% 91.02% # Number of insts commited each cycle
652 system.cpu.commit.committed_per_cycle::5 34102690 2.27% 93.29% # Number of insts commited each cycle
653 system.cpu.commit.committed_per_cycle::6 24713726 1.64% 94.93% # Number of insts commited each cycle
654 system.cpu.commit.committed_per_cycle::7 18129256 1.21% 96.14% # Number of insts commited each cycle
655 system.cpu.commit.committed_per_cycle::8 58069727 3.86% 100.00% # Number of insts commited each cycle
656 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
657 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
658 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
659 system.cpu.commit.committed_per_cycle::total 1504006174 # Number of insts commited each cycle
660 system.cpu.commit.committedInsts 1544563041 # Number of instructions committed
661 system.cpu.commit.committedOps 1664032433 # Number of ops (including micro ops) committed
662 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
663 system.cpu.commit.refs 633153379 # Number of memory references committed
664 system.cpu.commit.loads 458306334 # Number of loads committed
665 system.cpu.commit.membars 62 # Number of memory barriers committed
666 system.cpu.commit.branches 213462426 # Number of branches committed
667 system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
668 system.cpu.commit.int_insts 1477900421 # Number of committed integer instructions.
669 system.cpu.commit.function_calls 13665177 # Number of function calls committed.
670 system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
671 system.cpu.commit.op_class_0::IntAlu 1030178729 61.91% 61.91% # Class of committed instruction
672 system.cpu.commit.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction
673 system.cpu.commit.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction
674 system.cpu.commit.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction
675 system.cpu.commit.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction
676 system.cpu.commit.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction
677 system.cpu.commit.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction
678 system.cpu.commit.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction
679 system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction
680 system.cpu.commit.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction
681 system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction
682 system.cpu.commit.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction
683 system.cpu.commit.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction
684 system.cpu.commit.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction
685 system.cpu.commit.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction
686 system.cpu.commit.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction
687 system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction
688 system.cpu.commit.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction
689 system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction
690 system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction
691 system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction
692 system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction
693 system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction
694 system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction
695 system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction
696 system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 61.95% # Class of committed instruction
697 system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction
698 system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction
699 system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction
700 system.cpu.commit.op_class_0::MemRead 458306334 27.54% 89.49% # Class of committed instruction
701 system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Class of committed instruction
702 system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
703 system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
704 system.cpu.commit.op_class_0::total 1664032433 # Class of committed instruction
705 system.cpu.commit.bw_lim_events 58069727 # number cycles where commit BW limit reached
706 system.cpu.rob.rob_reads 3367926925 # The number of ROB reads
707 system.cpu.rob.rob_writes 3883468057 # The number of ROB writes
708 system.cpu.timesIdled 846 # Number of times that the entire CPU went into an idle state and unscheduled itself
709 system.cpu.idleCycles 78604 # Total number of cycles that the CPU has spent unscheduled due to idling
710 system.cpu.committedInsts 1544563023 # Number of Instructions Simulated
711 system.cpu.committedOps 1664032415 # Number of Ops (including micro ops) Simulated
712 system.cpu.cpi 0.999354 # CPI: Cycles Per Instruction
713 system.cpu.cpi_total 0.999354 # CPI: Total CPI of All Threads
714 system.cpu.ipc 1.000646 # IPC: Instructions Per Cycle
715 system.cpu.ipc_total 1.000646 # IPC: Total IPC of All Threads
716 system.cpu.int_regfile_reads 2175695472 # number of integer regfile reads
717 system.cpu.int_regfile_writes 1261559121 # number of integer regfile writes
718 system.cpu.fp_regfile_reads 38 # number of floating regfile reads
719 system.cpu.fp_regfile_writes 48 # number of floating regfile writes
720 system.cpu.cc_regfile_reads 6965502930 # number of cc regfile reads
721 system.cpu.cc_regfile_writes 551873305 # number of cc regfile writes
722 system.cpu.misc_regfile_reads 675842878 # number of misc regfile reads
723 system.cpu.misc_regfile_writes 124 # number of misc regfile writes
724 system.cpu.dcache.tags.replacements 17005493 # number of replacements
725 system.cpu.dcache.tags.tagsinuse 511.964646 # Cycle average of tags in use
726 system.cpu.dcache.tags.total_refs 638183172 # Total number of references to valid blocks.
727 system.cpu.dcache.tags.sampled_refs 17006005 # Sample count of references to valid blocks.
728 system.cpu.dcache.tags.avg_refs 37.526931 # Average number of references to valid blocks.
729 system.cpu.dcache.tags.warmup_cycle 79063000 # Cycle when the warmup percentage was hit.
730 system.cpu.dcache.tags.occ_blocks::cpu.data 511.964646 # Average occupied blocks per requestor
731 system.cpu.dcache.tags.occ_percent::cpu.data 0.999931 # Average percentage of cache occupancy
732 system.cpu.dcache.tags.occ_percent::total 0.999931 # Average percentage of cache occupancy
733 system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
734 system.cpu.dcache.tags.age_task_id_blocks_1024::0 392 # Occupied blocks per task id
735 system.cpu.dcache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id
736 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
737 system.cpu.dcache.tags.tag_accesses 1335677307 # Number of tag accesses
738 system.cpu.dcache.tags.data_accesses 1335677307 # Number of data accesses
739 system.cpu.dcache.ReadReq_hits::cpu.data 469397613 # number of ReadReq hits
740 system.cpu.dcache.ReadReq_hits::total 469397613 # number of ReadReq hits
741 system.cpu.dcache.WriteReq_hits::cpu.data 168785441 # number of WriteReq hits
742 system.cpu.dcache.WriteReq_hits::total 168785441 # number of WriteReq hits
743 system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits
744 system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits
745 system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
746 system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
747 system.cpu.dcache.demand_hits::cpu.data 638183054 # number of demand (read+write) hits
748 system.cpu.dcache.demand_hits::total 638183054 # number of demand (read+write) hits
749 system.cpu.dcache.overall_hits::cpu.data 638183054 # number of overall hits
750 system.cpu.dcache.overall_hits::total 638183054 # number of overall hits
751 system.cpu.dcache.ReadReq_misses::cpu.data 17351867 # number of ReadReq misses
752 system.cpu.dcache.ReadReq_misses::total 17351867 # number of ReadReq misses
753 system.cpu.dcache.WriteReq_misses::cpu.data 3800606 # number of WriteReq misses
754 system.cpu.dcache.WriteReq_misses::total 3800606 # number of WriteReq misses
755 system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses
756 system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses
757 system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses
758 system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses
759 system.cpu.dcache.demand_misses::cpu.data 21152473 # number of demand (read+write) misses
760 system.cpu.dcache.demand_misses::total 21152473 # number of demand (read+write) misses
761 system.cpu.dcache.overall_misses::cpu.data 21152475 # number of overall misses
762 system.cpu.dcache.overall_misses::total 21152475 # number of overall misses
763 system.cpu.dcache.ReadReq_miss_latency::cpu.data 417182903209 # number of ReadReq miss cycles
764 system.cpu.dcache.ReadReq_miss_latency::total 417182903209 # number of ReadReq miss cycles
765 system.cpu.dcache.WriteReq_miss_latency::cpu.data 149917932873 # number of WriteReq miss cycles
766 system.cpu.dcache.WriteReq_miss_latency::total 149917932873 # number of WriteReq miss cycles
767 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 358750 # number of LoadLockedReq miss cycles
768 system.cpu.dcache.LoadLockedReq_miss_latency::total 358750 # number of LoadLockedReq miss cycles
769 system.cpu.dcache.demand_miss_latency::cpu.data 567100836082 # number of demand (read+write) miss cycles
770 system.cpu.dcache.demand_miss_latency::total 567100836082 # number of demand (read+write) miss cycles
771 system.cpu.dcache.overall_miss_latency::cpu.data 567100836082 # number of overall miss cycles
772 system.cpu.dcache.overall_miss_latency::total 567100836082 # number of overall miss cycles
773 system.cpu.dcache.ReadReq_accesses::cpu.data 486749480 # number of ReadReq accesses(hits+misses)
774 system.cpu.dcache.ReadReq_accesses::total 486749480 # number of ReadReq accesses(hits+misses)
775 system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
776 system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
777 system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses)
778 system.cpu.dcache.SoftPFReq_accesses::total 2 # number of SoftPFReq accesses(hits+misses)
779 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
780 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
781 system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
782 system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
783 system.cpu.dcache.demand_accesses::cpu.data 659335527 # number of demand (read+write) accesses
784 system.cpu.dcache.demand_accesses::total 659335527 # number of demand (read+write) accesses
785 system.cpu.dcache.overall_accesses::cpu.data 659335529 # number of overall (read+write) accesses
786 system.cpu.dcache.overall_accesses::total 659335529 # number of overall (read+write) accesses
787 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035648 # miss rate for ReadReq accesses
788 system.cpu.dcache.ReadReq_miss_rate::total 0.035648 # miss rate for ReadReq accesses
789 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022022 # miss rate for WriteReq accesses
790 system.cpu.dcache.WriteReq_miss_rate::total 0.022022 # miss rate for WriteReq accesses
791 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses
792 system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses
793 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses
794 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses
795 system.cpu.dcache.demand_miss_rate::cpu.data 0.032082 # miss rate for demand accesses
796 system.cpu.dcache.demand_miss_rate::total 0.032082 # miss rate for demand accesses
797 system.cpu.dcache.overall_miss_rate::cpu.data 0.032082 # miss rate for overall accesses
798 system.cpu.dcache.overall_miss_rate::total 0.032082 # miss rate for overall accesses
799 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24042.536933 # average ReadReq miss latency
800 system.cpu.dcache.ReadReq_avg_miss_latency::total 24042.536933 # average ReadReq miss latency
801 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39445.797032 # average WriteReq miss latency
802 system.cpu.dcache.WriteReq_avg_miss_latency::total 39445.797032 # average WriteReq miss latency
803 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 89687.500000 # average LoadLockedReq miss latency
804 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 89687.500000 # average LoadLockedReq miss latency
805 system.cpu.dcache.demand_avg_miss_latency::cpu.data 26810.143480 # average overall miss latency
806 system.cpu.dcache.demand_avg_miss_latency::total 26810.143480 # average overall miss latency
807 system.cpu.dcache.overall_avg_miss_latency::cpu.data 26810.140945 # average overall miss latency
808 system.cpu.dcache.overall_avg_miss_latency::total 26810.140945 # average overall miss latency
809 system.cpu.dcache.blocked_cycles::no_mshrs 20723795 # number of cycles access was blocked
810 system.cpu.dcache.blocked_cycles::no_targets 3315809 # number of cycles access was blocked
811 system.cpu.dcache.blocked::no_mshrs 944207 # number of cycles access was blocked
812 system.cpu.dcache.blocked::no_targets 67033 # number of cycles access was blocked
813 system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.948360 # average number of cycles each access was blocked
814 system.cpu.dcache.avg_blocked_cycles::no_targets 49.465323 # average number of cycles each access was blocked
815 system.cpu.dcache.fast_writes 0 # number of fast writes performed
816 system.cpu.dcache.cache_copies 0 # number of cache copies performed
817 system.cpu.dcache.writebacks::writebacks 4835251 # number of writebacks
818 system.cpu.dcache.writebacks::total 4835251 # number of writebacks
819 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3083373 # number of ReadReq MSHR hits
820 system.cpu.dcache.ReadReq_mshr_hits::total 3083373 # number of ReadReq MSHR hits
821 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1063096 # number of WriteReq MSHR hits
822 system.cpu.dcache.WriteReq_mshr_hits::total 1063096 # number of WriteReq MSHR hits
823 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits
824 system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits
825 system.cpu.dcache.demand_mshr_hits::cpu.data 4146469 # number of demand (read+write) MSHR hits
826 system.cpu.dcache.demand_mshr_hits::total 4146469 # number of demand (read+write) MSHR hits
827 system.cpu.dcache.overall_mshr_hits::cpu.data 4146469 # number of overall MSHR hits
828 system.cpu.dcache.overall_mshr_hits::total 4146469 # number of overall MSHR hits
829 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14268494 # number of ReadReq MSHR misses
830 system.cpu.dcache.ReadReq_mshr_misses::total 14268494 # number of ReadReq MSHR misses
831 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737510 # number of WriteReq MSHR misses
832 system.cpu.dcache.WriteReq_mshr_misses::total 2737510 # number of WriteReq MSHR misses
833 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
834 system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
835 system.cpu.dcache.demand_mshr_misses::cpu.data 17006004 # number of demand (read+write) MSHR misses
836 system.cpu.dcache.demand_mshr_misses::total 17006004 # number of demand (read+write) MSHR misses
837 system.cpu.dcache.overall_mshr_misses::cpu.data 17006005 # number of overall MSHR misses
838 system.cpu.dcache.overall_mshr_misses::total 17006005 # number of overall MSHR misses
839 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 329072767985 # number of ReadReq MSHR miss cycles
840 system.cpu.dcache.ReadReq_mshr_miss_latency::total 329072767985 # number of ReadReq MSHR miss cycles
841 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115107857313 # number of WriteReq MSHR miss cycles
842 system.cpu.dcache.WriteReq_mshr_miss_latency::total 115107857313 # number of WriteReq MSHR miss cycles
843 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 67750 # number of SoftPFReq MSHR miss cycles
844 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 67750 # number of SoftPFReq MSHR miss cycles
845 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 444180625298 # number of demand (read+write) MSHR miss cycles
846 system.cpu.dcache.demand_mshr_miss_latency::total 444180625298 # number of demand (read+write) MSHR miss cycles
847 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 444180693048 # number of overall MSHR miss cycles
848 system.cpu.dcache.overall_mshr_miss_latency::total 444180693048 # number of overall MSHR miss cycles
849 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029314 # mshr miss rate for ReadReq accesses
850 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029314 # mshr miss rate for ReadReq accesses
851 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses
852 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses
853 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses
854 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses
855 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025793 # mshr miss rate for demand accesses
856 system.cpu.dcache.demand_mshr_miss_rate::total 0.025793 # mshr miss rate for demand accesses
857 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025793 # mshr miss rate for overall accesses
858 system.cpu.dcache.overall_mshr_miss_rate::total 0.025793 # mshr miss rate for overall accesses
859 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23062.894233 # average ReadReq mshr miss latency
860 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23062.894233 # average ReadReq mshr miss latency
861 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42048.378750 # average WriteReq mshr miss latency
862 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42048.378750 # average WriteReq mshr miss latency
863 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 67750 # average SoftPFReq mshr miss latency
864 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 67750 # average SoftPFReq mshr miss latency
865 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26119.047443 # average overall mshr miss latency
866 system.cpu.dcache.demand_avg_mshr_miss_latency::total 26119.047443 # average overall mshr miss latency
867 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26119.049891 # average overall mshr miss latency
868 system.cpu.dcache.overall_avg_mshr_miss_latency::total 26119.049891 # average overall mshr miss latency
869 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
870 system.cpu.icache.tags.replacements 588 # number of replacements
871 system.cpu.icache.tags.tagsinuse 446.068543 # Cycle average of tags in use
872 system.cpu.icache.tags.total_refs 656912599 # Total number of references to valid blocks.
873 system.cpu.icache.tags.sampled_refs 1076 # Sample count of references to valid blocks.
874 system.cpu.icache.tags.avg_refs 610513.567844 # Average number of references to valid blocks.
875 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
876 system.cpu.icache.tags.occ_blocks::cpu.inst 446.068543 # Average occupied blocks per requestor
877 system.cpu.icache.tags.occ_percent::cpu.inst 0.871228 # Average percentage of cache occupancy
878 system.cpu.icache.tags.occ_percent::total 0.871228 # Average percentage of cache occupancy
879 system.cpu.icache.tags.occ_task_id_blocks::1024 488 # Occupied blocks per task id
880 system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
881 system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id
882 system.cpu.icache.tags.age_task_id_blocks_1024::4 442 # Occupied blocks per task id
883 system.cpu.icache.tags.occ_task_id_percent::1024 0.953125 # Percentage of cache occupancy per task id
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885 system.cpu.icache.tags.data_accesses 1313829498 # Number of data accesses
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887 system.cpu.icache.ReadReq_hits::total 656912599 # number of ReadReq hits
888 system.cpu.icache.demand_hits::cpu.inst 656912599 # number of demand (read+write) hits
889 system.cpu.icache.demand_hits::total 656912599 # number of demand (read+write) hits
890 system.cpu.icache.overall_hits::cpu.inst 656912599 # number of overall hits
891 system.cpu.icache.overall_hits::total 656912599 # number of overall hits
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893 system.cpu.icache.ReadReq_misses::total 1612 # number of ReadReq misses
894 system.cpu.icache.demand_misses::cpu.inst 1612 # number of demand (read+write) misses
895 system.cpu.icache.demand_misses::total 1612 # number of demand (read+write) misses
896 system.cpu.icache.overall_misses::cpu.inst 1612 # number of overall misses
897 system.cpu.icache.overall_misses::total 1612 # number of overall misses
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899 system.cpu.icache.ReadReq_miss_latency::total 102924516 # number of ReadReq miss cycles
900 system.cpu.icache.demand_miss_latency::cpu.inst 102924516 # number of demand (read+write) miss cycles
901 system.cpu.icache.demand_miss_latency::total 102924516 # number of demand (read+write) miss cycles
902 system.cpu.icache.overall_miss_latency::cpu.inst 102924516 # number of overall miss cycles
903 system.cpu.icache.overall_miss_latency::total 102924516 # number of overall miss cycles
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905 system.cpu.icache.ReadReq_accesses::total 656914211 # number of ReadReq accesses(hits+misses)
906 system.cpu.icache.demand_accesses::cpu.inst 656914211 # number of demand (read+write) accesses
907 system.cpu.icache.demand_accesses::total 656914211 # number of demand (read+write) accesses
908 system.cpu.icache.overall_accesses::cpu.inst 656914211 # number of overall (read+write) accesses
909 system.cpu.icache.overall_accesses::total 656914211 # number of overall (read+write) accesses
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911 system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses
912 system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses
913 system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses
914 system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses
915 system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses
916 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63848.955335 # average ReadReq miss latency
917 system.cpu.icache.ReadReq_avg_miss_latency::total 63848.955335 # average ReadReq miss latency
918 system.cpu.icache.demand_avg_miss_latency::cpu.inst 63848.955335 # average overall miss latency
919 system.cpu.icache.demand_avg_miss_latency::total 63848.955335 # average overall miss latency
920 system.cpu.icache.overall_avg_miss_latency::cpu.inst 63848.955335 # average overall miss latency
921 system.cpu.icache.overall_avg_miss_latency::total 63848.955335 # average overall miss latency
922 system.cpu.icache.blocked_cycles::no_mshrs 17306 # number of cycles access was blocked
923 system.cpu.icache.blocked_cycles::no_targets 307 # number of cycles access was blocked
924 system.cpu.icache.blocked::no_mshrs 186 # number of cycles access was blocked
925 system.cpu.icache.blocked::no_targets 8 # number of cycles access was blocked
926 system.cpu.icache.avg_blocked_cycles::no_mshrs 93.043011 # average number of cycles each access was blocked
927 system.cpu.icache.avg_blocked_cycles::no_targets 38.375000 # average number of cycles each access was blocked
928 system.cpu.icache.fast_writes 0 # number of fast writes performed
929 system.cpu.icache.cache_copies 0 # number of cache copies performed
930 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 536 # number of ReadReq MSHR hits
931 system.cpu.icache.ReadReq_mshr_hits::total 536 # number of ReadReq MSHR hits
932 system.cpu.icache.demand_mshr_hits::cpu.inst 536 # number of demand (read+write) MSHR hits
933 system.cpu.icache.demand_mshr_hits::total 536 # number of demand (read+write) MSHR hits
934 system.cpu.icache.overall_mshr_hits::cpu.inst 536 # number of overall MSHR hits
935 system.cpu.icache.overall_mshr_hits::total 536 # number of overall MSHR hits
936 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1076 # number of ReadReq MSHR misses
937 system.cpu.icache.ReadReq_mshr_misses::total 1076 # number of ReadReq MSHR misses
938 system.cpu.icache.demand_mshr_misses::cpu.inst 1076 # number of demand (read+write) MSHR misses
939 system.cpu.icache.demand_mshr_misses::total 1076 # number of demand (read+write) MSHR misses
940 system.cpu.icache.overall_mshr_misses::cpu.inst 1076 # number of overall MSHR misses
941 system.cpu.icache.overall_mshr_misses::total 1076 # number of overall MSHR misses
942 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 76203217 # number of ReadReq MSHR miss cycles
943 system.cpu.icache.ReadReq_mshr_miss_latency::total 76203217 # number of ReadReq MSHR miss cycles
944 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 76203217 # number of demand (read+write) MSHR miss cycles
945 system.cpu.icache.demand_mshr_miss_latency::total 76203217 # number of demand (read+write) MSHR miss cycles
946 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 76203217 # number of overall MSHR miss cycles
947 system.cpu.icache.overall_mshr_miss_latency::total 76203217 # number of overall MSHR miss cycles
948 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses
949 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses
950 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses
951 system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses
952 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses
953 system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
954 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70820.833643 # average ReadReq mshr miss latency
955 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70820.833643 # average ReadReq mshr miss latency
956 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70820.833643 # average overall mshr miss latency
957 system.cpu.icache.demand_avg_mshr_miss_latency::total 70820.833643 # average overall mshr miss latency
958 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70820.833643 # average overall mshr miss latency
959 system.cpu.icache.overall_avg_mshr_miss_latency::total 70820.833643 # average overall mshr miss latency
960 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
961 system.cpu.l2cache.prefetcher.num_hwpf_issued 10941726 # number of hwpf issued
962 system.cpu.l2cache.prefetcher.pfIdentified 11630409 # number of prefetch candidates identified
963 system.cpu.l2cache.prefetcher.pfBufferHit 431114 # number of redundant prefetches already in prefetch queue
964 system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
965 system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
966 system.cpu.l2cache.prefetcher.pfSpanPage 4654951 # number of prefetches not generated due to page crossing
967 system.cpu.l2cache.tags.replacements 4713207 # number of replacements
968 system.cpu.l2cache.tags.tagsinuse 16130.406064 # Cycle average of tags in use
969 system.cpu.l2cache.tags.total_refs 15325447 # Total number of references to valid blocks.
970 system.cpu.l2cache.tags.sampled_refs 4729134 # Sample count of references to valid blocks.
971 system.cpu.l2cache.tags.avg_refs 3.240646 # Average number of references to valid blocks.
972 system.cpu.l2cache.tags.warmup_cycle 29468558500 # Cycle when the warmup percentage was hit.
973 system.cpu.l2cache.tags.occ_blocks::writebacks 5233.732135 # Average occupied blocks per requestor
974 system.cpu.l2cache.tags.occ_blocks::cpu.inst 18.908605 # Average occupied blocks per requestor
975 system.cpu.l2cache.tags.occ_blocks::cpu.data 7574.796716 # Average occupied blocks per requestor
976 system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 3302.968608 # Average occupied blocks per requestor
977 system.cpu.l2cache.tags.occ_percent::writebacks 0.319442 # Average percentage of cache occupancy
978 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001154 # Average percentage of cache occupancy
979 system.cpu.l2cache.tags.occ_percent::cpu.data 0.462329 # Average percentage of cache occupancy
980 system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.201597 # Average percentage of cache occupancy
981 system.cpu.l2cache.tags.occ_percent::total 0.984522 # Average percentage of cache occupancy
982 system.cpu.l2cache.tags.occ_task_id_blocks::1022 731 # Occupied blocks per task id
983 system.cpu.l2cache.tags.occ_task_id_blocks::1024 15196 # Occupied blocks per task id
984 system.cpu.l2cache.tags.age_task_id_blocks_1022::0 5 # Occupied blocks per task id
985 system.cpu.l2cache.tags.age_task_id_blocks_1022::1 525 # Occupied blocks per task id
986 system.cpu.l2cache.tags.age_task_id_blocks_1022::3 201 # Occupied blocks per task id
987 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 466 # Occupied blocks per task id
988 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2455 # Occupied blocks per task id
989 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1253 # Occupied blocks per task id
990 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9206 # Occupied blocks per task id
991 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1816 # Occupied blocks per task id
992 system.cpu.l2cache.tags.occ_task_id_percent::1022 0.044617 # Percentage of cache occupancy per task id
993 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.927490 # Percentage of cache occupancy per task id
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995 system.cpu.l2cache.tags.data_accesses 356943997 # Number of data accesses
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998 system.cpu.l2cache.ReadReq_hits::total 11484217 # number of ReadReq hits
999 system.cpu.l2cache.Writeback_hits::writebacks 4835251 # number of Writeback hits
1000 system.cpu.l2cache.Writeback_hits::total 4835251 # number of Writeback hits
1001 system.cpu.l2cache.ReadExReq_hits::cpu.data 1752141 # number of ReadExReq hits
1002 system.cpu.l2cache.ReadExReq_hits::total 1752141 # number of ReadExReq hits
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1004 system.cpu.l2cache.demand_hits::cpu.data 13236315 # number of demand (read+write) hits
1005 system.cpu.l2cache.demand_hits::total 13236358 # number of demand (read+write) hits
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1007 system.cpu.l2cache.overall_hits::cpu.data 13236315 # number of overall hits
1008 system.cpu.l2cache.overall_hits::total 13236358 # number of overall hits
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1013 system.cpu.l2cache.ReadExReq_misses::total 985410 # number of ReadExReq misses
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1029 system.cpu.l2cache.overall_miss_latency::cpu.data 339189559125 # number of overall miss cycles
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1033 system.cpu.l2cache.ReadReq_accesses::total 14269530 # number of ReadReq accesses(hits+misses)
1034 system.cpu.l2cache.Writeback_accesses::writebacks 4835251 # number of Writeback accesses(hits+misses)
1035 system.cpu.l2cache.Writeback_accesses::total 4835251 # number of Writeback accesses(hits+misses)
1036 system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737551 # number of ReadExReq accesses(hits+misses)
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1042 system.cpu.l2cache.overall_accesses::cpu.data 17006005 # number of overall (read+write) accesses
1043 system.cpu.l2cache.overall_accesses::total 17007081 # number of overall (read+write) accesses
1044 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.960037 # miss rate for ReadReq accesses
1045 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.195135 # miss rate for ReadReq accesses
1046 system.cpu.l2cache.ReadReq_miss_rate::total 0.195193 # miss rate for ReadReq accesses
1047 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.359960 # miss rate for ReadExReq accesses
1048 system.cpu.l2cache.ReadExReq_miss_rate::total 0.359960 # miss rate for ReadExReq accesses
1049 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.960037 # miss rate for demand accesses
1050 system.cpu.l2cache.demand_miss_rate::cpu.data 0.221668 # miss rate for demand accesses
1051 system.cpu.l2cache.demand_miss_rate::total 0.221715 # miss rate for demand accesses
1052 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.960037 # miss rate for overall accesses
1053 system.cpu.l2cache.overall_miss_rate::cpu.data 0.221668 # miss rate for overall accesses
1054 system.cpu.l2cache.overall_miss_rate::total 0.221715 # miss rate for overall accesses
1055 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72964.887706 # average ReadReq miss latency
1056 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85856.024946 # average ReadReq miss latency
1057 system.cpu.l2cache.ReadReq_avg_miss_latency::total 85851.243960 # average ReadReq miss latency
1058 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101625.055547 # average ReadExReq miss latency
1059 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101625.055547 # average ReadExReq miss latency
1060 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72964.887706 # average overall miss latency
1061 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89978.104068 # average overall miss latency
1062 system.cpu.l2cache.demand_avg_miss_latency::total 89973.443251 # average overall miss latency
1063 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72964.887706 # average overall miss latency
1064 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89978.104068 # average overall miss latency
1065 system.cpu.l2cache.overall_avg_miss_latency::total 89973.443251 # average overall miss latency
1066 system.cpu.l2cache.blocked_cycles::no_mshrs 846 # number of cycles access was blocked
1067 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1068 system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked
1069 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1070 system.cpu.l2cache.avg_blocked_cycles::no_mshrs 211.500000 # average number of cycles each access was blocked
1071 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1072 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1073 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1074 system.cpu.l2cache.writebacks::writebacks 1639072 # number of writebacks
1075 system.cpu.l2cache.writebacks::total 1639072 # number of writebacks
1076 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 36084 # number of ReadReq MSHR hits
1077 system.cpu.l2cache.ReadReq_mshr_hits::total 36084 # number of ReadReq MSHR hits
1078 system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3647 # number of ReadExReq MSHR hits
1079 system.cpu.l2cache.ReadExReq_mshr_hits::total 3647 # number of ReadExReq MSHR hits
1080 system.cpu.l2cache.demand_mshr_hits::cpu.data 39731 # number of demand (read+write) MSHR hits
1081 system.cpu.l2cache.demand_mshr_hits::total 39731 # number of demand (read+write) MSHR hits
1082 system.cpu.l2cache.overall_mshr_hits::cpu.data 39731 # number of overall MSHR hits
1083 system.cpu.l2cache.overall_mshr_hits::total 39731 # number of overall MSHR hits
1084 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1033 # number of ReadReq MSHR misses
1085 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 2748196 # number of ReadReq MSHR misses
1086 system.cpu.l2cache.ReadReq_mshr_misses::total 2749229 # number of ReadReq MSHR misses
1087 system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 993723 # number of HardPFReq MSHR misses
1088 system.cpu.l2cache.HardPFReq_mshr_misses::total 993723 # number of HardPFReq MSHR misses
1089 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 981763 # number of ReadExReq MSHR misses
1090 system.cpu.l2cache.ReadExReq_mshr_misses::total 981763 # number of ReadExReq MSHR misses
1091 system.cpu.l2cache.demand_mshr_misses::cpu.inst 1033 # number of demand (read+write) MSHR misses
1092 system.cpu.l2cache.demand_mshr_misses::cpu.data 3729959 # number of demand (read+write) MSHR misses
1093 system.cpu.l2cache.demand_mshr_misses::total 3730992 # number of demand (read+write) MSHR misses
1094 system.cpu.l2cache.overall_mshr_misses::cpu.inst 1033 # number of overall MSHR misses
1095 system.cpu.l2cache.overall_mshr_misses::cpu.data 3729959 # number of overall MSHR misses
1096 system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 993723 # number of overall MSHR misses
1097 system.cpu.l2cache.overall_mshr_misses::total 4724715 # number of overall MSHR misses
1098 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 66585771 # number of ReadReq MSHR miss cycles
1099 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 212846915589 # number of ReadReq MSHR miss cycles
1100 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 212913501360 # number of ReadReq MSHR miss cycles
1101 system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 71046693133 # number of HardPFReq MSHR miss cycles
1102 system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 71046693133 # number of HardPFReq MSHR miss cycles
1103 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 91372170669 # number of ReadExReq MSHR miss cycles
1104 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 91372170669 # number of ReadExReq MSHR miss cycles
1105 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66585771 # number of demand (read+write) MSHR miss cycles
1106 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 304219086258 # number of demand (read+write) MSHR miss cycles
1107 system.cpu.l2cache.demand_mshr_miss_latency::total 304285672029 # number of demand (read+write) MSHR miss cycles
1108 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66585771 # number of overall MSHR miss cycles
1109 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 304219086258 # number of overall MSHR miss cycles
1110 system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 71046693133 # number of overall MSHR miss cycles
1111 system.cpu.l2cache.overall_mshr_miss_latency::total 375332365162 # number of overall MSHR miss cycles
1112 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960037 # mshr miss rate for ReadReq accesses
1113 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.192606 # mshr miss rate for ReadReq accesses
1114 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.192664 # mshr miss rate for ReadReq accesses
1115 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1116 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1117 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358628 # mshr miss rate for ReadExReq accesses
1118 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358628 # mshr miss rate for ReadExReq accesses
1119 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960037 # mshr miss rate for demand accesses
1120 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.219332 # mshr miss rate for demand accesses
1121 system.cpu.l2cache.demand_mshr_miss_rate::total 0.219379 # mshr miss rate for demand accesses
1122 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960037 # mshr miss rate for overall accesses
1123 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.219332 # mshr miss rate for overall accesses
1124 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
1125 system.cpu.l2cache.overall_mshr_miss_rate::total 0.277809 # mshr miss rate for overall accesses
1126 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64458.636012 # average ReadReq mshr miss latency
1127 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77449.685390 # average ReadReq mshr miss latency
1128 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77444.804111 # average ReadReq mshr miss latency
1129 system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 71495.470199 # average HardPFReq mshr miss latency
1130 system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 71495.470199 # average HardPFReq mshr miss latency
1131 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 93069.478753 # average ReadExReq mshr miss latency
1132 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 93069.478753 # average ReadExReq mshr miss latency
1133 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64458.636012 # average overall mshr miss latency
1134 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81560.973259 # average overall mshr miss latency
1135 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81556.238134 # average overall mshr miss latency
1136 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64458.636012 # average overall mshr miss latency
1137 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81560.973259 # average overall mshr miss latency
1138 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 71495.470199 # average overall mshr miss latency
1139 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79440.212830 # average overall mshr miss latency
1140 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1141 system.cpu.toL2Bus.trans_dist::ReadReq 14269530 # Transaction distribution
1142 system.cpu.toL2Bus.trans_dist::ReadResp 14269530 # Transaction distribution
1143 system.cpu.toL2Bus.trans_dist::Writeback 4835251 # Transaction distribution
1144 system.cpu.toL2Bus.trans_dist::HardPFReq 1300143 # Transaction distribution
1145 system.cpu.toL2Bus.trans_dist::ReadExReq 2737551 # Transaction distribution
1146 system.cpu.toL2Bus.trans_dist::ReadExResp 2737551 # Transaction distribution
1147 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2152 # Packet count per connected master and slave (bytes)
1148 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 38847261 # Packet count per connected master and slave (bytes)
1149 system.cpu.toL2Bus.pkt_count::total 38849413 # Packet count per connected master and slave (bytes)
1150 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 68864 # Cumulative packet size per connected master and slave (bytes)
1151 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1397840384 # Cumulative packet size per connected master and slave (bytes)
1152 system.cpu.toL2Bus.pkt_size::total 1397909248 # Cumulative packet size per connected master and slave (bytes)
1153 system.cpu.toL2Bus.snoops 1300143 # Total snoops (count)
1154 system.cpu.toL2Bus.snoop_fanout::samples 23142477 # Request fanout histogram
1155 system.cpu.toL2Bus.snoop_fanout::mean 3.056180 # Request fanout histogram
1156 system.cpu.toL2Bus.snoop_fanout::stdev 0.230269 # Request fanout histogram
1157 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1158 system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1159 system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
1160 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
1161 system.cpu.toL2Bus.snoop_fanout::3 21842334 94.38% 94.38% # Request fanout histogram
1162 system.cpu.toL2Bus.snoop_fanout::4 1300143 5.62% 100.00% # Request fanout histogram
1163 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1164 system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
1165 system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
1166 system.cpu.toL2Bus.snoop_fanout::total 23142477 # Request fanout histogram
1167 system.cpu.toL2Bus.reqLayer0.occupancy 15756418748 # Layer occupancy (ticks)
1168 system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%)
1169 system.cpu.toL2Bus.respLayer0.occupancy 1812271 # Layer occupancy (ticks)
1170 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1171 system.cpu.toL2Bus.respLayer1.occupancy 26100835834 # Layer occupancy (ticks)
1172 system.cpu.toL2Bus.respLayer1.utilization 3.4 # Layer utilization (%)
1173 system.membus.trans_dist::ReadReq 3739202 # Transaction distribution
1174 system.membus.trans_dist::ReadResp 3739202 # Transaction distribution
1175 system.membus.trans_dist::Writeback 1639072 # Transaction distribution
1176 system.membus.trans_dist::ReadExReq 982028 # Transaction distribution
1177 system.membus.trans_dist::ReadExResp 982028 # Transaction distribution
1178 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11081532 # Packet count per connected master and slave (bytes)
1179 system.membus.pkt_count::total 11081532 # Packet count per connected master and slave (bytes)
1180 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 407059328 # Cumulative packet size per connected master and slave (bytes)
1181 system.membus.pkt_size::total 407059328 # Cumulative packet size per connected master and slave (bytes)
1182 system.membus.snoops 0 # Total snoops (count)
1183 system.membus.snoop_fanout::samples 6360302 # Request fanout histogram
1184 system.membus.snoop_fanout::mean 0 # Request fanout histogram
1185 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1186 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1187 system.membus.snoop_fanout::0 6360302 100.00% 100.00% # Request fanout histogram
1188 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
1189 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1190 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1191 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
1192 system.membus.snoop_fanout::total 6360302 # Request fanout histogram
1193 system.membus.reqLayer0.occupancy 14493239223 # Layer occupancy (ticks)
1194 system.membus.reqLayer0.utilization 1.9 # Layer utilization (%)
1195 system.membus.respLayer1.occupancy 25671846860 # Layer occupancy (ticks)
1196 system.membus.respLayer1.utilization 3.3 # Layer utilization (%)
1198 ---------- End Simulation Statistics ----------
projects / gem5.git / blob