2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.506354 # Number of seconds simulated
4 sim_ticks 506353996500 # Number of ticks simulated
5 final_tick 506353996500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 105319 # Simulator instruction rate (inst/s)
8 host_op_rate 117491 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 34526611 # Simulator tick rate (ticks/s)
10 host_mem_usage 552892 # Number of bytes of host memory used
11 host_seconds 14665.62 # Real time elapsed on the host
12 sim_insts 1544563023 # Number of instructions simulated
13 sim_ops 1723073835 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 48000 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 143771904 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 143819904 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 48000 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 48000 # Number of instructions bytes read from this memory
19 system.physmem.bytes_written::writebacks 70451968 # Number of bytes written to this memory
20 system.physmem.bytes_written::total 70451968 # Number of bytes written to this memory
21 system.physmem.num_reads::cpu.inst 750 # Number of read requests responded to by this memory
22 system.physmem.num_reads::cpu.data 2246436 # Number of read requests responded to by this memory
23 system.physmem.num_reads::total 2247186 # Number of read requests responded to by this memory
24 system.physmem.num_writes::writebacks 1100812 # Number of write requests responded to by this memory
25 system.physmem.num_writes::total 1100812 # Number of write requests responded to by this memory
26 system.physmem.bw_read::cpu.inst 94795 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_read::cpu.data 283935557 # Total read bandwidth from this memory (bytes/s)
28 system.physmem.bw_read::total 284030352 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_inst_read::cpu.inst 94795 # Instruction read bandwidth from this memory (bytes/s)
30 system.physmem.bw_inst_read::total 94795 # Instruction read bandwidth from this memory (bytes/s)
31 system.physmem.bw_write::writebacks 139135799 # Write bandwidth from this memory (bytes/s)
32 system.physmem.bw_write::total 139135799 # Write bandwidth from this memory (bytes/s)
33 system.physmem.bw_total::writebacks 139135799 # Total bandwidth to/from this memory (bytes/s)
34 system.physmem.bw_total::cpu.inst 94795 # Total bandwidth to/from this memory (bytes/s)
35 system.physmem.bw_total::cpu.data 283935557 # Total bandwidth to/from this memory (bytes/s)
36 system.physmem.bw_total::total 423166152 # Total bandwidth to/from this memory (bytes/s)
37 system.physmem.readReqs 2247186 # Total number of read requests seen
38 system.physmem.writeReqs 1100812 # Total number of write requests seen
39 system.physmem.cpureqs 3347998 # Reqs generatd by CPU via cache - shady
40 system.physmem.bytesRead 143819904 # Total number of bytes read from memory
41 system.physmem.bytesWritten 70451968 # Total number of bytes written to memory
42 system.physmem.bytesConsumedRd 143819904 # bytesRead derated as per pkt->getSize()
43 system.physmem.bytesConsumedWr 70451968 # bytesWritten derated as per pkt->getSize()
44 system.physmem.servicedByWrQ 672 # Number of read reqs serviced by write Q
45 system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
46 system.physmem.perBankRdReqs::0 139825 # Track reads on a per bank basis
47 system.physmem.perBankRdReqs::1 143804 # Track reads on a per bank basis
48 system.physmem.perBankRdReqs::2 141798 # Track reads on a per bank basis
49 system.physmem.perBankRdReqs::3 141106 # Track reads on a per bank basis
50 system.physmem.perBankRdReqs::4 137923 # Track reads on a per bank basis
51 system.physmem.perBankRdReqs::5 140335 # Track reads on a per bank basis
52 system.physmem.perBankRdReqs::6 141438 # Track reads on a per bank basis
53 system.physmem.perBankRdReqs::7 140855 # Track reads on a per bank basis
54 system.physmem.perBankRdReqs::8 141349 # Track reads on a per bank basis
55 system.physmem.perBankRdReqs::9 139500 # Track reads on a per bank basis
56 system.physmem.perBankRdReqs::10 140412 # Track reads on a per bank basis
57 system.physmem.perBankRdReqs::11 140930 # Track reads on a per bank basis
58 system.physmem.perBankRdReqs::12 137255 # Track reads on a per bank basis
59 system.physmem.perBankRdReqs::13 141125 # Track reads on a per bank basis
60 system.physmem.perBankRdReqs::14 138862 # Track reads on a per bank basis
61 system.physmem.perBankRdReqs::15 139997 # Track reads on a per bank basis
62 system.physmem.perBankWrReqs::0 69198 # Track writes on a per bank basis
63 system.physmem.perBankWrReqs::1 70413 # Track writes on a per bank basis
64 system.physmem.perBankWrReqs::2 69591 # Track writes on a per bank basis
65 system.physmem.perBankWrReqs::3 68873 # Track writes on a per bank basis
66 system.physmem.perBankWrReqs::4 67768 # Track writes on a per bank basis
67 system.physmem.perBankWrReqs::5 68429 # Track writes on a per bank basis
68 system.physmem.perBankWrReqs::6 68697 # Track writes on a per bank basis
69 system.physmem.perBankWrReqs::7 68477 # Track writes on a per bank basis
70 system.physmem.perBankWrReqs::8 68286 # Track writes on a per bank basis
71 system.physmem.perBankWrReqs::9 68308 # Track writes on a per bank basis
72 system.physmem.perBankWrReqs::10 68629 # Track writes on a per bank basis
73 system.physmem.perBankWrReqs::11 68528 # Track writes on a per bank basis
74 system.physmem.perBankWrReqs::12 67273 # Track writes on a per bank basis
75 system.physmem.perBankWrReqs::13 70384 # Track writes on a per bank basis
76 system.physmem.perBankWrReqs::14 69023 # Track writes on a per bank basis
77 system.physmem.perBankWrReqs::15 68935 # Track writes on a per bank basis
78 system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
79 system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
80 system.physmem.totGap 506353933500 # Total gap between requests
81 system.physmem.readPktSize::0 0 # Categorize read packet sizes
82 system.physmem.readPktSize::1 0 # Categorize read packet sizes
83 system.physmem.readPktSize::2 0 # Categorize read packet sizes
84 system.physmem.readPktSize::3 0 # Categorize read packet sizes
85 system.physmem.readPktSize::4 0 # Categorize read packet sizes
86 system.physmem.readPktSize::5 0 # Categorize read packet sizes
87 system.physmem.readPktSize::6 2247186 # Categorize read packet sizes
88 system.physmem.readPktSize::7 0 # Categorize read packet sizes
89 system.physmem.readPktSize::8 0 # Categorize read packet sizes
90 system.physmem.writePktSize::0 0 # categorize write packet sizes
91 system.physmem.writePktSize::1 0 # categorize write packet sizes
92 system.physmem.writePktSize::2 0 # categorize write packet sizes
93 system.physmem.writePktSize::3 0 # categorize write packet sizes
94 system.physmem.writePktSize::4 0 # categorize write packet sizes
95 system.physmem.writePktSize::5 0 # categorize write packet sizes
96 system.physmem.writePktSize::6 1100812 # categorize write packet sizes
97 system.physmem.writePktSize::7 0 # categorize write packet sizes
98 system.physmem.writePktSize::8 0 # categorize write packet sizes
99 system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
100 system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
101 system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
102 system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
103 system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
104 system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
105 system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
106 system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
107 system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
108 system.physmem.rdQLenPdf::0 1577555 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::1 446581 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::2 156376 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::3 65982 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
136 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
137 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
138 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
139 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
140 system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
141 system.physmem.wrQLenPdf::0 45520 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::1 47517 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::2 47811 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::3 47856 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::4 47861 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::5 47862 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::6 47862 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::7 47862 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::8 47862 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::9 47861 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::10 47861 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::11 47861 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::12 47861 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::13 47861 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::14 47861 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::15 47861 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::16 47861 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::17 47861 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::18 47861 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::19 47861 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::20 47861 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::21 47861 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::22 47861 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::23 2342 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::24 345 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::25 51 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
174 system.physmem.totQLat 27009597750 # Total cycles spent in queuing delays
175 system.physmem.totMemAccLat 102747541750 # Sum of mem lat for all requests
176 system.physmem.totBusLat 8986056000 # Total cycles spent in databus access
177 system.physmem.totBankLat 66751888000 # Total cycles spent in bank access
178 system.physmem.avgQLat 12022.89 # Average queueing delay per request
179 system.physmem.avgBankLat 29713.54 # Average bank access latency per request
180 system.physmem.avgBusLat 4000.00 # Average bus latency per request
181 system.physmem.avgMemAccLat 45736.44 # Average memory access latency
182 system.physmem.avgRdBW 284.03 # Average achieved read bandwidth in MB/s
183 system.physmem.avgWrBW 139.14 # Average achieved write bandwidth in MB/s
184 system.physmem.avgConsumedRdBW 284.03 # Average consumed read bandwidth in MB/s
185 system.physmem.avgConsumedWrBW 139.14 # Average consumed write bandwidth in MB/s
186 system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
187 system.physmem.busUtil 2.64 # Data bus utilization in percentage
188 system.physmem.avgRdQLen 0.20 # Average read queue length over time
189 system.physmem.avgWrQLen 11.52 # Average write queue length over time
190 system.physmem.readRowHits 914505 # Number of row buffer hits during reads
191 system.physmem.writeRowHits 189005 # Number of row buffer hits during writes
192 system.physmem.readRowHitRate 40.71 # Row buffer hit rate for reads
193 system.physmem.writeRowHitRate 17.17 # Row buffer hit rate for writes
194 system.physmem.avgGap 151240.81 # Average gap between requests
195 system.cpu.branchPred.lookups 301930111 # Number of BP lookups
196 system.cpu.branchPred.condPredicted 248173247 # Number of conditional branches predicted
197 system.cpu.branchPred.condIncorrect 15201095 # Number of conditional branches incorrect
198 system.cpu.branchPred.BTBLookups 171785530 # Number of BTB lookups
199 system.cpu.branchPred.BTBHits 160276899 # Number of BTB hits
200 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
201 system.cpu.branchPred.BTBHitPct 93.300582 # BTB Hit Percentage
202 system.cpu.branchPred.usedRAS 17551988 # Number of times the RAS was used to get a target.
203 system.cpu.branchPred.RASInCorrect 206 # Number of incorrect RAS predictions.
204 system.cpu.dtb.inst_hits 0 # ITB inst hits
205 system.cpu.dtb.inst_misses 0 # ITB inst misses
206 system.cpu.dtb.read_hits 0 # DTB read hits
207 system.cpu.dtb.read_misses 0 # DTB read misses
208 system.cpu.dtb.write_hits 0 # DTB write hits
209 system.cpu.dtb.write_misses 0 # DTB write misses
210 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
211 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
212 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
213 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
214 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
215 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
216 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
217 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
218 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
219 system.cpu.dtb.read_accesses 0 # DTB read accesses
220 system.cpu.dtb.write_accesses 0 # DTB write accesses
221 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
222 system.cpu.dtb.hits 0 # DTB hits
223 system.cpu.dtb.misses 0 # DTB misses
224 system.cpu.dtb.accesses 0 # DTB accesses
225 system.cpu.itb.inst_hits 0 # ITB inst hits
226 system.cpu.itb.inst_misses 0 # ITB inst misses
227 system.cpu.itb.read_hits 0 # DTB read hits
228 system.cpu.itb.read_misses 0 # DTB read misses
229 system.cpu.itb.write_hits 0 # DTB write hits
230 system.cpu.itb.write_misses 0 # DTB write misses
231 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
232 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
233 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
234 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
235 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
236 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
237 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
238 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
239 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
240 system.cpu.itb.read_accesses 0 # DTB read accesses
241 system.cpu.itb.write_accesses 0 # DTB write accesses
242 system.cpu.itb.inst_accesses 0 # ITB inst accesses
243 system.cpu.itb.hits 0 # DTB hits
244 system.cpu.itb.misses 0 # DTB misses
245 system.cpu.itb.accesses 0 # DTB accesses
246 system.cpu.workload.num_syscalls 46 # Number of system calls
247 system.cpu.numCycles 1012707994 # number of cpu cycles simulated
248 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
249 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
250 system.cpu.fetch.icacheStallCycles 296178013 # Number of cycles fetch is stalled on an Icache miss
251 system.cpu.fetch.Insts 2176838116 # Number of instructions fetch has processed
252 system.cpu.fetch.Branches 301930111 # Number of branches that fetch encountered
253 system.cpu.fetch.predictedBranches 177828887 # Number of branches that fetch has predicted taken
254 system.cpu.fetch.Cycles 433076308 # Number of cycles fetch has run and was not squashing or blocked
255 system.cpu.fetch.SquashCycles 86433742 # Number of cycles fetch has spent squashing
256 system.cpu.fetch.BlockedCycles 153009166 # Number of cycles fetch has spent blocked
257 system.cpu.fetch.PendingTrapStallCycles 127 # Number of stall cycles due to pending traps
258 system.cpu.fetch.CacheLines 286734480 # Number of cache lines fetched
259 system.cpu.fetch.IcacheSquashes 5522368 # Number of outstanding Icache misses that were squashed
260 system.cpu.fetch.rateDist::samples 951217236 # Number of instructions fetched each cycle (Total)
261 system.cpu.fetch.rateDist::mean 2.532975 # Number of instructions fetched each cycle (Total)
262 system.cpu.fetch.rateDist::stdev 3.216056 # Number of instructions fetched each cycle (Total)
263 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
264 system.cpu.fetch.rateDist::0 518141000 54.47% 54.47% # Number of instructions fetched each cycle (Total)
265 system.cpu.fetch.rateDist::1 25031243 2.63% 57.10% # Number of instructions fetched each cycle (Total)
266 system.cpu.fetch.rateDist::2 39020791 4.10% 61.21% # Number of instructions fetched each cycle (Total)
267 system.cpu.fetch.rateDist::3 48260411 5.07% 66.28% # Number of instructions fetched each cycle (Total)
268 system.cpu.fetch.rateDist::4 42551008 4.47% 70.75% # Number of instructions fetched each cycle (Total)
269 system.cpu.fetch.rateDist::5 46329866 4.87% 75.62% # Number of instructions fetched each cycle (Total)
270 system.cpu.fetch.rateDist::6 38408585 4.04% 79.66% # Number of instructions fetched each cycle (Total)
271 system.cpu.fetch.rateDist::7 18543654 1.95% 81.61% # Number of instructions fetched each cycle (Total)
272 system.cpu.fetch.rateDist::8 174930678 18.39% 100.00% # Number of instructions fetched each cycle (Total)
273 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
274 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
275 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
276 system.cpu.fetch.rateDist::total 951217236 # Number of instructions fetched each cycle (Total)
277 system.cpu.fetch.branchRate 0.298141 # Number of branch fetches per cycle
278 system.cpu.fetch.rate 2.149522 # Number of inst fetches per cycle
279 system.cpu.decode.IdleCycles 327471231 # Number of cycles decode is idle
280 system.cpu.decode.BlockedCycles 131306156 # Number of cycles decode is blocked
281 system.cpu.decode.RunCycles 403441377 # Number of cycles decode is running
282 system.cpu.decode.UnblockCycles 20045518 # Number of cycles decode is unblocking
283 system.cpu.decode.SquashCycles 68952954 # Number of cycles decode is squashing
284 system.cpu.decode.BranchResolved 46012127 # Number of times decode resolved a branch
285 system.cpu.decode.BranchMispred 693 # Number of times decode detected a branch misprediction
286 system.cpu.decode.DecodedInsts 2358019040 # Number of instructions handled by decode
287 system.cpu.decode.SquashedInsts 2460 # Number of squashed instructions handled by decode
288 system.cpu.rename.SquashCycles 68952954 # Number of cycles rename is squashing
289 system.cpu.rename.IdleCycles 350612417 # Number of cycles rename is idle
290 system.cpu.rename.BlockCycles 61250936 # Number of cycles rename is blocking
291 system.cpu.rename.serializeStallCycles 16584 # count of cycles rename stalled for serializing inst
292 system.cpu.rename.RunCycles 398830274 # Number of cycles rename is running
293 system.cpu.rename.UnblockCycles 71554071 # Number of cycles rename is unblocking
294 system.cpu.rename.RenamedInsts 2297211554 # Number of instructions processed by rename
295 system.cpu.rename.ROBFullEvents 127534 # Number of times rename has blocked due to ROB full
296 system.cpu.rename.IQFullEvents 5036199 # Number of times rename has blocked due to IQ full
297 system.cpu.rename.LSQFullEvents 58405264 # Number of times rename has blocked due to LSQ full
298 system.cpu.rename.FullRegisterEvents 16 # Number of times there has been no free registers
299 system.cpu.rename.RenamedOperands 2272168650 # Number of destination operands rename has renamed
300 system.cpu.rename.RenameLookups 10608574023 # Number of register rename lookups that rename has made
301 system.cpu.rename.int_rename_lookups 10608571065 # Number of integer rename lookups
302 system.cpu.rename.fp_rename_lookups 2958 # Number of floating rename lookups
303 system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed
304 system.cpu.rename.UndoneMaps 565848720 # Number of HB maps that are undone due to squashing
305 system.cpu.rename.serializingInsts 855 # count of serializing insts renamed
306 system.cpu.rename.tempSerializingInsts 852 # count of temporary serializing insts renamed
307 system.cpu.rename.skidInsts 158388501 # count of insts added to the skid buffer
308 system.cpu.memDep0.insertedLoads 623121269 # Number of loads inserted to the mem dependence unit.
309 system.cpu.memDep0.insertedStores 220470896 # Number of stores inserted to the mem dependence unit.
310 system.cpu.memDep0.conflictingLoads 86042540 # Number of conflicting loads.
311 system.cpu.memDep0.conflictingStores 70771050 # Number of conflicting stores.
312 system.cpu.iq.iqInstsAdded 2196546407 # Number of instructions added to the IQ (excludes non-spec)
313 system.cpu.iq.iqNonSpecInstsAdded 888 # Number of non-speculative instructions added to the IQ
314 system.cpu.iq.iqInstsIssued 2016009796 # Number of instructions issued
315 system.cpu.iq.iqSquashedInstsIssued 3969588 # Number of squashed instructions issued
316 system.cpu.iq.iqSquashedInstsExamined 468927262 # Number of squashed instructions iterated over during squash; mainly for profiling
317 system.cpu.iq.iqSquashedOperandsExamined 1107841980 # Number of squashed operands that are examined and possibly removed from graph
318 system.cpu.iq.iqSquashedNonSpecRemoved 718 # Number of squashed non-spec instructions that were removed
319 system.cpu.iq.issued_per_cycle::samples 951217236 # Number of insts issued each cycle
320 system.cpu.iq.issued_per_cycle::mean 2.119400 # Number of insts issued each cycle
321 system.cpu.iq.issued_per_cycle::stdev 1.906359 # Number of insts issued each cycle
322 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
323 system.cpu.iq.issued_per_cycle::0 271448438 28.54% 28.54% # Number of insts issued each cycle
324 system.cpu.iq.issued_per_cycle::1 150881497 15.86% 44.40% # Number of insts issued each cycle
325 system.cpu.iq.issued_per_cycle::2 160823100 16.91% 61.31% # Number of insts issued each cycle
326 system.cpu.iq.issued_per_cycle::3 119315575 12.54% 73.85% # Number of insts issued each cycle
327 system.cpu.iq.issued_per_cycle::4 124031902 13.04% 86.89% # Number of insts issued each cycle
328 system.cpu.iq.issued_per_cycle::5 73881034 7.77% 94.66% # Number of insts issued each cycle
329 system.cpu.iq.issued_per_cycle::6 38429694 4.04% 98.70% # Number of insts issued each cycle
330 system.cpu.iq.issued_per_cycle::7 9823536 1.03% 99.73% # Number of insts issued each cycle
331 system.cpu.iq.issued_per_cycle::8 2582460 0.27% 100.00% # Number of insts issued each cycle
332 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
333 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
334 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
335 system.cpu.iq.issued_per_cycle::total 951217236 # Number of insts issued each cycle
336 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
337 system.cpu.iq.fu_full::IntAlu 875964 3.67% 3.67% # attempts to use FU when none available
338 system.cpu.iq.fu_full::IntMult 5764 0.02% 3.70% # attempts to use FU when none available
339 system.cpu.iq.fu_full::IntDiv 0 0.00% 3.70% # attempts to use FU when none available
340 system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.70% # attempts to use FU when none available
341 system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.70% # attempts to use FU when none available
342 system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.70% # attempts to use FU when none available
343 system.cpu.iq.fu_full::FloatMult 0 0.00% 3.70% # attempts to use FU when none available
344 system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.70% # attempts to use FU when none available
345 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.70% # attempts to use FU when none available
346 system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.70% # attempts to use FU when none available
347 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.70% # attempts to use FU when none available
348 system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.70% # attempts to use FU when none available
349 system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.70% # attempts to use FU when none available
350 system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.70% # attempts to use FU when none available
351 system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.70% # attempts to use FU when none available
352 system.cpu.iq.fu_full::SimdMult 0 0.00% 3.70% # attempts to use FU when none available
353 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.70% # attempts to use FU when none available
354 system.cpu.iq.fu_full::SimdShift 0 0.00% 3.70% # attempts to use FU when none available
355 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.70% # attempts to use FU when none available
356 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.70% # attempts to use FU when none available
357 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.70% # attempts to use FU when none available
358 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.70% # attempts to use FU when none available
359 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.70% # attempts to use FU when none available
360 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.70% # attempts to use FU when none available
361 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.70% # attempts to use FU when none available
362 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.70% # attempts to use FU when none available
363 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.70% # attempts to use FU when none available
364 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.70% # attempts to use FU when none available
365 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.70% # attempts to use FU when none available
366 system.cpu.iq.fu_full::MemRead 18242361 76.45% 80.15% # attempts to use FU when none available
367 system.cpu.iq.fu_full::MemWrite 4736544 19.85% 100.00% # attempts to use FU when none available
368 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
369 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
370 system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
371 system.cpu.iq.FU_type_0::IntAlu 1235492979 61.28% 61.28% # Type of FU issued
372 system.cpu.iq.FU_type_0::IntMult 925544 0.05% 61.33% # Type of FU issued
373 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.33% # Type of FU issued
374 system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.33% # Type of FU issued
375 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.33% # Type of FU issued
376 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.33% # Type of FU issued
377 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.33% # Type of FU issued
378 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.33% # Type of FU issued
379 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.33% # Type of FU issued
380 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.33% # Type of FU issued
381 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.33% # Type of FU issued
382 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.33% # Type of FU issued
383 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.33% # Type of FU issued
384 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.33% # Type of FU issued
385 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.33% # Type of FU issued
386 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.33% # Type of FU issued
387 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.33% # Type of FU issued
388 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.33% # Type of FU issued
389 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.33% # Type of FU issued
390 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.33% # Type of FU issued
391 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.33% # Type of FU issued
392 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.33% # Type of FU issued
393 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.33% # Type of FU issued
394 system.cpu.iq.FU_type_0::SimdFloatCvt 40 0.00% 61.33% # Type of FU issued
395 system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.33% # Type of FU issued
396 system.cpu.iq.FU_type_0::SimdFloatMisc 21 0.00% 61.33% # Type of FU issued
397 system.cpu.iq.FU_type_0::SimdFloatMult 7 0.00% 61.33% # Type of FU issued
398 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.33% # Type of FU issued
399 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.33% # Type of FU issued
400 system.cpu.iq.FU_type_0::MemRead 586540633 29.09% 90.42% # Type of FU issued
401 system.cpu.iq.FU_type_0::MemWrite 193050569 9.58% 100.00% # Type of FU issued
402 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
403 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
404 system.cpu.iq.FU_type_0::total 2016009796 # Type of FU issued
405 system.cpu.iq.rate 1.990712 # Inst issue rate
406 system.cpu.iq.fu_busy_cnt 23860633 # FU busy when requested
407 system.cpu.iq.fu_busy_rate 0.011836 # FU busy rate (busy events/executed inst)
408 system.cpu.iq.int_inst_queue_reads 5011066759 # Number of integer instruction queue reads
409 system.cpu.iq.int_inst_queue_writes 2665664471 # Number of integer instruction queue writes
410 system.cpu.iq.int_inst_queue_wakeup_accesses 1956606463 # Number of integer instruction queue wakeup accesses
411 system.cpu.iq.fp_inst_queue_reads 290 # Number of floating instruction queue reads
412 system.cpu.iq.fp_inst_queue_writes 554 # Number of floating instruction queue writes
413 system.cpu.iq.fp_inst_queue_wakeup_accesses 113 # Number of floating instruction queue wakeup accesses
414 system.cpu.iq.int_alu_accesses 2039870285 # Number of integer alu accesses
415 system.cpu.iq.fp_alu_accesses 144 # Number of floating point alu accesses
416 system.cpu.iew.lsq.thread0.forwLoads 64705720 # Number of loads that had data forwarded from stores
417 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
418 system.cpu.iew.lsq.thread0.squashedLoads 137194500 # Number of loads squashed
419 system.cpu.iew.lsq.thread0.ignoredResponses 273797 # Number of memory responses ignored because the instruction is squashed
420 system.cpu.iew.lsq.thread0.memOrderViolation 192943 # Number of memory ordering violations
421 system.cpu.iew.lsq.thread0.squashedStores 45623851 # Number of stores squashed
422 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
423 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
424 system.cpu.iew.lsq.thread0.rescheduledLoads 3 # Number of loads that were rescheduled
425 system.cpu.iew.lsq.thread0.cacheBlocked 3807412 # Number of times an access to memory failed due to the cache being blocked
426 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
427 system.cpu.iew.iewSquashCycles 68952954 # Number of cycles IEW is squashing
428 system.cpu.iew.iewBlockCycles 27155997 # Number of cycles IEW is blocking
429 system.cpu.iew.iewUnblockCycles 1495704 # Number of cycles IEW is unblocking
430 system.cpu.iew.iewDispatchedInsts 2196547422 # Number of instructions dispatched to IQ
431 system.cpu.iew.iewDispSquashedInsts 6100181 # Number of squashed instructions skipped by dispatch
432 system.cpu.iew.iewDispLoadInsts 623121269 # Number of dispatched load instructions
433 system.cpu.iew.iewDispStoreInsts 220470896 # Number of dispatched store instructions
434 system.cpu.iew.iewDispNonSpecInsts 826 # Number of dispatched non-speculative instructions
435 system.cpu.iew.iewIQFullEvents 473871 # Number of times the IQ has become full, causing a stall
436 system.cpu.iew.iewLSQFullEvents 90052 # Number of times the LSQ has become full, causing a stall
437 system.cpu.iew.memOrderViolationEvents 192943 # Number of memory order violations
438 system.cpu.iew.predictedTakenIncorrect 8142096 # Number of branches that were predicted taken incorrectly
439 system.cpu.iew.predictedNotTakenIncorrect 9608050 # Number of branches that were predicted not taken incorrectly
440 system.cpu.iew.branchMispredicts 17750146 # Number of branch mispredicts detected at execute
441 system.cpu.iew.iewExecutedInsts 1986410888 # Number of executed instructions
442 system.cpu.iew.iewExecLoadInsts 573023734 # Number of load instructions executed
443 system.cpu.iew.iewExecSquashedInsts 29598908 # Number of squashed instructions skipped in execute
444 system.cpu.iew.exec_swp 0 # number of swp insts executed
445 system.cpu.iew.exec_nop 127 # number of nop insts executed
446 system.cpu.iew.exec_refs 763190345 # number of memory reference insts executed
447 system.cpu.iew.exec_branches 238305534 # Number of branches executed
448 system.cpu.iew.exec_stores 190166611 # Number of stores executed
449 system.cpu.iew.exec_rate 1.961484 # Inst execution rate
450 system.cpu.iew.wb_sent 1965043499 # cumulative count of insts sent to commit
451 system.cpu.iew.wb_count 1956606576 # cumulative count of insts written-back
452 system.cpu.iew.wb_producers 1295701772 # num instructions producing a value
453 system.cpu.iew.wb_consumers 2060221208 # num instructions consuming a value
454 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
455 system.cpu.iew.wb_rate 1.932054 # insts written-back per cycle
456 system.cpu.iew.wb_fanout 0.628914 # average fanout of values written-back
457 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
458 system.cpu.commit.commitSquashedInsts 473572340 # The number of squashed insts skipped by commit
459 system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards
460 system.cpu.commit.branchMispredicts 15200427 # The number of times a branch was mispredicted
461 system.cpu.commit.committed_per_cycle::samples 882264282 # Number of insts commited each cycle
462 system.cpu.commit.committed_per_cycle::mean 1.953013 # Number of insts commited each cycle
463 system.cpu.commit.committed_per_cycle::stdev 2.733344 # Number of insts commited each cycle
464 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
465 system.cpu.commit.committed_per_cycle::0 395036396 44.78% 44.78% # Number of insts commited each cycle
466 system.cpu.commit.committed_per_cycle::1 191994213 21.76% 66.54% # Number of insts commited each cycle
467 system.cpu.commit.committed_per_cycle::2 72477507 8.21% 74.75% # Number of insts commited each cycle
468 system.cpu.commit.committed_per_cycle::3 35260039 4.00% 78.75% # Number of insts commited each cycle
469 system.cpu.commit.committed_per_cycle::4 18947912 2.15% 80.90% # Number of insts commited each cycle
470 system.cpu.commit.committed_per_cycle::5 30765236 3.49% 84.38% # Number of insts commited each cycle
471 system.cpu.commit.committed_per_cycle::6 20067867 2.27% 86.66% # Number of insts commited each cycle
472 system.cpu.commit.committed_per_cycle::7 11401417 1.29% 87.95% # Number of insts commited each cycle
473 system.cpu.commit.committed_per_cycle::8 106313695 12.05% 100.00% # Number of insts commited each cycle
474 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
475 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
476 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
477 system.cpu.commit.committed_per_cycle::total 882264282 # Number of insts commited each cycle
478 system.cpu.commit.committedInsts 1544563041 # Number of instructions committed
479 system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed
480 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
481 system.cpu.commit.refs 660773814 # Number of memory references committed
482 system.cpu.commit.loads 485926769 # Number of loads committed
483 system.cpu.commit.membars 62 # Number of memory barriers committed
484 system.cpu.commit.branches 213462426 # Number of branches committed
485 system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
486 system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions.
487 system.cpu.commit.function_calls 13665177 # Number of function calls committed.
488 system.cpu.commit.bw_lim_events 106313695 # number cycles where commit BW limit reached
489 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
490 system.cpu.rob.rob_reads 2972596181 # The number of ROB reads
491 system.cpu.rob.rob_writes 4462393115 # The number of ROB writes
492 system.cpu.timesIdled 1008109 # Number of times that the entire CPU went into an idle state and unscheduled itself
493 system.cpu.idleCycles 61490758 # Total number of cycles that the CPU has spent unscheduled due to idling
494 system.cpu.committedInsts 1544563023 # Number of Instructions Simulated
495 system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated
496 system.cpu.committedInsts_total 1544563023 # Number of Instructions Simulated
497 system.cpu.cpi 0.655660 # CPI: Cycles Per Instruction
498 system.cpu.cpi_total 0.655660 # CPI: Total CPI of All Threads
499 system.cpu.ipc 1.525181 # IPC: Instructions Per Cycle
500 system.cpu.ipc_total 1.525181 # IPC: Total IPC of All Threads
501 system.cpu.int_regfile_reads 9949148949 # number of integer regfile reads
502 system.cpu.int_regfile_writes 1936492974 # number of integer regfile writes
503 system.cpu.fp_regfile_reads 113 # number of floating regfile reads
504 system.cpu.fp_regfile_writes 115 # number of floating regfile writes
505 system.cpu.misc_regfile_reads 737540247 # number of misc regfile reads
506 system.cpu.misc_regfile_writes 124 # number of misc regfile writes
507 system.cpu.icache.replacements 23 # number of replacements
508 system.cpu.icache.tagsinuse 625.185145 # Cycle average of tags in use
509 system.cpu.icache.total_refs 286733320 # Total number of references to valid blocks.
510 system.cpu.icache.sampled_refs 778 # Sample count of references to valid blocks.
511 system.cpu.icache.avg_refs 368551.825193 # Average number of references to valid blocks.
512 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
513 system.cpu.icache.occ_blocks::cpu.inst 625.185145 # Average occupied blocks per requestor
514 system.cpu.icache.occ_percent::cpu.inst 0.305266 # Average percentage of cache occupancy
515 system.cpu.icache.occ_percent::total 0.305266 # Average percentage of cache occupancy
516 system.cpu.icache.ReadReq_hits::cpu.inst 286733320 # number of ReadReq hits
517 system.cpu.icache.ReadReq_hits::total 286733320 # number of ReadReq hits
518 system.cpu.icache.demand_hits::cpu.inst 286733320 # number of demand (read+write) hits
519 system.cpu.icache.demand_hits::total 286733320 # number of demand (read+write) hits
520 system.cpu.icache.overall_hits::cpu.inst 286733320 # number of overall hits
521 system.cpu.icache.overall_hits::total 286733320 # number of overall hits
522 system.cpu.icache.ReadReq_misses::cpu.inst 1160 # number of ReadReq misses
523 system.cpu.icache.ReadReq_misses::total 1160 # number of ReadReq misses
524 system.cpu.icache.demand_misses::cpu.inst 1160 # number of demand (read+write) misses
525 system.cpu.icache.demand_misses::total 1160 # number of demand (read+write) misses
526 system.cpu.icache.overall_misses::cpu.inst 1160 # number of overall misses
527 system.cpu.icache.overall_misses::total 1160 # number of overall misses
528 system.cpu.icache.ReadReq_miss_latency::cpu.inst 59910000 # number of ReadReq miss cycles
529 system.cpu.icache.ReadReq_miss_latency::total 59910000 # number of ReadReq miss cycles
530 system.cpu.icache.demand_miss_latency::cpu.inst 59910000 # number of demand (read+write) miss cycles
531 system.cpu.icache.demand_miss_latency::total 59910000 # number of demand (read+write) miss cycles
532 system.cpu.icache.overall_miss_latency::cpu.inst 59910000 # number of overall miss cycles
533 system.cpu.icache.overall_miss_latency::total 59910000 # number of overall miss cycles
534 system.cpu.icache.ReadReq_accesses::cpu.inst 286734480 # number of ReadReq accesses(hits+misses)
535 system.cpu.icache.ReadReq_accesses::total 286734480 # number of ReadReq accesses(hits+misses)
536 system.cpu.icache.demand_accesses::cpu.inst 286734480 # number of demand (read+write) accesses
537 system.cpu.icache.demand_accesses::total 286734480 # number of demand (read+write) accesses
538 system.cpu.icache.overall_accesses::cpu.inst 286734480 # number of overall (read+write) accesses
539 system.cpu.icache.overall_accesses::total 286734480 # number of overall (read+write) accesses
540 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
541 system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
542 system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
543 system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
544 system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
545 system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
546 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51646.551724 # average ReadReq miss latency
547 system.cpu.icache.ReadReq_avg_miss_latency::total 51646.551724 # average ReadReq miss latency
548 system.cpu.icache.demand_avg_miss_latency::cpu.inst 51646.551724 # average overall miss latency
549 system.cpu.icache.demand_avg_miss_latency::total 51646.551724 # average overall miss latency
550 system.cpu.icache.overall_avg_miss_latency::cpu.inst 51646.551724 # average overall miss latency
551 system.cpu.icache.overall_avg_miss_latency::total 51646.551724 # average overall miss latency
552 system.cpu.icache.blocked_cycles::no_mshrs 207 # number of cycles access was blocked
553 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
554 system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked
555 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
556 system.cpu.icache.avg_blocked_cycles::no_mshrs 69 # average number of cycles each access was blocked
557 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
558 system.cpu.icache.fast_writes 0 # number of fast writes performed
559 system.cpu.icache.cache_copies 0 # number of cache copies performed
560 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 382 # number of ReadReq MSHR hits
561 system.cpu.icache.ReadReq_mshr_hits::total 382 # number of ReadReq MSHR hits
562 system.cpu.icache.demand_mshr_hits::cpu.inst 382 # number of demand (read+write) MSHR hits
563 system.cpu.icache.demand_mshr_hits::total 382 # number of demand (read+write) MSHR hits
564 system.cpu.icache.overall_mshr_hits::cpu.inst 382 # number of overall MSHR hits
565 system.cpu.icache.overall_mshr_hits::total 382 # number of overall MSHR hits
566 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 778 # number of ReadReq MSHR misses
567 system.cpu.icache.ReadReq_mshr_misses::total 778 # number of ReadReq MSHR misses
568 system.cpu.icache.demand_mshr_misses::cpu.inst 778 # number of demand (read+write) MSHR misses
569 system.cpu.icache.demand_mshr_misses::total 778 # number of demand (read+write) MSHR misses
570 system.cpu.icache.overall_mshr_misses::cpu.inst 778 # number of overall MSHR misses
571 system.cpu.icache.overall_mshr_misses::total 778 # number of overall MSHR misses
572 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43554500 # number of ReadReq MSHR miss cycles
573 system.cpu.icache.ReadReq_mshr_miss_latency::total 43554500 # number of ReadReq MSHR miss cycles
574 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43554500 # number of demand (read+write) MSHR miss cycles
575 system.cpu.icache.demand_mshr_miss_latency::total 43554500 # number of demand (read+write) MSHR miss cycles
576 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43554500 # number of overall MSHR miss cycles
577 system.cpu.icache.overall_mshr_miss_latency::total 43554500 # number of overall MSHR miss cycles
578 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
579 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses
580 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
581 system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses
582 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
583 system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses
584 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55982.647815 # average ReadReq mshr miss latency
585 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55982.647815 # average ReadReq mshr miss latency
586 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55982.647815 # average overall mshr miss latency
587 system.cpu.icache.demand_avg_mshr_miss_latency::total 55982.647815 # average overall mshr miss latency
588 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55982.647815 # average overall mshr miss latency
589 system.cpu.icache.overall_avg_mshr_miss_latency::total 55982.647815 # average overall mshr miss latency
590 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
591 system.cpu.l2cache.replacements 2214498 # number of replacements
592 system.cpu.l2cache.tagsinuse 31523.726273 # Cycle average of tags in use
593 system.cpu.l2cache.total_refs 9246379 # Total number of references to valid blocks.
594 system.cpu.l2cache.sampled_refs 2244276 # Sample count of references to valid blocks.
595 system.cpu.l2cache.avg_refs 4.119983 # Average number of references to valid blocks.
596 system.cpu.l2cache.warmup_cycle 20414306502 # Cycle when the warmup percentage was hit.
597 system.cpu.l2cache.occ_blocks::writebacks 14432.975360 # Average occupied blocks per requestor
598 system.cpu.l2cache.occ_blocks::cpu.inst 20.502484 # Average occupied blocks per requestor
599 system.cpu.l2cache.occ_blocks::cpu.data 17070.248430 # Average occupied blocks per requestor
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602 system.cpu.l2cache.occ_percent::cpu.data 0.520943 # Average percentage of cache occupancy
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606 system.cpu.l2cache.ReadReq_hits::total 6289336 # number of ReadReq hits
607 system.cpu.l2cache.Writeback_hits::writebacks 3781550 # number of Writeback hits
608 system.cpu.l2cache.Writeback_hits::total 3781550 # number of Writeback hits
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610 system.cpu.l2cache.ReadExReq_hits::total 1066723 # number of ReadExReq hits
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614 system.cpu.l2cache.overall_hits::cpu.inst 26 # number of overall hits
615 system.cpu.l2cache.overall_hits::cpu.data 7356033 # number of overall hits
616 system.cpu.l2cache.overall_hits::total 7356059 # number of overall hits
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621 system.cpu.l2cache.ReadExReq_misses::total 826690 # number of ReadExReq misses
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626 system.cpu.l2cache.overall_misses::cpu.data 2246443 # number of overall misses
627 system.cpu.l2cache.overall_misses::total 2247195 # number of overall misses
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637 system.cpu.l2cache.overall_miss_latency::cpu.data 156865997500 # number of overall miss cycles
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642 system.cpu.l2cache.Writeback_accesses::writebacks 3781550 # number of Writeback accesses(hits+misses)
643 system.cpu.l2cache.Writeback_accesses::total 3781550 # number of Writeback accesses(hits+misses)
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645 system.cpu.l2cache.ReadExReq_accesses::total 1893413 # number of ReadExReq accesses(hits+misses)
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651 system.cpu.l2cache.overall_accesses::total 9603254 # number of overall (read+write) accesses
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653 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184167 # miss rate for ReadReq accesses
654 system.cpu.l2cache.ReadReq_miss_rate::total 0.184246 # miss rate for ReadReq accesses
655 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436614 # miss rate for ReadExReq accesses
656 system.cpu.l2cache.ReadExReq_miss_rate::total 0.436614 # miss rate for ReadExReq accesses
657 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.966581 # miss rate for demand accesses
658 system.cpu.l2cache.demand_miss_rate::cpu.data 0.233944 # miss rate for demand accesses
659 system.cpu.l2cache.demand_miss_rate::total 0.234003 # miss rate for demand accesses
660 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.966581 # miss rate for overall accesses
661 system.cpu.l2cache.overall_miss_rate::cpu.data 0.233944 # miss rate for overall accesses
662 system.cpu.l2cache.overall_miss_rate::total 0.234003 # miss rate for overall accesses
663 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56521.941489 # average ReadReq miss latency
664 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69113.012968 # average ReadReq miss latency
665 system.cpu.l2cache.ReadReq_avg_miss_latency::total 69106.347391 # average ReadReq miss latency
666 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71057.579020 # average ReadExReq miss latency
667 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71057.579020 # average ReadExReq miss latency
668 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56521.941489 # average overall miss latency
669 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69828.612389 # average overall miss latency
670 system.cpu.l2cache.demand_avg_miss_latency::total 69824.159452 # average overall miss latency
671 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56521.941489 # average overall miss latency
672 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69828.612389 # average overall miss latency
673 system.cpu.l2cache.overall_avg_miss_latency::total 69824.159452 # average overall miss latency
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675 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
676 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
677 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
678 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
679 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
680 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
681 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
682 system.cpu.l2cache.writebacks::writebacks 1100812 # number of writebacks
683 system.cpu.l2cache.writebacks::total 1100812 # number of writebacks
684 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
685 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits
686 system.cpu.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits
687 system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
688 system.cpu.l2cache.demand_mshr_hits::cpu.data 7 # number of demand (read+write) MSHR hits
689 system.cpu.l2cache.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits
690 system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
691 system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits
692 system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits
693 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 750 # number of ReadReq MSHR misses
694 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1419746 # number of ReadReq MSHR misses
695 system.cpu.l2cache.ReadReq_mshr_misses::total 1420496 # number of ReadReq MSHR misses
696 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 826690 # number of ReadExReq MSHR misses
697 system.cpu.l2cache.ReadExReq_mshr_misses::total 826690 # number of ReadExReq MSHR misses
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702 system.cpu.l2cache.overall_mshr_misses::cpu.data 2246436 # number of overall MSHR misses
703 system.cpu.l2cache.overall_mshr_misses::total 2247186 # number of overall MSHR misses
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705 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 80176207714 # number of ReadReq MSHR miss cycles
706 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 80209126898 # number of ReadReq MSHR miss cycles
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708 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48315790009 # number of ReadExReq MSHR miss cycles
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713 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 128491997723 # number of overall MSHR miss cycles
714 system.cpu.l2cache.overall_mshr_miss_latency::total 128524916907 # number of overall MSHR miss cycles
715 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964010 # mshr miss rate for ReadReq accesses
716 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184166 # mshr miss rate for ReadReq accesses
717 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184245 # mshr miss rate for ReadReq accesses
718 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436614 # mshr miss rate for ReadExReq accesses
719 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436614 # mshr miss rate for ReadExReq accesses
720 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964010 # mshr miss rate for demand accesses
721 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233943 # mshr miss rate for demand accesses
722 system.cpu.l2cache.demand_mshr_miss_rate::total 0.234003 # mshr miss rate for demand accesses
723 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964010 # mshr miss rate for overall accesses
724 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233943 # mshr miss rate for overall accesses
725 system.cpu.l2cache.overall_mshr_miss_rate::total 0.234003 # mshr miss rate for overall accesses
726 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43892.245333 # average ReadReq mshr miss latency
727 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56472.219477 # average ReadReq mshr miss latency
728 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56465.577445 # average ReadReq mshr miss latency
729 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58444.870519 # average ReadExReq mshr miss latency
730 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58444.870519 # average ReadExReq mshr miss latency
731 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43892.245333 # average overall mshr miss latency
732 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57198.156423 # average overall mshr miss latency
733 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57193.715566 # average overall mshr miss latency
734 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43892.245333 # average overall mshr miss latency
735 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57198.156423 # average overall mshr miss latency
736 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57193.715566 # average overall mshr miss latency
737 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
738 system.cpu.dcache.replacements 9598379 # number of replacements
739 system.cpu.dcache.tagsinuse 4087.934747 # Cycle average of tags in use
740 system.cpu.dcache.total_refs 656008169 # Total number of references to valid blocks.
741 system.cpu.dcache.sampled_refs 9602475 # Sample count of references to valid blocks.
742 system.cpu.dcache.avg_refs 68.316571 # Average number of references to valid blocks.
743 system.cpu.dcache.warmup_cycle 3424422000 # Cycle when the warmup percentage was hit.
744 system.cpu.dcache.occ_blocks::cpu.data 4087.934747 # Average occupied blocks per requestor
745 system.cpu.dcache.occ_percent::cpu.data 0.998031 # Average percentage of cache occupancy
746 system.cpu.dcache.occ_percent::total 0.998031 # Average percentage of cache occupancy
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748 system.cpu.dcache.ReadReq_hits::total 488954223 # number of ReadReq hits
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750 system.cpu.dcache.WriteReq_hits::total 167053823 # number of WriteReq hits
751 system.cpu.dcache.LoadLockedReq_hits::cpu.data 62 # number of LoadLockedReq hits
752 system.cpu.dcache.LoadLockedReq_hits::total 62 # number of LoadLockedReq hits
753 system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
754 system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
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758 system.cpu.dcache.overall_hits::total 656008046 # number of overall hits
759 system.cpu.dcache.ReadReq_misses::cpu.data 11476242 # number of ReadReq misses
760 system.cpu.dcache.ReadReq_misses::total 11476242 # number of ReadReq misses
761 system.cpu.dcache.WriteReq_misses::cpu.data 5532224 # number of WriteReq misses
762 system.cpu.dcache.WriteReq_misses::total 5532224 # number of WriteReq misses
763 system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
764 system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
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766 system.cpu.dcache.demand_misses::total 17008466 # number of demand (read+write) misses
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768 system.cpu.dcache.overall_misses::total 17008466 # number of overall misses
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770 system.cpu.dcache.ReadReq_miss_latency::total 299283762000 # number of ReadReq miss cycles
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772 system.cpu.dcache.WriteReq_miss_latency::total 216949721927 # number of WriteReq miss cycles
773 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 217500 # number of LoadLockedReq miss cycles
774 system.cpu.dcache.LoadLockedReq_miss_latency::total 217500 # number of LoadLockedReq miss cycles
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782 system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
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784 system.cpu.dcache.LoadLockedReq_accesses::total 65 # number of LoadLockedReq accesses(hits+misses)
785 system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
786 system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
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790 system.cpu.dcache.overall_accesses::total 673016512 # number of overall (read+write) accesses
791 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022933 # miss rate for ReadReq accesses
792 system.cpu.dcache.ReadReq_miss_rate::total 0.022933 # miss rate for ReadReq accesses
793 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032055 # miss rate for WriteReq accesses
794 system.cpu.dcache.WriteReq_miss_rate::total 0.032055 # miss rate for WriteReq accesses
795 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046154 # miss rate for LoadLockedReq accesses
796 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046154 # miss rate for LoadLockedReq accesses
797 system.cpu.dcache.demand_miss_rate::cpu.data 0.025272 # miss rate for demand accesses
798 system.cpu.dcache.demand_miss_rate::total 0.025272 # miss rate for demand accesses
799 system.cpu.dcache.overall_miss_rate::cpu.data 0.025272 # miss rate for overall accesses
800 system.cpu.dcache.overall_miss_rate::total 0.025272 # miss rate for overall accesses
801 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26078.550975 # average ReadReq miss latency
802 system.cpu.dcache.ReadReq_avg_miss_latency::total 26078.550975 # average ReadReq miss latency
803 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39215.643099 # average WriteReq miss latency
804 system.cpu.dcache.WriteReq_avg_miss_latency::total 39215.643099 # average WriteReq miss latency
805 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72500 # average LoadLockedReq miss latency
806 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72500 # average LoadLockedReq miss latency
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808 system.cpu.dcache.demand_avg_miss_latency::total 30351.560448 # average overall miss latency
809 system.cpu.dcache.overall_avg_miss_latency::cpu.data 30351.560448 # average overall miss latency
810 system.cpu.dcache.overall_avg_miss_latency::total 30351.560448 # average overall miss latency
811 system.cpu.dcache.blocked_cycles::no_mshrs 19781174 # number of cycles access was blocked
812 system.cpu.dcache.blocked_cycles::no_targets 987477 # number of cycles access was blocked
813 system.cpu.dcache.blocked::no_mshrs 1172505 # number of cycles access was blocked
814 system.cpu.dcache.blocked::no_targets 64541 # number of cycles access was blocked
815 system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.870865 # average number of cycles each access was blocked
816 system.cpu.dcache.avg_blocked_cycles::no_targets 15.299995 # average number of cycles each access was blocked
817 system.cpu.dcache.fast_writes 0 # number of fast writes performed
818 system.cpu.dcache.cache_copies 0 # number of cache copies performed
819 system.cpu.dcache.writebacks::writebacks 3781550 # number of writebacks
820 system.cpu.dcache.writebacks::total 3781550 # number of writebacks
821 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3767179 # number of ReadReq MSHR hits
822 system.cpu.dcache.ReadReq_mshr_hits::total 3767179 # number of ReadReq MSHR hits
823 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3638811 # number of WriteReq MSHR hits
824 system.cpu.dcache.WriteReq_mshr_hits::total 3638811 # number of WriteReq MSHR hits
825 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
826 system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
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828 system.cpu.dcache.demand_mshr_hits::total 7405990 # number of demand (read+write) MSHR hits
829 system.cpu.dcache.overall_mshr_hits::cpu.data 7405990 # number of overall MSHR hits
830 system.cpu.dcache.overall_mshr_hits::total 7405990 # number of overall MSHR hits
831 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7709063 # number of ReadReq MSHR misses
832 system.cpu.dcache.ReadReq_mshr_misses::total 7709063 # number of ReadReq MSHR misses
833 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893413 # number of WriteReq MSHR misses
834 system.cpu.dcache.WriteReq_mshr_misses::total 1893413 # number of WriteReq MSHR misses
835 system.cpu.dcache.demand_mshr_misses::cpu.data 9602476 # number of demand (read+write) MSHR misses
836 system.cpu.dcache.demand_mshr_misses::total 9602476 # number of demand (read+write) MSHR misses
837 system.cpu.dcache.overall_mshr_misses::cpu.data 9602476 # number of overall MSHR misses
838 system.cpu.dcache.overall_mshr_misses::total 9602476 # number of overall MSHR misses
839 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 170550521000 # number of ReadReq MSHR miss cycles
840 system.cpu.dcache.ReadReq_mshr_miss_latency::total 170550521000 # number of ReadReq MSHR miss cycles
841 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71842126604 # number of WriteReq MSHR miss cycles
842 system.cpu.dcache.WriteReq_mshr_miss_latency::total 71842126604 # number of WriteReq MSHR miss cycles
843 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 242392647604 # number of demand (read+write) MSHR miss cycles
844 system.cpu.dcache.demand_mshr_miss_latency::total 242392647604 # number of demand (read+write) MSHR miss cycles
845 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 242392647604 # number of overall MSHR miss cycles
846 system.cpu.dcache.overall_mshr_miss_latency::total 242392647604 # number of overall MSHR miss cycles
847 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015405 # mshr miss rate for ReadReq accesses
848 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015405 # mshr miss rate for ReadReq accesses
849 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses
850 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses
851 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014268 # mshr miss rate for demand accesses
852 system.cpu.dcache.demand_mshr_miss_rate::total 0.014268 # mshr miss rate for demand accesses
853 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014268 # mshr miss rate for overall accesses
854 system.cpu.dcache.overall_mshr_miss_rate::total 0.014268 # mshr miss rate for overall accesses
855 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22123.378808 # average ReadReq mshr miss latency
856 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22123.378808 # average ReadReq mshr miss latency
857 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37943.188625 # average WriteReq mshr miss latency
858 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37943.188625 # average WriteReq mshr miss latency
859 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25242.723606 # average overall mshr miss latency
860 system.cpu.dcache.demand_avg_mshr_miss_latency::total 25242.723606 # average overall mshr miss latency
861 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25242.723606 # average overall mshr miss latency
862 system.cpu.dcache.overall_avg_mshr_miss_latency::total 25242.723606 # average overall mshr miss latency
863 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
865 ---------- End Simulation Statistics ----------
projects / gem5.git / blob