2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.463994 # Number of seconds simulated
4 sim_ticks 463993693500 # Number of ticks simulated
5 final_tick 463993693500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 128371 # Simulator instruction rate (inst/s)
8 host_op_rate 143208 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 38563333 # Simulator tick rate (ticks/s)
10 host_mem_usage 232076 # Number of bytes of host memory used
11 host_seconds 12031.99 # Real time elapsed on the host
12 sim_insts 1544563066 # Number of instructions simulated
13 sim_ops 1723073879 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 49344 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 189746304 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 189795648 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 49344 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 49344 # Number of instructions bytes read from this memory
19 system.physmem.bytes_written::writebacks 78222144 # Number of bytes written to this memory
20 system.physmem.bytes_written::total 78222144 # Number of bytes written to this memory
21 system.physmem.num_reads::cpu.inst 771 # Number of read requests responded to by this memory
22 system.physmem.num_reads::cpu.data 2964786 # Number of read requests responded to by this memory
23 system.physmem.num_reads::total 2965557 # Number of read requests responded to by this memory
24 system.physmem.num_writes::writebacks 1222221 # Number of write requests responded to by this memory
25 system.physmem.num_writes::total 1222221 # Number of write requests responded to by this memory
26 system.physmem.bw_read::cpu.inst 106346 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_read::cpu.data 408941558 # Total read bandwidth from this memory (bytes/s)
28 system.physmem.bw_read::total 409047904 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_inst_read::cpu.inst 106346 # Instruction read bandwidth from this memory (bytes/s)
30 system.physmem.bw_inst_read::total 106346 # Instruction read bandwidth from this memory (bytes/s)
31 system.physmem.bw_write::writebacks 168584498 # Write bandwidth from this memory (bytes/s)
32 system.physmem.bw_write::total 168584498 # Write bandwidth from this memory (bytes/s)
33 system.physmem.bw_total::writebacks 168584498 # Total bandwidth to/from this memory (bytes/s)
34 system.physmem.bw_total::cpu.inst 106346 # Total bandwidth to/from this memory (bytes/s)
35 system.physmem.bw_total::cpu.data 408941558 # Total bandwidth to/from this memory (bytes/s)
36 system.physmem.bw_total::total 577632403 # Total bandwidth to/from this memory (bytes/s)
37 system.cpu.dtb.inst_hits 0 # ITB inst hits
38 system.cpu.dtb.inst_misses 0 # ITB inst misses
39 system.cpu.dtb.read_hits 0 # DTB read hits
40 system.cpu.dtb.read_misses 0 # DTB read misses
41 system.cpu.dtb.write_hits 0 # DTB write hits
42 system.cpu.dtb.write_misses 0 # DTB write misses
43 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
44 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
45 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
46 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
47 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
48 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
49 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
50 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
51 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
52 system.cpu.dtb.read_accesses 0 # DTB read accesses
53 system.cpu.dtb.write_accesses 0 # DTB write accesses
54 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
55 system.cpu.dtb.hits 0 # DTB hits
56 system.cpu.dtb.misses 0 # DTB misses
57 system.cpu.dtb.accesses 0 # DTB accesses
58 system.cpu.itb.inst_hits 0 # ITB inst hits
59 system.cpu.itb.inst_misses 0 # ITB inst misses
60 system.cpu.itb.read_hits 0 # DTB read hits
61 system.cpu.itb.read_misses 0 # DTB read misses
62 system.cpu.itb.write_hits 0 # DTB write hits
63 system.cpu.itb.write_misses 0 # DTB write misses
64 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
65 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
66 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
67 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
68 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
69 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
70 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
71 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
72 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
73 system.cpu.itb.read_accesses 0 # DTB read accesses
74 system.cpu.itb.write_accesses 0 # DTB write accesses
75 system.cpu.itb.inst_accesses 0 # ITB inst accesses
76 system.cpu.itb.hits 0 # DTB hits
77 system.cpu.itb.misses 0 # DTB misses
78 system.cpu.itb.accesses 0 # DTB accesses
79 system.cpu.workload.num_syscalls 46 # Number of system calls
80 system.cpu.numCycles 927987388 # number of cpu cycles simulated
81 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
82 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
83 system.cpu.BPredUnit.lookups 300553850 # Number of BP lookups
84 system.cpu.BPredUnit.condPredicted 246366147 # Number of conditional branches predicted
85 system.cpu.BPredUnit.condIncorrect 16098585 # Number of conditional branches incorrect
86 system.cpu.BPredUnit.BTBLookups 170916236 # Number of BTB lookups
87 system.cpu.BPredUnit.BTBHits 156311774 # Number of BTB hits
88 system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
89 system.cpu.BPredUnit.usedRAS 18335288 # Number of times the RAS was used to get a target.
90 system.cpu.BPredUnit.RASInCorrect 425 # Number of incorrect RAS predictions.
91 system.cpu.fetch.icacheStallCycles 292740519 # Number of cycles fetch is stalled on an Icache miss
92 system.cpu.fetch.Insts 2158326699 # Number of instructions fetch has processed
93 system.cpu.fetch.Branches 300553850 # Number of branches that fetch encountered
94 system.cpu.fetch.predictedBranches 174647062 # Number of branches that fetch has predicted taken
95 system.cpu.fetch.Cycles 429206926 # Number of cycles fetch has run and was not squashing or blocked
96 system.cpu.fetch.SquashCycles 83759589 # Number of cycles fetch has spent squashing
97 system.cpu.fetch.BlockedCycles 129259054 # Number of cycles fetch has spent blocked
98 system.cpu.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
99 system.cpu.fetch.PendingTrapStallCycles 200 # Number of stall cycles due to pending traps
100 system.cpu.fetch.CacheLines 283730265 # Number of cache lines fetched
101 system.cpu.fetch.IcacheSquashes 5372560 # Number of outstanding Icache misses that were squashed
102 system.cpu.fetch.rateDist::samples 918446800 # Number of instructions fetched each cycle (Total)
103 system.cpu.fetch.rateDist::mean 2.613763 # Number of instructions fetched each cycle (Total)
104 system.cpu.fetch.rateDist::stdev 3.238744 # Number of instructions fetched each cycle (Total)
105 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
106 system.cpu.fetch.rateDist::0 489239924 53.27% 53.27% # Number of instructions fetched each cycle (Total)
107 system.cpu.fetch.rateDist::1 23020148 2.51% 55.77% # Number of instructions fetched each cycle (Total)
108 system.cpu.fetch.rateDist::2 38764254 4.22% 60.00% # Number of instructions fetched each cycle (Total)
109 system.cpu.fetch.rateDist::3 47809734 5.21% 65.20% # Number of instructions fetched each cycle (Total)
110 system.cpu.fetch.rateDist::4 40766066 4.44% 69.64% # Number of instructions fetched each cycle (Total)
111 system.cpu.fetch.rateDist::5 46976906 5.11% 74.75% # Number of instructions fetched each cycle (Total)
112 system.cpu.fetch.rateDist::6 39072572 4.25% 79.01% # Number of instructions fetched each cycle (Total)
113 system.cpu.fetch.rateDist::7 18137057 1.97% 80.98% # Number of instructions fetched each cycle (Total)
114 system.cpu.fetch.rateDist::8 174660139 19.02% 100.00% # Number of instructions fetched each cycle (Total)
115 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
116 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
117 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
118 system.cpu.fetch.rateDist::total 918446800 # Number of instructions fetched each cycle (Total)
119 system.cpu.fetch.branchRate 0.323877 # Number of branch fetches per cycle
120 system.cpu.fetch.rate 2.325815 # Number of inst fetches per cycle
121 system.cpu.decode.IdleCycles 322039794 # Number of cycles decode is idle
122 system.cpu.decode.BlockedCycles 109288431 # Number of cycles decode is blocked
123 system.cpu.decode.RunCycles 403236235 # Number of cycles decode is running
124 system.cpu.decode.UnblockCycles 16643003 # Number of cycles decode is unblocking
125 system.cpu.decode.SquashCycles 67239337 # Number of cycles decode is squashing
126 system.cpu.decode.BranchResolved 46165390 # Number of times decode resolved a branch
127 system.cpu.decode.BranchMispred 810 # Number of times decode detected a branch misprediction
128 system.cpu.decode.DecodedInsts 2346870217 # Number of instructions handled by decode
129 system.cpu.decode.SquashedInsts 2646 # Number of squashed instructions handled by decode
130 system.cpu.rename.SquashCycles 67239337 # Number of cycles rename is squashing
131 system.cpu.rename.IdleCycles 343676895 # Number of cycles rename is idle
132 system.cpu.rename.BlockCycles 50827249 # Number of cycles rename is blocking
133 system.cpu.rename.serializeStallCycles 9551 # count of cycles rename stalled for serializing inst
134 system.cpu.rename.RunCycles 397069716 # Number of cycles rename is running
135 system.cpu.rename.UnblockCycles 59624052 # Number of cycles rename is unblocking
136 system.cpu.rename.RenamedInsts 2289998307 # Number of instructions processed by rename
137 system.cpu.rename.ROBFullEvents 23088 # Number of times rename has blocked due to ROB full
138 system.cpu.rename.IQFullEvents 4666333 # Number of times rename has blocked due to IQ full
139 system.cpu.rename.LSQFullEvents 46320806 # Number of times rename has blocked due to LSQ full
140 system.cpu.rename.FullRegisterEvents 5 # Number of times there has been no free registers
141 system.cpu.rename.RenamedOperands 2264655243 # Number of destination operands rename has renamed
142 system.cpu.rename.RenameLookups 10570139009 # Number of register rename lookups that rename has made
143 system.cpu.rename.int_rename_lookups 10570134861 # Number of integer rename lookups
144 system.cpu.rename.fp_rename_lookups 4148 # Number of floating rename lookups
145 system.cpu.rename.CommittedMaps 1706319999 # Number of HB maps that are committed
146 system.cpu.rename.UndoneMaps 558335244 # Number of HB maps that are undone due to squashing
147 system.cpu.rename.serializingInsts 4462 # count of serializing insts renamed
148 system.cpu.rename.tempSerializingInsts 4454 # count of temporary serializing insts renamed
149 system.cpu.rename.skidInsts 136929133 # count of insts added to the skid buffer
150 system.cpu.memDep0.insertedLoads 624839821 # Number of loads inserted to the mem dependence unit.
151 system.cpu.memDep0.insertedStores 218742392 # Number of stores inserted to the mem dependence unit.
152 system.cpu.memDep0.conflictingLoads 85961960 # Number of conflicting loads.
153 system.cpu.memDep0.conflictingStores 66558298 # Number of conflicting stores.
154 system.cpu.iq.iqInstsAdded 2190567677 # Number of instructions added to the IQ (excludes non-spec)
155 system.cpu.iq.iqNonSpecInstsAdded 692 # Number of non-speculative instructions added to the IQ
156 system.cpu.iq.iqInstsIssued 2016055896 # Number of instructions issued
157 system.cpu.iq.iqSquashedInstsIssued 4892741 # Number of squashed instructions issued
158 system.cpu.iq.iqSquashedInstsExamined 462785080 # Number of squashed instructions iterated over during squash; mainly for profiling
159 system.cpu.iq.iqSquashedOperandsExamined 1074735939 # Number of squashed operands that are examined and possibly removed from graph
160 system.cpu.iq.iqSquashedNonSpecRemoved 515 # Number of squashed non-spec instructions that were removed
161 system.cpu.iq.issued_per_cycle::samples 918446800 # Number of insts issued each cycle
162 system.cpu.iq.issued_per_cycle::mean 2.195071 # Number of insts issued each cycle
163 system.cpu.iq.issued_per_cycle::stdev 1.923309 # Number of insts issued each cycle
164 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
165 system.cpu.iq.issued_per_cycle::0 251194344 27.35% 27.35% # Number of insts issued each cycle
166 system.cpu.iq.issued_per_cycle::1 138877340 15.12% 42.47% # Number of insts issued each cycle
167 system.cpu.iq.issued_per_cycle::2 158309179 17.24% 59.71% # Number of insts issued each cycle
168 system.cpu.iq.issued_per_cycle::3 116273452 12.66% 72.37% # Number of insts issued each cycle
169 system.cpu.iq.issued_per_cycle::4 125754756 13.69% 86.06% # Number of insts issued each cycle
170 system.cpu.iq.issued_per_cycle::5 75525220 8.22% 94.28% # Number of insts issued each cycle
171 system.cpu.iq.issued_per_cycle::6 39163504 4.26% 98.55% # Number of insts issued each cycle
172 system.cpu.iq.issued_per_cycle::7 10678346 1.16% 99.71% # Number of insts issued each cycle
173 system.cpu.iq.issued_per_cycle::8 2670659 0.29% 100.00% # Number of insts issued each cycle
174 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
175 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
176 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
177 system.cpu.iq.issued_per_cycle::total 918446800 # Number of insts issued each cycle
178 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
179 system.cpu.iq.fu_full::IntAlu 824240 3.28% 3.28% # attempts to use FU when none available
180 system.cpu.iq.fu_full::IntMult 4827 0.02% 3.30% # attempts to use FU when none available
181 system.cpu.iq.fu_full::IntDiv 0 0.00% 3.30% # attempts to use FU when none available
182 system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.30% # attempts to use FU when none available
183 system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.30% # attempts to use FU when none available
184 system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.30% # attempts to use FU when none available
185 system.cpu.iq.fu_full::FloatMult 0 0.00% 3.30% # attempts to use FU when none available
186 system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.30% # attempts to use FU when none available
187 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.30% # attempts to use FU when none available
188 system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.30% # attempts to use FU when none available
189 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.30% # attempts to use FU when none available
190 system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.30% # attempts to use FU when none available
191 system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.30% # attempts to use FU when none available
192 system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.30% # attempts to use FU when none available
193 system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.30% # attempts to use FU when none available
194 system.cpu.iq.fu_full::SimdMult 0 0.00% 3.30% # attempts to use FU when none available
195 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.30% # attempts to use FU when none available
196 system.cpu.iq.fu_full::SimdShift 0 0.00% 3.30% # attempts to use FU when none available
197 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.30% # attempts to use FU when none available
198 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.30% # attempts to use FU when none available
199 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.30% # attempts to use FU when none available
200 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.30% # attempts to use FU when none available
201 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.30% # attempts to use FU when none available
202 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.30% # attempts to use FU when none available
203 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.30% # attempts to use FU when none available
204 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.30% # attempts to use FU when none available
205 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.30% # attempts to use FU when none available
206 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.30% # attempts to use FU when none available
207 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.30% # attempts to use FU when none available
208 system.cpu.iq.fu_full::MemRead 19025079 75.82% 79.12% # attempts to use FU when none available
209 system.cpu.iq.fu_full::MemWrite 5238831 20.88% 100.00% # attempts to use FU when none available
210 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
211 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
212 system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
213 system.cpu.iq.FU_type_0::IntAlu 1234276939 61.22% 61.22% # Type of FU issued
214 system.cpu.iq.FU_type_0::IntMult 932607 0.05% 61.27% # Type of FU issued
215 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.27% # Type of FU issued
216 system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.27% # Type of FU issued
217 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.27% # Type of FU issued
218 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.27% # Type of FU issued
219 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.27% # Type of FU issued
220 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.27% # Type of FU issued
221 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.27% # Type of FU issued
222 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.27% # Type of FU issued
223 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.27% # Type of FU issued
224 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.27% # Type of FU issued
225 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.27% # Type of FU issued
226 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.27% # Type of FU issued
227 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.27% # Type of FU issued
228 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.27% # Type of FU issued
229 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.27% # Type of FU issued
230 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.27% # Type of FU issued
231 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.27% # Type of FU issued
232 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.27% # Type of FU issued
233 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.27% # Type of FU issued
234 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.27% # Type of FU issued
235 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.27% # Type of FU issued
236 system.cpu.iq.FU_type_0::SimdFloatCvt 77 0.00% 61.27% # Type of FU issued
237 system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 61.27% # Type of FU issued
238 system.cpu.iq.FU_type_0::SimdFloatMisc 29 0.00% 61.27% # Type of FU issued
239 system.cpu.iq.FU_type_0::SimdFloatMult 14 0.00% 61.27% # Type of FU issued
240 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.27% # Type of FU issued
241 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.27% # Type of FU issued
242 system.cpu.iq.FU_type_0::MemRead 587048024 29.12% 90.39% # Type of FU issued
243 system.cpu.iq.FU_type_0::MemWrite 193798201 9.61% 100.00% # Type of FU issued
244 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
245 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
246 system.cpu.iq.FU_type_0::total 2016055896 # Type of FU issued
247 system.cpu.iq.rate 2.172504 # Inst issue rate
248 system.cpu.iq.fu_busy_cnt 25092977 # FU busy when requested
249 system.cpu.iq.fu_busy_rate 0.012447 # FU busy rate (busy events/executed inst)
250 system.cpu.iq.int_inst_queue_reads 4980543862 # Number of integer instruction queue reads
251 system.cpu.iq.int_inst_queue_writes 2653539100 # Number of integer instruction queue writes
252 system.cpu.iq.int_inst_queue_wakeup_accesses 1958126109 # Number of integer instruction queue wakeup accesses
253 system.cpu.iq.fp_inst_queue_reads 448 # Number of floating instruction queue reads
254 system.cpu.iq.fp_inst_queue_writes 790 # Number of floating instruction queue writes
255 system.cpu.iq.fp_inst_queue_wakeup_accesses 172 # Number of floating instruction queue wakeup accesses
256 system.cpu.iq.int_alu_accesses 2041148646 # Number of integer alu accesses
257 system.cpu.iq.fp_alu_accesses 227 # Number of floating point alu accesses
258 system.cpu.iew.lsq.thread0.forwLoads 63700277 # Number of loads that had data forwarded from stores
259 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
260 system.cpu.iew.lsq.thread0.squashedLoads 138913044 # Number of loads squashed
261 system.cpu.iew.lsq.thread0.ignoredResponses 284373 # Number of memory responses ignored because the instruction is squashed
262 system.cpu.iew.lsq.thread0.memOrderViolation 189336 # Number of memory ordering violations
263 system.cpu.iew.lsq.thread0.squashedStores 43895340 # Number of stores squashed
264 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
265 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
266 system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
267 system.cpu.iew.lsq.thread0.cacheBlocked 451092 # Number of times an access to memory failed due to the cache being blocked
268 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
269 system.cpu.iew.iewSquashCycles 67239337 # Number of cycles IEW is squashing
270 system.cpu.iew.iewBlockCycles 23164250 # Number of cycles IEW is blocking
271 system.cpu.iew.iewUnblockCycles 1316440 # Number of cycles IEW is unblocking
272 system.cpu.iew.iewDispatchedInsts 2190576494 # Number of instructions dispatched to IQ
273 system.cpu.iew.iewDispSquashedInsts 5585867 # Number of squashed instructions skipped by dispatch
274 system.cpu.iew.iewDispLoadInsts 624839821 # Number of dispatched load instructions
275 system.cpu.iew.iewDispStoreInsts 218742392 # Number of dispatched store instructions
276 system.cpu.iew.iewDispNonSpecInsts 626 # Number of dispatched non-speculative instructions
277 system.cpu.iew.iewIQFullEvents 207277 # Number of times the IQ has become full, causing a stall
278 system.cpu.iew.iewLSQFullEvents 49894 # Number of times the LSQ has become full, causing a stall
279 system.cpu.iew.memOrderViolationEvents 189336 # Number of memory order violations
280 system.cpu.iew.predictedTakenIncorrect 8626288 # Number of branches that were predicted taken incorrectly
281 system.cpu.iew.predictedNotTakenIncorrect 10208500 # Number of branches that were predicted not taken incorrectly
282 system.cpu.iew.branchMispredicts 18834788 # Number of branch mispredicts detected at execute
283 system.cpu.iew.iewExecutedInsts 1986583692 # Number of executed instructions
284 system.cpu.iew.iewExecLoadInsts 572477440 # Number of load instructions executed
285 system.cpu.iew.iewExecSquashedInsts 29472204 # Number of squashed instructions skipped in execute
286 system.cpu.iew.exec_swp 0 # number of swp insts executed
287 system.cpu.iew.exec_nop 8125 # number of nop insts executed
288 system.cpu.iew.exec_refs 763312359 # number of memory reference insts executed
289 system.cpu.iew.exec_branches 238194699 # Number of branches executed
290 system.cpu.iew.exec_stores 190834919 # Number of stores executed
291 system.cpu.iew.exec_rate 2.140744 # Inst execution rate
292 system.cpu.iew.wb_sent 1967109112 # cumulative count of insts sent to commit
293 system.cpu.iew.wb_count 1958126281 # cumulative count of insts written-back
294 system.cpu.iew.wb_producers 1296093484 # num instructions producing a value
295 system.cpu.iew.wb_consumers 2068479796 # num instructions consuming a value
296 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
297 system.cpu.iew.wb_rate 2.110079 # insts written-back per cycle
298 system.cpu.iew.wb_fanout 0.626592 # average fanout of values written-back
299 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
300 system.cpu.commit.commitCommittedInsts 1544563084 # The number of committed instructions
301 system.cpu.commit.commitCommittedOps 1723073897 # The number of committed instructions
302 system.cpu.commit.commitSquashedInsts 467569115 # The number of squashed insts skipped by commit
303 system.cpu.commit.commitNonSpecStalls 177 # The number of times commit has been forced to stall to communicate backwards
304 system.cpu.commit.branchMispredicts 16098007 # The number of times a branch was mispredicted
305 system.cpu.commit.committed_per_cycle::samples 851207464 # Number of insts commited each cycle
306 system.cpu.commit.committed_per_cycle::mean 2.024270 # Number of insts commited each cycle
307 system.cpu.commit.committed_per_cycle::stdev 2.756192 # Number of insts commited each cycle
308 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
309 system.cpu.commit.committed_per_cycle::0 362905349 42.63% 42.63% # Number of insts commited each cycle
310 system.cpu.commit.committed_per_cycle::1 192760849 22.65% 65.28% # Number of insts commited each cycle
311 system.cpu.commit.committed_per_cycle::2 73571189 8.64% 73.92% # Number of insts commited each cycle
312 system.cpu.commit.committed_per_cycle::3 35131293 4.13% 78.05% # Number of insts commited each cycle
313 system.cpu.commit.committed_per_cycle::4 18689200 2.20% 80.25% # Number of insts commited each cycle
314 system.cpu.commit.committed_per_cycle::5 30622248 3.60% 83.84% # Number of insts commited each cycle
315 system.cpu.commit.committed_per_cycle::6 19666355 2.31% 86.15% # Number of insts commited each cycle
316 system.cpu.commit.committed_per_cycle::7 10977227 1.29% 87.44% # Number of insts commited each cycle
317 system.cpu.commit.committed_per_cycle::8 106883754 12.56% 100.00% # Number of insts commited each cycle
318 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
319 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
320 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
321 system.cpu.commit.committed_per_cycle::total 851207464 # Number of insts commited each cycle
322 system.cpu.commit.committedInsts 1544563084 # Number of instructions committed
323 system.cpu.commit.committedOps 1723073897 # Number of ops (including micro ops) committed
324 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
325 system.cpu.commit.refs 660773829 # Number of memory references committed
326 system.cpu.commit.loads 485926777 # Number of loads committed
327 system.cpu.commit.membars 62 # Number of memory barriers committed
328 system.cpu.commit.branches 213462371 # Number of branches committed
329 system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
330 system.cpu.commit.int_insts 1536941877 # Number of committed integer instructions.
331 system.cpu.commit.function_calls 13665177 # Number of function calls committed.
332 system.cpu.commit.bw_lim_events 106883754 # number cycles where commit BW limit reached
333 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
334 system.cpu.rob.rob_reads 2934966123 # The number of ROB reads
335 system.cpu.rob.rob_writes 4448699546 # The number of ROB writes
336 system.cpu.timesIdled 899596 # Number of times that the entire CPU went into an idle state and unscheduled itself
337 system.cpu.idleCycles 9540588 # Total number of cycles that the CPU has spent unscheduled due to idling
338 system.cpu.committedInsts 1544563066 # Number of Instructions Simulated
339 system.cpu.committedOps 1723073879 # Number of Ops (including micro ops) Simulated
340 system.cpu.committedInsts_total 1544563066 # Number of Instructions Simulated
341 system.cpu.cpi 0.600809 # CPI: Cycles Per Instruction
342 system.cpu.cpi_total 0.600809 # CPI: Total CPI of All Threads
343 system.cpu.ipc 1.664422 # IPC: Instructions Per Cycle
344 system.cpu.ipc_total 1.664422 # IPC: Total IPC of All Threads
345 system.cpu.int_regfile_reads 9951953141 # number of integer regfile reads
346 system.cpu.int_regfile_writes 1938266429 # number of integer regfile writes
347 system.cpu.fp_regfile_reads 186 # number of floating regfile reads
348 system.cpu.fp_regfile_writes 205 # number of floating regfile writes
349 system.cpu.misc_regfile_reads 2897977277 # number of misc regfile reads
350 system.cpu.misc_regfile_writes 138 # number of misc regfile writes
351 system.cpu.icache.replacements 28 # number of replacements
352 system.cpu.icache.tagsinuse 641.389873 # Cycle average of tags in use
353 system.cpu.icache.total_refs 283729068 # Total number of references to valid blocks.
354 system.cpu.icache.sampled_refs 801 # Sample count of references to valid blocks.
355 system.cpu.icache.avg_refs 354218.561798 # Average number of references to valid blocks.
356 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
357 system.cpu.icache.occ_blocks::cpu.inst 641.389873 # Average occupied blocks per requestor
358 system.cpu.icache.occ_percent::cpu.inst 0.313179 # Average percentage of cache occupancy
359 system.cpu.icache.occ_percent::total 0.313179 # Average percentage of cache occupancy
360 system.cpu.icache.ReadReq_hits::cpu.inst 283729068 # number of ReadReq hits
361 system.cpu.icache.ReadReq_hits::total 283729068 # number of ReadReq hits
362 system.cpu.icache.demand_hits::cpu.inst 283729068 # number of demand (read+write) hits
363 system.cpu.icache.demand_hits::total 283729068 # number of demand (read+write) hits
364 system.cpu.icache.overall_hits::cpu.inst 283729068 # number of overall hits
365 system.cpu.icache.overall_hits::total 283729068 # number of overall hits
366 system.cpu.icache.ReadReq_misses::cpu.inst 1197 # number of ReadReq misses
367 system.cpu.icache.ReadReq_misses::total 1197 # number of ReadReq misses
368 system.cpu.icache.demand_misses::cpu.inst 1197 # number of demand (read+write) misses
369 system.cpu.icache.demand_misses::total 1197 # number of demand (read+write) misses
370 system.cpu.icache.overall_misses::cpu.inst 1197 # number of overall misses
371 system.cpu.icache.overall_misses::total 1197 # number of overall misses
372 system.cpu.icache.ReadReq_miss_latency::cpu.inst 39840000 # number of ReadReq miss cycles
373 system.cpu.icache.ReadReq_miss_latency::total 39840000 # number of ReadReq miss cycles
374 system.cpu.icache.demand_miss_latency::cpu.inst 39840000 # number of demand (read+write) miss cycles
375 system.cpu.icache.demand_miss_latency::total 39840000 # number of demand (read+write) miss cycles
376 system.cpu.icache.overall_miss_latency::cpu.inst 39840000 # number of overall miss cycles
377 system.cpu.icache.overall_miss_latency::total 39840000 # number of overall miss cycles
378 system.cpu.icache.ReadReq_accesses::cpu.inst 283730265 # number of ReadReq accesses(hits+misses)
379 system.cpu.icache.ReadReq_accesses::total 283730265 # number of ReadReq accesses(hits+misses)
380 system.cpu.icache.demand_accesses::cpu.inst 283730265 # number of demand (read+write) accesses
381 system.cpu.icache.demand_accesses::total 283730265 # number of demand (read+write) accesses
382 system.cpu.icache.overall_accesses::cpu.inst 283730265 # number of overall (read+write) accesses
383 system.cpu.icache.overall_accesses::total 283730265 # number of overall (read+write) accesses
384 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
385 system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
386 system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
387 system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
388 system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
389 system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
390 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33283.208020 # average ReadReq miss latency
391 system.cpu.icache.ReadReq_avg_miss_latency::total 33283.208020 # average ReadReq miss latency
392 system.cpu.icache.demand_avg_miss_latency::cpu.inst 33283.208020 # average overall miss latency
393 system.cpu.icache.demand_avg_miss_latency::total 33283.208020 # average overall miss latency
394 system.cpu.icache.overall_avg_miss_latency::cpu.inst 33283.208020 # average overall miss latency
395 system.cpu.icache.overall_avg_miss_latency::total 33283.208020 # average overall miss latency
396 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
397 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
398 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
399 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
400 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
401 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
402 system.cpu.icache.fast_writes 0 # number of fast writes performed
403 system.cpu.icache.cache_copies 0 # number of cache copies performed
404 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 396 # number of ReadReq MSHR hits
405 system.cpu.icache.ReadReq_mshr_hits::total 396 # number of ReadReq MSHR hits
406 system.cpu.icache.demand_mshr_hits::cpu.inst 396 # number of demand (read+write) MSHR hits
407 system.cpu.icache.demand_mshr_hits::total 396 # number of demand (read+write) MSHR hits
408 system.cpu.icache.overall_mshr_hits::cpu.inst 396 # number of overall MSHR hits
409 system.cpu.icache.overall_mshr_hits::total 396 # number of overall MSHR hits
410 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 801 # number of ReadReq MSHR misses
411 system.cpu.icache.ReadReq_mshr_misses::total 801 # number of ReadReq MSHR misses
412 system.cpu.icache.demand_mshr_misses::cpu.inst 801 # number of demand (read+write) MSHR misses
413 system.cpu.icache.demand_mshr_misses::total 801 # number of demand (read+write) MSHR misses
414 system.cpu.icache.overall_mshr_misses::cpu.inst 801 # number of overall MSHR misses
415 system.cpu.icache.overall_mshr_misses::total 801 # number of overall MSHR misses
416 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27579500 # number of ReadReq MSHR miss cycles
417 system.cpu.icache.ReadReq_mshr_miss_latency::total 27579500 # number of ReadReq MSHR miss cycles
418 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27579500 # number of demand (read+write) MSHR miss cycles
419 system.cpu.icache.demand_mshr_miss_latency::total 27579500 # number of demand (read+write) MSHR miss cycles
420 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27579500 # number of overall MSHR miss cycles
421 system.cpu.icache.overall_mshr_miss_latency::total 27579500 # number of overall MSHR miss cycles
422 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
423 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses
424 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
425 system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses
426 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
427 system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses
428 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34431.335830 # average ReadReq mshr miss latency
429 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34431.335830 # average ReadReq mshr miss latency
430 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34431.335830 # average overall mshr miss latency
431 system.cpu.icache.demand_avg_mshr_miss_latency::total 34431.335830 # average overall mshr miss latency
432 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34431.335830 # average overall mshr miss latency
433 system.cpu.icache.overall_avg_mshr_miss_latency::total 34431.335830 # average overall mshr miss latency
434 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
435 system.cpu.dcache.replacements 9619302 # number of replacements
436 system.cpu.dcache.tagsinuse 4087.756066 # Cycle average of tags in use
437 system.cpu.dcache.total_refs 660726669 # Total number of references to valid blocks.
438 system.cpu.dcache.sampled_refs 9623398 # Sample count of references to valid blocks.
439 system.cpu.dcache.avg_refs 68.658354 # Average number of references to valid blocks.
440 system.cpu.dcache.warmup_cycle 3346373000 # Cycle when the warmup percentage was hit.
441 system.cpu.dcache.occ_blocks::cpu.data 4087.756066 # Average occupied blocks per requestor
442 system.cpu.dcache.occ_percent::cpu.data 0.997987 # Average percentage of cache occupancy
443 system.cpu.dcache.occ_percent::total 0.997987 # Average percentage of cache occupancy
444 system.cpu.dcache.ReadReq_hits::cpu.data 493348220 # number of ReadReq hits
445 system.cpu.dcache.ReadReq_hits::total 493348220 # number of ReadReq hits
446 system.cpu.dcache.WriteReq_hits::cpu.data 167378287 # number of WriteReq hits
447 system.cpu.dcache.WriteReq_hits::total 167378287 # number of WriteReq hits
448 system.cpu.dcache.LoadLockedReq_hits::cpu.data 94 # number of LoadLockedReq hits
449 system.cpu.dcache.LoadLockedReq_hits::total 94 # number of LoadLockedReq hits
450 system.cpu.dcache.StoreCondReq_hits::cpu.data 68 # number of StoreCondReq hits
451 system.cpu.dcache.StoreCondReq_hits::total 68 # number of StoreCondReq hits
452 system.cpu.dcache.demand_hits::cpu.data 660726507 # number of demand (read+write) hits
453 system.cpu.dcache.demand_hits::total 660726507 # number of demand (read+write) hits
454 system.cpu.dcache.overall_hits::cpu.data 660726507 # number of overall hits
455 system.cpu.dcache.overall_hits::total 660726507 # number of overall hits
456 system.cpu.dcache.ReadReq_misses::cpu.data 10693817 # number of ReadReq misses
457 system.cpu.dcache.ReadReq_misses::total 10693817 # number of ReadReq misses
458 system.cpu.dcache.WriteReq_misses::cpu.data 5207760 # number of WriteReq misses
459 system.cpu.dcache.WriteReq_misses::total 5207760 # number of WriteReq misses
460 system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
461 system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
462 system.cpu.dcache.demand_misses::cpu.data 15901577 # number of demand (read+write) misses
463 system.cpu.dcache.demand_misses::total 15901577 # number of demand (read+write) misses
464 system.cpu.dcache.overall_misses::cpu.data 15901577 # number of overall misses
465 system.cpu.dcache.overall_misses::total 15901577 # number of overall misses
466 system.cpu.dcache.ReadReq_miss_latency::cpu.data 189065481500 # number of ReadReq miss cycles
467 system.cpu.dcache.ReadReq_miss_latency::total 189065481500 # number of ReadReq miss cycles
468 system.cpu.dcache.WriteReq_miss_latency::cpu.data 129319032251 # number of WriteReq miss cycles
469 system.cpu.dcache.WriteReq_miss_latency::total 129319032251 # number of WriteReq miss cycles
470 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 113500 # number of LoadLockedReq miss cycles
471 system.cpu.dcache.LoadLockedReq_miss_latency::total 113500 # number of LoadLockedReq miss cycles
472 system.cpu.dcache.demand_miss_latency::cpu.data 318384513751 # number of demand (read+write) miss cycles
473 system.cpu.dcache.demand_miss_latency::total 318384513751 # number of demand (read+write) miss cycles
474 system.cpu.dcache.overall_miss_latency::cpu.data 318384513751 # number of overall miss cycles
475 system.cpu.dcache.overall_miss_latency::total 318384513751 # number of overall miss cycles
476 system.cpu.dcache.ReadReq_accesses::cpu.data 504042037 # number of ReadReq accesses(hits+misses)
477 system.cpu.dcache.ReadReq_accesses::total 504042037 # number of ReadReq accesses(hits+misses)
478 system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
479 system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
480 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 97 # number of LoadLockedReq accesses(hits+misses)
481 system.cpu.dcache.LoadLockedReq_accesses::total 97 # number of LoadLockedReq accesses(hits+misses)
482 system.cpu.dcache.StoreCondReq_accesses::cpu.data 68 # number of StoreCondReq accesses(hits+misses)
483 system.cpu.dcache.StoreCondReq_accesses::total 68 # number of StoreCondReq accesses(hits+misses)
484 system.cpu.dcache.demand_accesses::cpu.data 676628084 # number of demand (read+write) accesses
485 system.cpu.dcache.demand_accesses::total 676628084 # number of demand (read+write) accesses
486 system.cpu.dcache.overall_accesses::cpu.data 676628084 # number of overall (read+write) accesses
487 system.cpu.dcache.overall_accesses::total 676628084 # number of overall (read+write) accesses
488 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021216 # miss rate for ReadReq accesses
489 system.cpu.dcache.ReadReq_miss_rate::total 0.021216 # miss rate for ReadReq accesses
490 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030175 # miss rate for WriteReq accesses
491 system.cpu.dcache.WriteReq_miss_rate::total 0.030175 # miss rate for WriteReq accesses
492 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.030928 # miss rate for LoadLockedReq accesses
493 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.030928 # miss rate for LoadLockedReq accesses
494 system.cpu.dcache.demand_miss_rate::cpu.data 0.023501 # miss rate for demand accesses
495 system.cpu.dcache.demand_miss_rate::total 0.023501 # miss rate for demand accesses
496 system.cpu.dcache.overall_miss_rate::cpu.data 0.023501 # miss rate for overall accesses
497 system.cpu.dcache.overall_miss_rate::total 0.023501 # miss rate for overall accesses
498 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17679.887499 # average ReadReq miss latency
499 system.cpu.dcache.ReadReq_avg_miss_latency::total 17679.887499 # average ReadReq miss latency
500 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24831.987697 # average WriteReq miss latency
501 system.cpu.dcache.WriteReq_avg_miss_latency::total 24831.987697 # average WriteReq miss latency
502 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37833.333333 # average LoadLockedReq miss latency
503 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37833.333333 # average LoadLockedReq miss latency
504 system.cpu.dcache.demand_avg_miss_latency::cpu.data 20022.197405 # average overall miss latency
505 system.cpu.dcache.demand_avg_miss_latency::total 20022.197405 # average overall miss latency
506 system.cpu.dcache.overall_avg_miss_latency::cpu.data 20022.197405 # average overall miss latency
507 system.cpu.dcache.overall_avg_miss_latency::total 20022.197405 # average overall miss latency
508 system.cpu.dcache.blocked_cycles::no_mshrs 271440605 # number of cycles access was blocked
509 system.cpu.dcache.blocked_cycles::no_targets 164500 # number of cycles access was blocked
510 system.cpu.dcache.blocked::no_mshrs 91957 # number of cycles access was blocked
511 system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked
512 system.cpu.dcache.avg_blocked_cycles::no_mshrs 2951.821014 # average number of cycles each access was blocked
513 system.cpu.dcache.avg_blocked_cycles::no_targets 16450 # average number of cycles each access was blocked
514 system.cpu.dcache.fast_writes 0 # number of fast writes performed
515 system.cpu.dcache.cache_copies 0 # number of cache copies performed
516 system.cpu.dcache.writebacks::writebacks 3133684 # number of writebacks
517 system.cpu.dcache.writebacks::total 3133684 # number of writebacks
518 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2964371 # number of ReadReq MSHR hits
519 system.cpu.dcache.ReadReq_mshr_hits::total 2964371 # number of ReadReq MSHR hits
520 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3313808 # number of WriteReq MSHR hits
521 system.cpu.dcache.WriteReq_mshr_hits::total 3313808 # number of WriteReq MSHR hits
522 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
523 system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
524 system.cpu.dcache.demand_mshr_hits::cpu.data 6278179 # number of demand (read+write) MSHR hits
525 system.cpu.dcache.demand_mshr_hits::total 6278179 # number of demand (read+write) MSHR hits
526 system.cpu.dcache.overall_mshr_hits::cpu.data 6278179 # number of overall MSHR hits
527 system.cpu.dcache.overall_mshr_hits::total 6278179 # number of overall MSHR hits
528 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7729446 # number of ReadReq MSHR misses
529 system.cpu.dcache.ReadReq_mshr_misses::total 7729446 # number of ReadReq MSHR misses
530 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893952 # number of WriteReq MSHR misses
531 system.cpu.dcache.WriteReq_mshr_misses::total 1893952 # number of WriteReq MSHR misses
532 system.cpu.dcache.demand_mshr_misses::cpu.data 9623398 # number of demand (read+write) MSHR misses
533 system.cpu.dcache.demand_mshr_misses::total 9623398 # number of demand (read+write) MSHR misses
534 system.cpu.dcache.overall_mshr_misses::cpu.data 9623398 # number of overall MSHR misses
535 system.cpu.dcache.overall_mshr_misses::total 9623398 # number of overall MSHR misses
536 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 93061119500 # number of ReadReq MSHR miss cycles
537 system.cpu.dcache.ReadReq_mshr_miss_latency::total 93061119500 # number of ReadReq MSHR miss cycles
538 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 45369971960 # number of WriteReq MSHR miss cycles
539 system.cpu.dcache.WriteReq_mshr_miss_latency::total 45369971960 # number of WriteReq MSHR miss cycles
540 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 138431091460 # number of demand (read+write) MSHR miss cycles
541 system.cpu.dcache.demand_mshr_miss_latency::total 138431091460 # number of demand (read+write) MSHR miss cycles
542 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 138431091460 # number of overall MSHR miss cycles
543 system.cpu.dcache.overall_mshr_miss_latency::total 138431091460 # number of overall MSHR miss cycles
544 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015335 # mshr miss rate for ReadReq accesses
545 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015335 # mshr miss rate for ReadReq accesses
546 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010974 # mshr miss rate for WriteReq accesses
547 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010974 # mshr miss rate for WriteReq accesses
548 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014223 # mshr miss rate for demand accesses
549 system.cpu.dcache.demand_mshr_miss_rate::total 0.014223 # mshr miss rate for demand accesses
550 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014223 # mshr miss rate for overall accesses
551 system.cpu.dcache.overall_mshr_miss_rate::total 0.014223 # mshr miss rate for overall accesses
552 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12039.817537 # average ReadReq mshr miss latency
553 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12039.817537 # average ReadReq mshr miss latency
554 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23955.185749 # average WriteReq mshr miss latency
555 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23955.185749 # average WriteReq mshr miss latency
556 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14384.845297 # average overall mshr miss latency
557 system.cpu.dcache.demand_avg_mshr_miss_latency::total 14384.845297 # average overall mshr miss latency
558 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14384.845297 # average overall mshr miss latency
559 system.cpu.dcache.overall_avg_mshr_miss_latency::total 14384.845297 # average overall mshr miss latency
560 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
561 system.cpu.l2cache.replacements 2953110 # number of replacements
562 system.cpu.l2cache.tagsinuse 26875.343151 # Cycle average of tags in use
563 system.cpu.l2cache.total_refs 7878336 # Total number of references to valid blocks.
564 system.cpu.l2cache.sampled_refs 2980430 # Sample count of references to valid blocks.
565 system.cpu.l2cache.avg_refs 2.643355 # Average number of references to valid blocks.
566 system.cpu.l2cache.warmup_cycle 100989511500 # Cycle when the warmup percentage was hit.
567 system.cpu.l2cache.occ_blocks::writebacks 10758.137226 # Average occupied blocks per requestor
568 system.cpu.l2cache.occ_blocks::cpu.inst 11.396468 # Average occupied blocks per requestor
569 system.cpu.l2cache.occ_blocks::cpu.data 16105.809458 # Average occupied blocks per requestor
570 system.cpu.l2cache.occ_percent::writebacks 0.328312 # Average percentage of cache occupancy
571 system.cpu.l2cache.occ_percent::cpu.inst 0.000348 # Average percentage of cache occupancy
572 system.cpu.l2cache.occ_percent::cpu.data 0.491510 # Average percentage of cache occupancy
573 system.cpu.l2cache.occ_percent::total 0.820170 # Average percentage of cache occupancy
574 system.cpu.l2cache.ReadReq_hits::cpu.inst 29 # number of ReadReq hits
575 system.cpu.l2cache.ReadReq_hits::cpu.data 5680299 # number of ReadReq hits
576 system.cpu.l2cache.ReadReq_hits::total 5680328 # number of ReadReq hits
577 system.cpu.l2cache.Writeback_hits::writebacks 3133684 # number of Writeback hits
578 system.cpu.l2cache.Writeback_hits::total 3133684 # number of Writeback hits
579 system.cpu.l2cache.ReadExReq_hits::cpu.data 978305 # number of ReadExReq hits
580 system.cpu.l2cache.ReadExReq_hits::total 978305 # number of ReadExReq hits
581 system.cpu.l2cache.demand_hits::cpu.inst 29 # number of demand (read+write) hits
582 system.cpu.l2cache.demand_hits::cpu.data 6658604 # number of demand (read+write) hits
583 system.cpu.l2cache.demand_hits::total 6658633 # number of demand (read+write) hits
584 system.cpu.l2cache.overall_hits::cpu.inst 29 # number of overall hits
585 system.cpu.l2cache.overall_hits::cpu.data 6658604 # number of overall hits
586 system.cpu.l2cache.overall_hits::total 6658633 # number of overall hits
587 system.cpu.l2cache.ReadReq_misses::cpu.inst 772 # number of ReadReq misses
588 system.cpu.l2cache.ReadReq_misses::cpu.data 2049145 # number of ReadReq misses
589 system.cpu.l2cache.ReadReq_misses::total 2049917 # number of ReadReq misses
590 system.cpu.l2cache.ReadExReq_misses::cpu.data 915649 # number of ReadExReq misses
591 system.cpu.l2cache.ReadExReq_misses::total 915649 # number of ReadExReq misses
592 system.cpu.l2cache.demand_misses::cpu.inst 772 # number of demand (read+write) misses
593 system.cpu.l2cache.demand_misses::cpu.data 2964794 # number of demand (read+write) misses
594 system.cpu.l2cache.demand_misses::total 2965566 # number of demand (read+write) misses
595 system.cpu.l2cache.overall_misses::cpu.inst 772 # number of overall misses
596 system.cpu.l2cache.overall_misses::cpu.data 2964794 # number of overall misses
597 system.cpu.l2cache.overall_misses::total 2965566 # number of overall misses
598 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26523500 # number of ReadReq miss cycles
599 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 70343968500 # number of ReadReq miss cycles
600 system.cpu.l2cache.ReadReq_miss_latency::total 70370492000 # number of ReadReq miss cycles
601 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 31764549000 # number of ReadExReq miss cycles
602 system.cpu.l2cache.ReadExReq_miss_latency::total 31764549000 # number of ReadExReq miss cycles
603 system.cpu.l2cache.demand_miss_latency::cpu.inst 26523500 # number of demand (read+write) miss cycles
604 system.cpu.l2cache.demand_miss_latency::cpu.data 102108517500 # number of demand (read+write) miss cycles
605 system.cpu.l2cache.demand_miss_latency::total 102135041000 # number of demand (read+write) miss cycles
606 system.cpu.l2cache.overall_miss_latency::cpu.inst 26523500 # number of overall miss cycles
607 system.cpu.l2cache.overall_miss_latency::cpu.data 102108517500 # number of overall miss cycles
608 system.cpu.l2cache.overall_miss_latency::total 102135041000 # number of overall miss cycles
609 system.cpu.l2cache.ReadReq_accesses::cpu.inst 801 # number of ReadReq accesses(hits+misses)
610 system.cpu.l2cache.ReadReq_accesses::cpu.data 7729444 # number of ReadReq accesses(hits+misses)
611 system.cpu.l2cache.ReadReq_accesses::total 7730245 # number of ReadReq accesses(hits+misses)
612 system.cpu.l2cache.Writeback_accesses::writebacks 3133684 # number of Writeback accesses(hits+misses)
613 system.cpu.l2cache.Writeback_accesses::total 3133684 # number of Writeback accesses(hits+misses)
614 system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893954 # number of ReadExReq accesses(hits+misses)
615 system.cpu.l2cache.ReadExReq_accesses::total 1893954 # number of ReadExReq accesses(hits+misses)
616 system.cpu.l2cache.demand_accesses::cpu.inst 801 # number of demand (read+write) accesses
617 system.cpu.l2cache.demand_accesses::cpu.data 9623398 # number of demand (read+write) accesses
618 system.cpu.l2cache.demand_accesses::total 9624199 # number of demand (read+write) accesses
619 system.cpu.l2cache.overall_accesses::cpu.inst 801 # number of overall (read+write) accesses
620 system.cpu.l2cache.overall_accesses::cpu.data 9623398 # number of overall (read+write) accesses
621 system.cpu.l2cache.overall_accesses::total 9624199 # number of overall (read+write) accesses
622 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.963795 # miss rate for ReadReq accesses
623 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.265109 # miss rate for ReadReq accesses
624 system.cpu.l2cache.ReadReq_miss_rate::total 0.265181 # miss rate for ReadReq accesses
625 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.483459 # miss rate for ReadExReq accesses
626 system.cpu.l2cache.ReadExReq_miss_rate::total 0.483459 # miss rate for ReadExReq accesses
627 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963795 # miss rate for demand accesses
628 system.cpu.l2cache.demand_miss_rate::cpu.data 0.308082 # miss rate for demand accesses
629 system.cpu.l2cache.demand_miss_rate::total 0.308136 # miss rate for demand accesses
630 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963795 # miss rate for overall accesses
631 system.cpu.l2cache.overall_miss_rate::cpu.data 0.308082 # miss rate for overall accesses
632 system.cpu.l2cache.overall_miss_rate::total 0.308136 # miss rate for overall accesses
633 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34356.865285 # average ReadReq miss latency
634 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34328.448450 # average ReadReq miss latency
635 system.cpu.l2cache.ReadReq_avg_miss_latency::total 34328.459152 # average ReadReq miss latency
636 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34690.748311 # average ReadExReq miss latency
637 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34690.748311 # average ReadExReq miss latency
638 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34356.865285 # average overall miss latency
639 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34440.341386 # average overall miss latency
640 system.cpu.l2cache.demand_avg_miss_latency::total 34440.319656 # average overall miss latency
641 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34356.865285 # average overall miss latency
642 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34440.341386 # average overall miss latency
643 system.cpu.l2cache.overall_avg_miss_latency::total 34440.319656 # average overall miss latency
644 system.cpu.l2cache.blocked_cycles::no_mshrs 57329500 # number of cycles access was blocked
645 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
646 system.cpu.l2cache.blocked::no_mshrs 6735 # number of cycles access was blocked
647 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
648 system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8512.175204 # average number of cycles each access was blocked
649 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
650 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
651 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
652 system.cpu.l2cache.writebacks::writebacks 1222221 # number of writebacks
653 system.cpu.l2cache.writebacks::total 1222221 # number of writebacks
654 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
655 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits
656 system.cpu.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits
657 system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
658 system.cpu.l2cache.demand_mshr_hits::cpu.data 8 # number of demand (read+write) MSHR hits
659 system.cpu.l2cache.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits
660 system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
661 system.cpu.l2cache.overall_mshr_hits::cpu.data 8 # number of overall MSHR hits
662 system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits
663 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 771 # number of ReadReq MSHR misses
664 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 2049137 # number of ReadReq MSHR misses
665 system.cpu.l2cache.ReadReq_mshr_misses::total 2049908 # number of ReadReq MSHR misses
666 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 915649 # number of ReadExReq MSHR misses
667 system.cpu.l2cache.ReadExReq_mshr_misses::total 915649 # number of ReadExReq MSHR misses
668 system.cpu.l2cache.demand_mshr_misses::cpu.inst 771 # number of demand (read+write) MSHR misses
669 system.cpu.l2cache.demand_mshr_misses::cpu.data 2964786 # number of demand (read+write) MSHR misses
670 system.cpu.l2cache.demand_mshr_misses::total 2965557 # number of demand (read+write) MSHR misses
671 system.cpu.l2cache.overall_mshr_misses::cpu.inst 771 # number of overall MSHR misses
672 system.cpu.l2cache.overall_mshr_misses::cpu.data 2964786 # number of overall MSHR misses
673 system.cpu.l2cache.overall_mshr_misses::total 2965557 # number of overall MSHR misses
674 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24050500 # number of ReadReq MSHR miss cycles
675 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 63906561000 # number of ReadReq MSHR miss cycles
676 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 63930611500 # number of ReadReq MSHR miss cycles
677 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 28918183500 # number of ReadExReq MSHR miss cycles
678 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 28918183500 # number of ReadExReq MSHR miss cycles
679 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24050500 # number of demand (read+write) MSHR miss cycles
680 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 92824744500 # number of demand (read+write) MSHR miss cycles
681 system.cpu.l2cache.demand_mshr_miss_latency::total 92848795000 # number of demand (read+write) MSHR miss cycles
682 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24050500 # number of overall MSHR miss cycles
683 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 92824744500 # number of overall MSHR miss cycles
684 system.cpu.l2cache.overall_mshr_miss_latency::total 92848795000 # number of overall MSHR miss cycles
685 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962547 # mshr miss rate for ReadReq accesses
686 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.265108 # mshr miss rate for ReadReq accesses
687 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.265180 # mshr miss rate for ReadReq accesses
688 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.483459 # mshr miss rate for ReadExReq accesses
689 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.483459 # mshr miss rate for ReadExReq accesses
690 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962547 # mshr miss rate for demand accesses
691 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.308081 # mshr miss rate for demand accesses
692 system.cpu.l2cache.demand_mshr_miss_rate::total 0.308135 # mshr miss rate for demand accesses
693 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962547 # mshr miss rate for overall accesses
694 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.308081 # mshr miss rate for overall accesses
695 system.cpu.l2cache.overall_mshr_miss_rate::total 0.308135 # mshr miss rate for overall accesses
696 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31193.904021 # average ReadReq mshr miss latency
697 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31187.061187 # average ReadReq mshr miss latency
698 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31187.063761 # average ReadReq mshr miss latency
699 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31582.171225 # average ReadExReq mshr miss latency
700 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31582.171225 # average ReadExReq mshr miss latency
701 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31193.904021 # average overall mshr miss latency
702 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31309.087570 # average overall mshr miss latency
703 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31309.057624 # average overall mshr miss latency
704 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31193.904021 # average overall mshr miss latency
705 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31309.087570 # average overall mshr miss latency
706 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31309.057624 # average overall mshr miss latency
707 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
709 ---------- End Simulation Statistics ----------
projects / gem5.git / blob