2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 2.391205 # Number of seconds simulated
4 sim_ticks 2391205115000 # Number of ticks simulated
5 final_tick 2391205115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 809589 # Simulator instruction rate (inst/s)
8 host_op_rate 903509 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 1258086461 # Simulator tick rate (ticks/s)
10 host_mem_usage 287292 # Number of bytes of host memory used
11 host_seconds 1900.67 # Real time elapsed on the host
12 sim_insts 1538759601 # Number of instructions simulated
13 sim_ops 1717270334 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 125322112 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 125361536 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory
19 system.physmem.bytes_written::writebacks 65100672 # Number of bytes written to this memory
20 system.physmem.bytes_written::total 65100672 # Number of bytes written to this memory
21 system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory
22 system.physmem.num_reads::cpu.data 1958158 # Number of read requests responded to by this memory
23 system.physmem.num_reads::total 1958774 # Number of read requests responded to by this memory
24 system.physmem.num_writes::writebacks 1017198 # Number of write requests responded to by this memory
25 system.physmem.num_writes::total 1017198 # Number of write requests responded to by this memory
26 system.physmem.bw_read::cpu.inst 16487 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_read::cpu.data 52409604 # Total read bandwidth from this memory (bytes/s)
28 system.physmem.bw_read::total 52426091 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_inst_read::cpu.inst 16487 # Instruction read bandwidth from this memory (bytes/s)
30 system.physmem.bw_inst_read::total 16487 # Instruction read bandwidth from this memory (bytes/s)
31 system.physmem.bw_write::writebacks 27225047 # Write bandwidth from this memory (bytes/s)
32 system.physmem.bw_write::total 27225047 # Write bandwidth from this memory (bytes/s)
33 system.physmem.bw_total::writebacks 27225047 # Total bandwidth to/from this memory (bytes/s)
34 system.physmem.bw_total::cpu.inst 16487 # Total bandwidth to/from this memory (bytes/s)
35 system.physmem.bw_total::cpu.data 52409604 # Total bandwidth to/from this memory (bytes/s)
36 system.physmem.bw_total::total 79651138 # Total bandwidth to/from this memory (bytes/s)
37 system.cpu.dtb.inst_hits 0 # ITB inst hits
38 system.cpu.dtb.inst_misses 0 # ITB inst misses
39 system.cpu.dtb.read_hits 0 # DTB read hits
40 system.cpu.dtb.read_misses 0 # DTB read misses
41 system.cpu.dtb.write_hits 0 # DTB write hits
42 system.cpu.dtb.write_misses 0 # DTB write misses
43 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
44 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
45 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
46 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
47 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
48 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
49 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
50 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
51 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
52 system.cpu.dtb.read_accesses 0 # DTB read accesses
53 system.cpu.dtb.write_accesses 0 # DTB write accesses
54 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
55 system.cpu.dtb.hits 0 # DTB hits
56 system.cpu.dtb.misses 0 # DTB misses
57 system.cpu.dtb.accesses 0 # DTB accesses
58 system.cpu.itb.inst_hits 0 # ITB inst hits
59 system.cpu.itb.inst_misses 0 # ITB inst misses
60 system.cpu.itb.read_hits 0 # DTB read hits
61 system.cpu.itb.read_misses 0 # DTB read misses
62 system.cpu.itb.write_hits 0 # DTB write hits
63 system.cpu.itb.write_misses 0 # DTB write misses
64 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
65 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
66 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
67 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
68 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
69 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
70 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
71 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
72 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
73 system.cpu.itb.read_accesses 0 # DTB read accesses
74 system.cpu.itb.write_accesses 0 # DTB write accesses
75 system.cpu.itb.inst_accesses 0 # ITB inst accesses
76 system.cpu.itb.hits 0 # DTB hits
77 system.cpu.itb.misses 0 # DTB misses
78 system.cpu.itb.accesses 0 # DTB accesses
79 system.cpu.workload.num_syscalls 46 # Number of system calls
80 system.cpu.numCycles 4782410230 # number of cpu cycles simulated
81 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
82 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
83 system.cpu.committedInsts 1538759601 # Number of instructions committed
84 system.cpu.committedOps 1717270334 # Number of ops (including micro ops) committed
85 system.cpu.num_int_alu_accesses 1536941842 # Number of integer alu accesses
86 system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses
87 system.cpu.num_func_calls 27330256 # number of times a function call or return occured
88 system.cpu.num_conditional_control_insts 177498328 # number of instructions that are conditional controls
89 system.cpu.num_int_insts 1536941842 # number of integer instructions
90 system.cpu.num_fp_insts 36 # number of float instructions
91 system.cpu.num_int_register_reads 9304894672 # number of times the integer registers were read
92 system.cpu.num_int_register_writes 1675132405 # number of times the integer registers were written
93 system.cpu.num_fp_register_reads 24 # number of times the floating registers were read
94 system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
95 system.cpu.num_mem_refs 660773815 # number of memory refs
96 system.cpu.num_load_insts 485926769 # Number of load instructions
97 system.cpu.num_store_insts 174847046 # Number of store instructions
98 system.cpu.num_idle_cycles 0 # Number of idle cycles
99 system.cpu.num_busy_cycles 4782410230 # Number of busy cycles
100 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
101 system.cpu.idle_fraction 0 # Percentage of idle cycles
102 system.cpu.icache.replacements 7 # number of replacements
103 system.cpu.icache.tagsinuse 514.976015 # Cycle average of tags in use
104 system.cpu.icache.total_refs 1544564952 # Total number of references to valid blocks.
105 system.cpu.icache.sampled_refs 638 # Sample count of references to valid blocks.
106 system.cpu.icache.avg_refs 2420948.200627 # Average number of references to valid blocks.
107 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
108 system.cpu.icache.occ_blocks::cpu.inst 514.976015 # Average occupied blocks per requestor
109 system.cpu.icache.occ_percent::cpu.inst 0.251453 # Average percentage of cache occupancy
110 system.cpu.icache.occ_percent::total 0.251453 # Average percentage of cache occupancy
111 system.cpu.icache.ReadReq_hits::cpu.inst 1544564952 # number of ReadReq hits
112 system.cpu.icache.ReadReq_hits::total 1544564952 # number of ReadReq hits
113 system.cpu.icache.demand_hits::cpu.inst 1544564952 # number of demand (read+write) hits
114 system.cpu.icache.demand_hits::total 1544564952 # number of demand (read+write) hits
115 system.cpu.icache.overall_hits::cpu.inst 1544564952 # number of overall hits
116 system.cpu.icache.overall_hits::total 1544564952 # number of overall hits
117 system.cpu.icache.ReadReq_misses::cpu.inst 638 # number of ReadReq misses
118 system.cpu.icache.ReadReq_misses::total 638 # number of ReadReq misses
119 system.cpu.icache.demand_misses::cpu.inst 638 # number of demand (read+write) misses
120 system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses
121 system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses
122 system.cpu.icache.overall_misses::total 638 # number of overall misses
123 system.cpu.icache.ReadReq_miss_latency::cpu.inst 34233000 # number of ReadReq miss cycles
124 system.cpu.icache.ReadReq_miss_latency::total 34233000 # number of ReadReq miss cycles
125 system.cpu.icache.demand_miss_latency::cpu.inst 34233000 # number of demand (read+write) miss cycles
126 system.cpu.icache.demand_miss_latency::total 34233000 # number of demand (read+write) miss cycles
127 system.cpu.icache.overall_miss_latency::cpu.inst 34233000 # number of overall miss cycles
128 system.cpu.icache.overall_miss_latency::total 34233000 # number of overall miss cycles
129 system.cpu.icache.ReadReq_accesses::cpu.inst 1544565590 # number of ReadReq accesses(hits+misses)
130 system.cpu.icache.ReadReq_accesses::total 1544565590 # number of ReadReq accesses(hits+misses)
131 system.cpu.icache.demand_accesses::cpu.inst 1544565590 # number of demand (read+write) accesses
132 system.cpu.icache.demand_accesses::total 1544565590 # number of demand (read+write) accesses
133 system.cpu.icache.overall_accesses::cpu.inst 1544565590 # number of overall (read+write) accesses
134 system.cpu.icache.overall_accesses::total 1544565590 # number of overall (read+write) accesses
135 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses
136 system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses
137 system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses
138 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
139 system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
140 system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses
141 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53656.739812 # average ReadReq miss latency
142 system.cpu.icache.ReadReq_avg_miss_latency::total 53656.739812 # average ReadReq miss latency
143 system.cpu.icache.demand_avg_miss_latency::cpu.inst 53656.739812 # average overall miss latency
144 system.cpu.icache.demand_avg_miss_latency::total 53656.739812 # average overall miss latency
145 system.cpu.icache.overall_avg_miss_latency::cpu.inst 53656.739812 # average overall miss latency
146 system.cpu.icache.overall_avg_miss_latency::total 53656.739812 # average overall miss latency
147 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
148 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
149 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
150 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
151 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
152 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
153 system.cpu.icache.fast_writes 0 # number of fast writes performed
154 system.cpu.icache.cache_copies 0 # number of cache copies performed
155 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 638 # number of ReadReq MSHR misses
156 system.cpu.icache.ReadReq_mshr_misses::total 638 # number of ReadReq MSHR misses
157 system.cpu.icache.demand_mshr_misses::cpu.inst 638 # number of demand (read+write) MSHR misses
158 system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses
159 system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses
160 system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses
161 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32957000 # number of ReadReq MSHR miss cycles
162 system.cpu.icache.ReadReq_mshr_miss_latency::total 32957000 # number of ReadReq MSHR miss cycles
163 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32957000 # number of demand (read+write) MSHR miss cycles
164 system.cpu.icache.demand_mshr_miss_latency::total 32957000 # number of demand (read+write) MSHR miss cycles
165 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32957000 # number of overall MSHR miss cycles
166 system.cpu.icache.overall_mshr_miss_latency::total 32957000 # number of overall MSHR miss cycles
167 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
168 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
169 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
170 system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
171 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
172 system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses
173 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51656.739812 # average ReadReq mshr miss latency
174 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51656.739812 # average ReadReq mshr miss latency
175 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51656.739812 # average overall mshr miss latency
176 system.cpu.icache.demand_avg_mshr_miss_latency::total 51656.739812 # average overall mshr miss latency
177 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51656.739812 # average overall mshr miss latency
178 system.cpu.icache.overall_avg_mshr_miss_latency::total 51656.739812 # average overall mshr miss latency
179 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
180 system.cpu.l2cache.replacements 1926075 # number of replacements
181 system.cpu.l2cache.tagsinuse 30987.094489 # Cycle average of tags in use
182 system.cpu.l2cache.total_refs 8967572 # Total number of references to valid blocks.
183 system.cpu.l2cache.sampled_refs 1955843 # Sample count of references to valid blocks.
184 system.cpu.l2cache.avg_refs 4.585016 # Average number of references to valid blocks.
185 system.cpu.l2cache.warmup_cycle 154026636000 # Cycle when the warmup percentage was hit.
186 system.cpu.l2cache.occ_blocks::writebacks 15648.493745 # Average occupied blocks per requestor
187 system.cpu.l2cache.occ_blocks::cpu.inst 24.153175 # Average occupied blocks per requestor
188 system.cpu.l2cache.occ_blocks::cpu.data 15314.447570 # Average occupied blocks per requestor
189 system.cpu.l2cache.occ_percent::writebacks 0.477554 # Average percentage of cache occupancy
190 system.cpu.l2cache.occ_percent::cpu.inst 0.000737 # Average percentage of cache occupancy
191 system.cpu.l2cache.occ_percent::cpu.data 0.467360 # Average percentage of cache occupancy
192 system.cpu.l2cache.occ_percent::total 0.945651 # Average percentage of cache occupancy
193 system.cpu.l2cache.ReadReq_hits::cpu.inst 22 # number of ReadReq hits
194 system.cpu.l2cache.ReadReq_hits::cpu.data 6048805 # number of ReadReq hits
195 system.cpu.l2cache.ReadReq_hits::total 6048827 # number of ReadReq hits
196 system.cpu.l2cache.Writeback_hits::writebacks 3697418 # number of Writeback hits
197 system.cpu.l2cache.Writeback_hits::total 3697418 # number of Writeback hits
198 system.cpu.l2cache.ReadExReq_hits::cpu.data 1108273 # number of ReadExReq hits
199 system.cpu.l2cache.ReadExReq_hits::total 1108273 # number of ReadExReq hits
200 system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits
201 system.cpu.l2cache.demand_hits::cpu.data 7157078 # number of demand (read+write) hits
202 system.cpu.l2cache.demand_hits::total 7157100 # number of demand (read+write) hits
203 system.cpu.l2cache.overall_hits::cpu.inst 22 # number of overall hits
204 system.cpu.l2cache.overall_hits::cpu.data 7157078 # number of overall hits
205 system.cpu.l2cache.overall_hits::total 7157100 # number of overall hits
206 system.cpu.l2cache.ReadReq_misses::cpu.inst 616 # number of ReadReq misses
207 system.cpu.l2cache.ReadReq_misses::cpu.data 1177282 # number of ReadReq misses
208 system.cpu.l2cache.ReadReq_misses::total 1177898 # number of ReadReq misses
209 system.cpu.l2cache.ReadExReq_misses::cpu.data 780876 # number of ReadExReq misses
210 system.cpu.l2cache.ReadExReq_misses::total 780876 # number of ReadExReq misses
211 system.cpu.l2cache.demand_misses::cpu.inst 616 # number of demand (read+write) misses
212 system.cpu.l2cache.demand_misses::cpu.data 1958158 # number of demand (read+write) misses
213 system.cpu.l2cache.demand_misses::total 1958774 # number of demand (read+write) misses
214 system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses
215 system.cpu.l2cache.overall_misses::cpu.data 1958158 # number of overall misses
216 system.cpu.l2cache.overall_misses::total 1958774 # number of overall misses
217 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32099000 # number of ReadReq miss cycles
218 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61225555000 # number of ReadReq miss cycles
219 system.cpu.l2cache.ReadReq_miss_latency::total 61257654000 # number of ReadReq miss cycles
220 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40608829000 # number of ReadExReq miss cycles
221 system.cpu.l2cache.ReadExReq_miss_latency::total 40608829000 # number of ReadExReq miss cycles
222 system.cpu.l2cache.demand_miss_latency::cpu.inst 32099000 # number of demand (read+write) miss cycles
223 system.cpu.l2cache.demand_miss_latency::cpu.data 101834384000 # number of demand (read+write) miss cycles
224 system.cpu.l2cache.demand_miss_latency::total 101866483000 # number of demand (read+write) miss cycles
225 system.cpu.l2cache.overall_miss_latency::cpu.inst 32099000 # number of overall miss cycles
226 system.cpu.l2cache.overall_miss_latency::cpu.data 101834384000 # number of overall miss cycles
227 system.cpu.l2cache.overall_miss_latency::total 101866483000 # number of overall miss cycles
228 system.cpu.l2cache.ReadReq_accesses::cpu.inst 638 # number of ReadReq accesses(hits+misses)
229 system.cpu.l2cache.ReadReq_accesses::cpu.data 7226087 # number of ReadReq accesses(hits+misses)
230 system.cpu.l2cache.ReadReq_accesses::total 7226725 # number of ReadReq accesses(hits+misses)
231 system.cpu.l2cache.Writeback_accesses::writebacks 3697418 # number of Writeback accesses(hits+misses)
232 system.cpu.l2cache.Writeback_accesses::total 3697418 # number of Writeback accesses(hits+misses)
233 system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889149 # number of ReadExReq accesses(hits+misses)
234 system.cpu.l2cache.ReadExReq_accesses::total 1889149 # number of ReadExReq accesses(hits+misses)
235 system.cpu.l2cache.demand_accesses::cpu.inst 638 # number of demand (read+write) accesses
236 system.cpu.l2cache.demand_accesses::cpu.data 9115236 # number of demand (read+write) accesses
237 system.cpu.l2cache.demand_accesses::total 9115874 # number of demand (read+write) accesses
238 system.cpu.l2cache.overall_accesses::cpu.inst 638 # number of overall (read+write) accesses
239 system.cpu.l2cache.overall_accesses::cpu.data 9115236 # number of overall (read+write) accesses
240 system.cpu.l2cache.overall_accesses::total 9115874 # number of overall (read+write) accesses
241 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.965517 # miss rate for ReadReq accesses
242 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.162921 # miss rate for ReadReq accesses
243 system.cpu.l2cache.ReadReq_miss_rate::total 0.162992 # miss rate for ReadReq accesses
244 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413348 # miss rate for ReadExReq accesses
245 system.cpu.l2cache.ReadExReq_miss_rate::total 0.413348 # miss rate for ReadExReq accesses
246 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965517 # miss rate for demand accesses
247 system.cpu.l2cache.demand_miss_rate::cpu.data 0.214823 # miss rate for demand accesses
248 system.cpu.l2cache.demand_miss_rate::total 0.214875 # miss rate for demand accesses
249 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses
250 system.cpu.l2cache.overall_miss_rate::cpu.data 0.214823 # miss rate for overall accesses
251 system.cpu.l2cache.overall_miss_rate::total 0.214875 # miss rate for overall accesses
252 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52108.766234 # average ReadReq miss latency
253 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52005.853313 # average ReadReq miss latency
254 system.cpu.l2cache.ReadReq_avg_miss_latency::total 52005.907133 # average ReadReq miss latency
255 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52004.196569 # average ReadExReq miss latency
256 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52004.196569 # average ReadExReq miss latency
257 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52108.766234 # average overall miss latency
258 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52005.192635 # average overall miss latency
259 system.cpu.l2cache.demand_avg_miss_latency::total 52005.225207 # average overall miss latency
260 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52108.766234 # average overall miss latency
261 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52005.192635 # average overall miss latency
262 system.cpu.l2cache.overall_avg_miss_latency::total 52005.225207 # average overall miss latency
263 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
264 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
265 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
266 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
267 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
268 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
269 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
270 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
271 system.cpu.l2cache.writebacks::writebacks 1017198 # number of writebacks
272 system.cpu.l2cache.writebacks::total 1017198 # number of writebacks
273 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 616 # number of ReadReq MSHR misses
274 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177282 # number of ReadReq MSHR misses
275 system.cpu.l2cache.ReadReq_mshr_misses::total 1177898 # number of ReadReq MSHR misses
276 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 780876 # number of ReadExReq MSHR misses
277 system.cpu.l2cache.ReadExReq_mshr_misses::total 780876 # number of ReadExReq MSHR misses
278 system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses
279 system.cpu.l2cache.demand_mshr_misses::cpu.data 1958158 # number of demand (read+write) MSHR misses
280 system.cpu.l2cache.demand_mshr_misses::total 1958774 # number of demand (read+write) MSHR misses
281 system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses
282 system.cpu.l2cache.overall_mshr_misses::cpu.data 1958158 # number of overall MSHR misses
283 system.cpu.l2cache.overall_mshr_misses::total 1958774 # number of overall MSHR misses
284 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24707000 # number of ReadReq MSHR miss cycles
285 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47098171000 # number of ReadReq MSHR miss cycles
286 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47122878000 # number of ReadReq MSHR miss cycles
287 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31238317000 # number of ReadExReq MSHR miss cycles
288 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31238317000 # number of ReadExReq MSHR miss cycles
289 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24707000 # number of demand (read+write) MSHR miss cycles
290 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78336488000 # number of demand (read+write) MSHR miss cycles
291 system.cpu.l2cache.demand_mshr_miss_latency::total 78361195000 # number of demand (read+write) MSHR miss cycles
292 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24707000 # number of overall MSHR miss cycles
293 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78336488000 # number of overall MSHR miss cycles
294 system.cpu.l2cache.overall_mshr_miss_latency::total 78361195000 # number of overall MSHR miss cycles
295 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadReq accesses
296 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162921 # mshr miss rate for ReadReq accesses
297 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.162992 # mshr miss rate for ReadReq accesses
298 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413348 # mshr miss rate for ReadExReq accesses
299 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413348 # mshr miss rate for ReadExReq accesses
300 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for demand accesses
301 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214823 # mshr miss rate for demand accesses
302 system.cpu.l2cache.demand_mshr_miss_rate::total 0.214875 # mshr miss rate for demand accesses
303 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses
304 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214823 # mshr miss rate for overall accesses
305 system.cpu.l2cache.overall_mshr_miss_rate::total 0.214875 # mshr miss rate for overall accesses
306 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40108.766234 # average ReadReq mshr miss latency
307 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40005.853313 # average ReadReq mshr miss latency
308 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40005.907133 # average ReadReq mshr miss latency
309 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40004.196569 # average ReadExReq mshr miss latency
310 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40004.196569 # average ReadExReq mshr miss latency
311 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40108.766234 # average overall mshr miss latency
312 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40005.192635 # average overall mshr miss latency
313 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.225207 # average overall mshr miss latency
314 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40108.766234 # average overall mshr miss latency
315 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.192635 # average overall mshr miss latency
316 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.225207 # average overall mshr miss latency
317 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
318 system.cpu.dcache.replacements 9111140 # number of replacements
319 system.cpu.dcache.tagsinuse 4083.522356 # Cycle average of tags in use
320 system.cpu.dcache.total_refs 645855059 # Total number of references to valid blocks.
321 system.cpu.dcache.sampled_refs 9115236 # Sample count of references to valid blocks.
322 system.cpu.dcache.avg_refs 70.854453 # Average number of references to valid blocks.
323 system.cpu.dcache.warmup_cycle 25914401000 # Cycle when the warmup percentage was hit.
324 system.cpu.dcache.occ_blocks::cpu.data 4083.522356 # Average occupied blocks per requestor
325 system.cpu.dcache.occ_percent::cpu.data 0.996954 # Average percentage of cache occupancy
326 system.cpu.dcache.occ_percent::total 0.996954 # Average percentage of cache occupancy
327 system.cpu.dcache.ReadReq_hits::cpu.data 475158039 # number of ReadReq hits
328 system.cpu.dcache.ReadReq_hits::total 475158039 # number of ReadReq hits
329 system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits
330 system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits
331 system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits
332 system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits
333 system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
334 system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
335 system.cpu.dcache.demand_hits::cpu.data 645854937 # number of demand (read+write) hits
336 system.cpu.dcache.demand_hits::total 645854937 # number of demand (read+write) hits
337 system.cpu.dcache.overall_hits::cpu.data 645854937 # number of overall hits
338 system.cpu.dcache.overall_hits::total 645854937 # number of overall hits
339 system.cpu.dcache.ReadReq_misses::cpu.data 7226087 # number of ReadReq misses
340 system.cpu.dcache.ReadReq_misses::total 7226087 # number of ReadReq misses
341 system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses
342 system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses
343 system.cpu.dcache.demand_misses::cpu.data 9115236 # number of demand (read+write) misses
344 system.cpu.dcache.demand_misses::total 9115236 # number of demand (read+write) misses
345 system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses
346 system.cpu.dcache.overall_misses::total 9115236 # number of overall misses
347 system.cpu.dcache.ReadReq_miss_latency::cpu.data 143391866000 # number of ReadReq miss cycles
348 system.cpu.dcache.ReadReq_miss_latency::total 143391866000 # number of ReadReq miss cycles
349 system.cpu.dcache.WriteReq_miss_latency::cpu.data 57359006000 # number of WriteReq miss cycles
350 system.cpu.dcache.WriteReq_miss_latency::total 57359006000 # number of WriteReq miss cycles
351 system.cpu.dcache.demand_miss_latency::cpu.data 200750872000 # number of demand (read+write) miss cycles
352 system.cpu.dcache.demand_miss_latency::total 200750872000 # number of demand (read+write) miss cycles
353 system.cpu.dcache.overall_miss_latency::cpu.data 200750872000 # number of overall miss cycles
354 system.cpu.dcache.overall_miss_latency::total 200750872000 # number of overall miss cycles
355 system.cpu.dcache.ReadReq_accesses::cpu.data 482384126 # number of ReadReq accesses(hits+misses)
356 system.cpu.dcache.ReadReq_accesses::total 482384126 # number of ReadReq accesses(hits+misses)
357 system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
358 system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
359 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
360 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
361 system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
362 system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
363 system.cpu.dcache.demand_accesses::cpu.data 654970173 # number of demand (read+write) accesses
364 system.cpu.dcache.demand_accesses::total 654970173 # number of demand (read+write) accesses
365 system.cpu.dcache.overall_accesses::cpu.data 654970173 # number of overall (read+write) accesses
366 system.cpu.dcache.overall_accesses::total 654970173 # number of overall (read+write) accesses
367 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.014980 # miss rate for ReadReq accesses
368 system.cpu.dcache.ReadReq_miss_rate::total 0.014980 # miss rate for ReadReq accesses
369 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses
370 system.cpu.dcache.WriteReq_miss_rate::total 0.010946 # miss rate for WriteReq accesses
371 system.cpu.dcache.demand_miss_rate::cpu.data 0.013917 # miss rate for demand accesses
372 system.cpu.dcache.demand_miss_rate::total 0.013917 # miss rate for demand accesses
373 system.cpu.dcache.overall_miss_rate::cpu.data 0.013917 # miss rate for overall accesses
374 system.cpu.dcache.overall_miss_rate::total 0.013917 # miss rate for overall accesses
375 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19843.639580 # average ReadReq miss latency
376 system.cpu.dcache.ReadReq_avg_miss_latency::total 19843.639580 # average ReadReq miss latency
377 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.351514 # average WriteReq miss latency
378 system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.351514 # average WriteReq miss latency
379 system.cpu.dcache.demand_avg_miss_latency::cpu.data 22023.661483 # average overall miss latency
380 system.cpu.dcache.demand_avg_miss_latency::total 22023.661483 # average overall miss latency
381 system.cpu.dcache.overall_avg_miss_latency::cpu.data 22023.661483 # average overall miss latency
382 system.cpu.dcache.overall_avg_miss_latency::total 22023.661483 # average overall miss latency
383 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
384 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
385 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
386 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
387 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
388 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
389 system.cpu.dcache.fast_writes 0 # number of fast writes performed
390 system.cpu.dcache.cache_copies 0 # number of cache copies performed
391 system.cpu.dcache.writebacks::writebacks 3697418 # number of writebacks
392 system.cpu.dcache.writebacks::total 3697418 # number of writebacks
393 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226087 # number of ReadReq MSHR misses
394 system.cpu.dcache.ReadReq_mshr_misses::total 7226087 # number of ReadReq MSHR misses
395 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses
396 system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses
397 system.cpu.dcache.demand_mshr_misses::cpu.data 9115236 # number of demand (read+write) MSHR misses
398 system.cpu.dcache.demand_mshr_misses::total 9115236 # number of demand (read+write) MSHR misses
399 system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses
400 system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses
401 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128939692000 # number of ReadReq MSHR miss cycles
402 system.cpu.dcache.ReadReq_mshr_miss_latency::total 128939692000 # number of ReadReq MSHR miss cycles
403 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53580708000 # number of WriteReq MSHR miss cycles
404 system.cpu.dcache.WriteReq_mshr_miss_latency::total 53580708000 # number of WriteReq MSHR miss cycles
405 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182520400000 # number of demand (read+write) MSHR miss cycles
406 system.cpu.dcache.demand_mshr_miss_latency::total 182520400000 # number of demand (read+write) MSHR miss cycles
407 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182520400000 # number of overall MSHR miss cycles
408 system.cpu.dcache.overall_mshr_miss_latency::total 182520400000 # number of overall MSHR miss cycles
409 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.014980 # mshr miss rate for ReadReq accesses
410 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.014980 # mshr miss rate for ReadReq accesses
411 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses
412 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010946 # mshr miss rate for WriteReq accesses
413 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for demand accesses
414 system.cpu.dcache.demand_mshr_miss_rate::total 0.013917 # mshr miss rate for demand accesses
415 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for overall accesses
416 system.cpu.dcache.overall_mshr_miss_rate::total 0.013917 # mshr miss rate for overall accesses
417 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17843.639580 # average ReadReq mshr miss latency
418 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17843.639580 # average ReadReq mshr miss latency
419 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28362.351514 # average WriteReq mshr miss latency
420 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28362.351514 # average WriteReq mshr miss latency
421 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20023.661483 # average overall mshr miss latency
422 system.cpu.dcache.demand_avg_mshr_miss_latency::total 20023.661483 # average overall mshr miss latency
423 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20023.661483 # average overall mshr miss latency
424 system.cpu.dcache.overall_avg_mshr_miss_latency::total 20023.661483 # average overall mshr miss latency
425 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
427 ---------- End Simulation Statistics ----------
projects / gem5.git / blob