2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 2.391205 # Number of seconds simulated
4 sim_ticks 2391205115000 # Number of ticks simulated
5 final_tick 2391205115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 1176543 # Simulator instruction rate (inst/s)
8 host_op_rate 1313033 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 1828326739 # Simulator tick rate (ticks/s)
10 host_mem_usage 268744 # Number of bytes of host memory used
11 host_seconds 1307.87 # Real time elapsed on the host
12 sim_insts 1538759601 # Number of instructions simulated
13 sim_ops 1717270334 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 125322112 # Number of bytes read from this memory
18 system.physmem.bytes_read::total 125361536 # Number of bytes read from this memory
19 system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory
20 system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory
21 system.physmem.bytes_written::writebacks 65100672 # Number of bytes written to this memory
22 system.physmem.bytes_written::total 65100672 # Number of bytes written to this memory
23 system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory
24 system.physmem.num_reads::cpu.data 1958158 # Number of read requests responded to by this memory
25 system.physmem.num_reads::total 1958774 # Number of read requests responded to by this memory
26 system.physmem.num_writes::writebacks 1017198 # Number of write requests responded to by this memory
27 system.physmem.num_writes::total 1017198 # Number of write requests responded to by this memory
28 system.physmem.bw_read::cpu.inst 16487 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_read::cpu.data 52409604 # Total read bandwidth from this memory (bytes/s)
30 system.physmem.bw_read::total 52426091 # Total read bandwidth from this memory (bytes/s)
31 system.physmem.bw_inst_read::cpu.inst 16487 # Instruction read bandwidth from this memory (bytes/s)
32 system.physmem.bw_inst_read::total 16487 # Instruction read bandwidth from this memory (bytes/s)
33 system.physmem.bw_write::writebacks 27225047 # Write bandwidth from this memory (bytes/s)
34 system.physmem.bw_write::total 27225047 # Write bandwidth from this memory (bytes/s)
35 system.physmem.bw_total::writebacks 27225047 # Total bandwidth to/from this memory (bytes/s)
36 system.physmem.bw_total::cpu.inst 16487 # Total bandwidth to/from this memory (bytes/s)
37 system.physmem.bw_total::cpu.data 52409604 # Total bandwidth to/from this memory (bytes/s)
38 system.physmem.bw_total::total 79651138 # Total bandwidth to/from this memory (bytes/s)
39 system.membus.throughput 79651138 # Throughput (bytes/s)
40 system.membus.trans_dist::ReadReq 1177898 # Transaction distribution
41 system.membus.trans_dist::ReadResp 1177898 # Transaction distribution
42 system.membus.trans_dist::Writeback 1017198 # Transaction distribution
43 system.membus.trans_dist::ReadExReq 780876 # Transaction distribution
44 system.membus.trans_dist::ReadExResp 780876 # Transaction distribution
45 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4934746 # Packet count per connected master and slave (bytes)
46 system.membus.pkt_count::total 4934746 # Packet count per connected master and slave (bytes)
47 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190462208 # Cumulative packet size per connected master and slave (bytes)
48 system.membus.tot_pkt_size::total 190462208 # Cumulative packet size per connected master and slave (bytes)
49 system.membus.data_through_bus 190462208 # Total data (bytes)
50 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
51 system.membus.reqLayer0.occupancy 11113556000 # Layer occupancy (ticks)
52 system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
53 system.membus.respLayer1.occupancy 17628966000 # Layer occupancy (ticks)
54 system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
55 system.cpu_clk_domain.clock 500 # Clock period in ticks
56 system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
57 system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
58 system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
59 system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
60 system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
61 system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
62 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
63 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
64 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
65 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
66 system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
67 system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
68 system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
69 system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
70 system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
71 system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
72 system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
73 system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
74 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
75 system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
76 system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
77 system.cpu.dtb.inst_hits 0 # ITB inst hits
78 system.cpu.dtb.inst_misses 0 # ITB inst misses
79 system.cpu.dtb.read_hits 0 # DTB read hits
80 system.cpu.dtb.read_misses 0 # DTB read misses
81 system.cpu.dtb.write_hits 0 # DTB write hits
82 system.cpu.dtb.write_misses 0 # DTB write misses
83 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
84 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
85 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
86 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
87 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
88 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
89 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
90 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
91 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
92 system.cpu.dtb.read_accesses 0 # DTB read accesses
93 system.cpu.dtb.write_accesses 0 # DTB write accesses
94 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
95 system.cpu.dtb.hits 0 # DTB hits
96 system.cpu.dtb.misses 0 # DTB misses
97 system.cpu.dtb.accesses 0 # DTB accesses
98 system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
99 system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
100 system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
101 system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
102 system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
103 system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
104 system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
105 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
106 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
107 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
108 system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
109 system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
110 system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
111 system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
112 system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
113 system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
114 system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
115 system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
116 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
117 system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
118 system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
119 system.cpu.itb.inst_hits 0 # ITB inst hits
120 system.cpu.itb.inst_misses 0 # ITB inst misses
121 system.cpu.itb.read_hits 0 # DTB read hits
122 system.cpu.itb.read_misses 0 # DTB read misses
123 system.cpu.itb.write_hits 0 # DTB write hits
124 system.cpu.itb.write_misses 0 # DTB write misses
125 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
126 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
127 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
128 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
129 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
130 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
131 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
132 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
133 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
134 system.cpu.itb.read_accesses 0 # DTB read accesses
135 system.cpu.itb.write_accesses 0 # DTB write accesses
136 system.cpu.itb.inst_accesses 0 # ITB inst accesses
137 system.cpu.itb.hits 0 # DTB hits
138 system.cpu.itb.misses 0 # DTB misses
139 system.cpu.itb.accesses 0 # DTB accesses
140 system.cpu.workload.num_syscalls 46 # Number of system calls
141 system.cpu.numCycles 4782410230 # number of cpu cycles simulated
142 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
143 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
144 system.cpu.committedInsts 1538759601 # Number of instructions committed
145 system.cpu.committedOps 1717270334 # Number of ops (including micro ops) committed
146 system.cpu.num_int_alu_accesses 1536941842 # Number of integer alu accesses
147 system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses
148 system.cpu.num_func_calls 27330256 # number of times a function call or return occured
149 system.cpu.num_conditional_control_insts 177498328 # number of instructions that are conditional controls
150 system.cpu.num_int_insts 1536941842 # number of integer instructions
151 system.cpu.num_fp_insts 36 # number of float instructions
152 system.cpu.num_int_register_reads 9304895467 # number of times the integer registers were read
153 system.cpu.num_int_register_writes 1675132405 # number of times the integer registers were written
154 system.cpu.num_fp_register_reads 24 # number of times the floating registers were read
155 system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
156 system.cpu.num_mem_refs 660773815 # number of memory refs
157 system.cpu.num_load_insts 485926769 # Number of load instructions
158 system.cpu.num_store_insts 174847046 # Number of store instructions
159 system.cpu.num_idle_cycles 0 # Number of idle cycles
160 system.cpu.num_busy_cycles 4782410230 # Number of busy cycles
161 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
162 system.cpu.idle_fraction 0 # Percentage of idle cycles
163 system.cpu.icache.tags.replacements 7 # number of replacements
164 system.cpu.icache.tags.tagsinuse 514.976015 # Cycle average of tags in use
165 system.cpu.icache.tags.total_refs 1544564952 # Total number of references to valid blocks.
166 system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks.
167 system.cpu.icache.tags.avg_refs 2420948.200627 # Average number of references to valid blocks.
168 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
169 system.cpu.icache.tags.occ_blocks::cpu.inst 514.976015 # Average occupied blocks per requestor
170 system.cpu.icache.tags.occ_percent::cpu.inst 0.251453 # Average percentage of cache occupancy
171 system.cpu.icache.tags.occ_percent::total 0.251453 # Average percentage of cache occupancy
172 system.cpu.icache.tags.occ_task_id_blocks::1024 631 # Occupied blocks per task id
173 system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id
174 system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
175 system.cpu.icache.tags.age_task_id_blocks_1024::4 606 # Occupied blocks per task id
176 system.cpu.icache.tags.occ_task_id_percent::1024 0.308105 # Percentage of cache occupancy per task id
177 system.cpu.icache.tags.tag_accesses 3089131818 # Number of tag accesses
178 system.cpu.icache.tags.data_accesses 3089131818 # Number of data accesses
179 system.cpu.icache.ReadReq_hits::cpu.inst 1544564952 # number of ReadReq hits
180 system.cpu.icache.ReadReq_hits::total 1544564952 # number of ReadReq hits
181 system.cpu.icache.demand_hits::cpu.inst 1544564952 # number of demand (read+write) hits
182 system.cpu.icache.demand_hits::total 1544564952 # number of demand (read+write) hits
183 system.cpu.icache.overall_hits::cpu.inst 1544564952 # number of overall hits
184 system.cpu.icache.overall_hits::total 1544564952 # number of overall hits
185 system.cpu.icache.ReadReq_misses::cpu.inst 638 # number of ReadReq misses
186 system.cpu.icache.ReadReq_misses::total 638 # number of ReadReq misses
187 system.cpu.icache.demand_misses::cpu.inst 638 # number of demand (read+write) misses
188 system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses
189 system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses
190 system.cpu.icache.overall_misses::total 638 # number of overall misses
191 system.cpu.icache.ReadReq_miss_latency::cpu.inst 34233000 # number of ReadReq miss cycles
192 system.cpu.icache.ReadReq_miss_latency::total 34233000 # number of ReadReq miss cycles
193 system.cpu.icache.demand_miss_latency::cpu.inst 34233000 # number of demand (read+write) miss cycles
194 system.cpu.icache.demand_miss_latency::total 34233000 # number of demand (read+write) miss cycles
195 system.cpu.icache.overall_miss_latency::cpu.inst 34233000 # number of overall miss cycles
196 system.cpu.icache.overall_miss_latency::total 34233000 # number of overall miss cycles
197 system.cpu.icache.ReadReq_accesses::cpu.inst 1544565590 # number of ReadReq accesses(hits+misses)
198 system.cpu.icache.ReadReq_accesses::total 1544565590 # number of ReadReq accesses(hits+misses)
199 system.cpu.icache.demand_accesses::cpu.inst 1544565590 # number of demand (read+write) accesses
200 system.cpu.icache.demand_accesses::total 1544565590 # number of demand (read+write) accesses
201 system.cpu.icache.overall_accesses::cpu.inst 1544565590 # number of overall (read+write) accesses
202 system.cpu.icache.overall_accesses::total 1544565590 # number of overall (read+write) accesses
203 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses
204 system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses
205 system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses
206 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
207 system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
208 system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses
209 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53656.739812 # average ReadReq miss latency
210 system.cpu.icache.ReadReq_avg_miss_latency::total 53656.739812 # average ReadReq miss latency
211 system.cpu.icache.demand_avg_miss_latency::cpu.inst 53656.739812 # average overall miss latency
212 system.cpu.icache.demand_avg_miss_latency::total 53656.739812 # average overall miss latency
213 system.cpu.icache.overall_avg_miss_latency::cpu.inst 53656.739812 # average overall miss latency
214 system.cpu.icache.overall_avg_miss_latency::total 53656.739812 # average overall miss latency
215 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
216 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
217 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
218 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
219 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
220 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
221 system.cpu.icache.fast_writes 0 # number of fast writes performed
222 system.cpu.icache.cache_copies 0 # number of cache copies performed
223 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 638 # number of ReadReq MSHR misses
224 system.cpu.icache.ReadReq_mshr_misses::total 638 # number of ReadReq MSHR misses
225 system.cpu.icache.demand_mshr_misses::cpu.inst 638 # number of demand (read+write) MSHR misses
226 system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses
227 system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses
228 system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses
229 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32957000 # number of ReadReq MSHR miss cycles
230 system.cpu.icache.ReadReq_mshr_miss_latency::total 32957000 # number of ReadReq MSHR miss cycles
231 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32957000 # number of demand (read+write) MSHR miss cycles
232 system.cpu.icache.demand_mshr_miss_latency::total 32957000 # number of demand (read+write) MSHR miss cycles
233 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32957000 # number of overall MSHR miss cycles
234 system.cpu.icache.overall_mshr_miss_latency::total 32957000 # number of overall MSHR miss cycles
235 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
236 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
237 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
238 system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
239 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
240 system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses
241 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51656.739812 # average ReadReq mshr miss latency
242 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51656.739812 # average ReadReq mshr miss latency
243 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51656.739812 # average overall mshr miss latency
244 system.cpu.icache.demand_avg_mshr_miss_latency::total 51656.739812 # average overall mshr miss latency
245 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51656.739812 # average overall mshr miss latency
246 system.cpu.icache.overall_avg_mshr_miss_latency::total 51656.739812 # average overall mshr miss latency
247 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
248 system.cpu.l2cache.tags.replacements 1926075 # number of replacements
249 system.cpu.l2cache.tags.tagsinuse 30987.094489 # Cycle average of tags in use
250 system.cpu.l2cache.tags.total_refs 8967572 # Total number of references to valid blocks.
251 system.cpu.l2cache.tags.sampled_refs 1955843 # Sample count of references to valid blocks.
252 system.cpu.l2cache.tags.avg_refs 4.585016 # Average number of references to valid blocks.
253 system.cpu.l2cache.tags.warmup_cycle 154026636000 # Cycle when the warmup percentage was hit.
254 system.cpu.l2cache.tags.occ_blocks::writebacks 15648.493745 # Average occupied blocks per requestor
255 system.cpu.l2cache.tags.occ_blocks::cpu.inst 24.153175 # Average occupied blocks per requestor
256 system.cpu.l2cache.tags.occ_blocks::cpu.data 15314.447570 # Average occupied blocks per requestor
257 system.cpu.l2cache.tags.occ_percent::writebacks 0.477554 # Average percentage of cache occupancy
258 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000737 # Average percentage of cache occupancy
259 system.cpu.l2cache.tags.occ_percent::cpu.data 0.467360 # Average percentage of cache occupancy
260 system.cpu.l2cache.tags.occ_percent::total 0.945651 # Average percentage of cache occupancy
261 system.cpu.l2cache.tags.occ_task_id_blocks::1024 29768 # Occupied blocks per task id
262 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id
263 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id
264 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1082 # Occupied blocks per task id
265 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1693 # Occupied blocks per task id
266 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26880 # Occupied blocks per task id
267 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908447 # Percentage of cache occupancy per task id
268 system.cpu.l2cache.tags.tag_accesses 106351328 # Number of tag accesses
269 system.cpu.l2cache.tags.data_accesses 106351328 # Number of data accesses
270 system.cpu.l2cache.ReadReq_hits::cpu.inst 22 # number of ReadReq hits
271 system.cpu.l2cache.ReadReq_hits::cpu.data 6048805 # number of ReadReq hits
272 system.cpu.l2cache.ReadReq_hits::total 6048827 # number of ReadReq hits
273 system.cpu.l2cache.Writeback_hits::writebacks 3697418 # number of Writeback hits
274 system.cpu.l2cache.Writeback_hits::total 3697418 # number of Writeback hits
275 system.cpu.l2cache.ReadExReq_hits::cpu.data 1108273 # number of ReadExReq hits
276 system.cpu.l2cache.ReadExReq_hits::total 1108273 # number of ReadExReq hits
277 system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits
278 system.cpu.l2cache.demand_hits::cpu.data 7157078 # number of demand (read+write) hits
279 system.cpu.l2cache.demand_hits::total 7157100 # number of demand (read+write) hits
280 system.cpu.l2cache.overall_hits::cpu.inst 22 # number of overall hits
281 system.cpu.l2cache.overall_hits::cpu.data 7157078 # number of overall hits
282 system.cpu.l2cache.overall_hits::total 7157100 # number of overall hits
283 system.cpu.l2cache.ReadReq_misses::cpu.inst 616 # number of ReadReq misses
284 system.cpu.l2cache.ReadReq_misses::cpu.data 1177282 # number of ReadReq misses
285 system.cpu.l2cache.ReadReq_misses::total 1177898 # number of ReadReq misses
286 system.cpu.l2cache.ReadExReq_misses::cpu.data 780876 # number of ReadExReq misses
287 system.cpu.l2cache.ReadExReq_misses::total 780876 # number of ReadExReq misses
288 system.cpu.l2cache.demand_misses::cpu.inst 616 # number of demand (read+write) misses
289 system.cpu.l2cache.demand_misses::cpu.data 1958158 # number of demand (read+write) misses
290 system.cpu.l2cache.demand_misses::total 1958774 # number of demand (read+write) misses
291 system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses
292 system.cpu.l2cache.overall_misses::cpu.data 1958158 # number of overall misses
293 system.cpu.l2cache.overall_misses::total 1958774 # number of overall misses
294 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32099000 # number of ReadReq miss cycles
295 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61225555000 # number of ReadReq miss cycles
296 system.cpu.l2cache.ReadReq_miss_latency::total 61257654000 # number of ReadReq miss cycles
297 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40608829000 # number of ReadExReq miss cycles
298 system.cpu.l2cache.ReadExReq_miss_latency::total 40608829000 # number of ReadExReq miss cycles
299 system.cpu.l2cache.demand_miss_latency::cpu.inst 32099000 # number of demand (read+write) miss cycles
300 system.cpu.l2cache.demand_miss_latency::cpu.data 101834384000 # number of demand (read+write) miss cycles
301 system.cpu.l2cache.demand_miss_latency::total 101866483000 # number of demand (read+write) miss cycles
302 system.cpu.l2cache.overall_miss_latency::cpu.inst 32099000 # number of overall miss cycles
303 system.cpu.l2cache.overall_miss_latency::cpu.data 101834384000 # number of overall miss cycles
304 system.cpu.l2cache.overall_miss_latency::total 101866483000 # number of overall miss cycles
305 system.cpu.l2cache.ReadReq_accesses::cpu.inst 638 # number of ReadReq accesses(hits+misses)
306 system.cpu.l2cache.ReadReq_accesses::cpu.data 7226087 # number of ReadReq accesses(hits+misses)
307 system.cpu.l2cache.ReadReq_accesses::total 7226725 # number of ReadReq accesses(hits+misses)
308 system.cpu.l2cache.Writeback_accesses::writebacks 3697418 # number of Writeback accesses(hits+misses)
309 system.cpu.l2cache.Writeback_accesses::total 3697418 # number of Writeback accesses(hits+misses)
310 system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889149 # number of ReadExReq accesses(hits+misses)
311 system.cpu.l2cache.ReadExReq_accesses::total 1889149 # number of ReadExReq accesses(hits+misses)
312 system.cpu.l2cache.demand_accesses::cpu.inst 638 # number of demand (read+write) accesses
313 system.cpu.l2cache.demand_accesses::cpu.data 9115236 # number of demand (read+write) accesses
314 system.cpu.l2cache.demand_accesses::total 9115874 # number of demand (read+write) accesses
315 system.cpu.l2cache.overall_accesses::cpu.inst 638 # number of overall (read+write) accesses
316 system.cpu.l2cache.overall_accesses::cpu.data 9115236 # number of overall (read+write) accesses
317 system.cpu.l2cache.overall_accesses::total 9115874 # number of overall (read+write) accesses
318 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.965517 # miss rate for ReadReq accesses
319 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.162921 # miss rate for ReadReq accesses
320 system.cpu.l2cache.ReadReq_miss_rate::total 0.162992 # miss rate for ReadReq accesses
321 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413348 # miss rate for ReadExReq accesses
322 system.cpu.l2cache.ReadExReq_miss_rate::total 0.413348 # miss rate for ReadExReq accesses
323 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965517 # miss rate for demand accesses
324 system.cpu.l2cache.demand_miss_rate::cpu.data 0.214823 # miss rate for demand accesses
325 system.cpu.l2cache.demand_miss_rate::total 0.214875 # miss rate for demand accesses
326 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses
327 system.cpu.l2cache.overall_miss_rate::cpu.data 0.214823 # miss rate for overall accesses
328 system.cpu.l2cache.overall_miss_rate::total 0.214875 # miss rate for overall accesses
329 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52108.766234 # average ReadReq miss latency
330 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52005.853313 # average ReadReq miss latency
331 system.cpu.l2cache.ReadReq_avg_miss_latency::total 52005.907133 # average ReadReq miss latency
332 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52004.196569 # average ReadExReq miss latency
333 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52004.196569 # average ReadExReq miss latency
334 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52108.766234 # average overall miss latency
335 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52005.192635 # average overall miss latency
336 system.cpu.l2cache.demand_avg_miss_latency::total 52005.225207 # average overall miss latency
337 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52108.766234 # average overall miss latency
338 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52005.192635 # average overall miss latency
339 system.cpu.l2cache.overall_avg_miss_latency::total 52005.225207 # average overall miss latency
340 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
341 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
342 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
343 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
344 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
345 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
346 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
347 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
348 system.cpu.l2cache.writebacks::writebacks 1017198 # number of writebacks
349 system.cpu.l2cache.writebacks::total 1017198 # number of writebacks
350 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 616 # number of ReadReq MSHR misses
351 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177282 # number of ReadReq MSHR misses
352 system.cpu.l2cache.ReadReq_mshr_misses::total 1177898 # number of ReadReq MSHR misses
353 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 780876 # number of ReadExReq MSHR misses
354 system.cpu.l2cache.ReadExReq_mshr_misses::total 780876 # number of ReadExReq MSHR misses
355 system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses
356 system.cpu.l2cache.demand_mshr_misses::cpu.data 1958158 # number of demand (read+write) MSHR misses
357 system.cpu.l2cache.demand_mshr_misses::total 1958774 # number of demand (read+write) MSHR misses
358 system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses
359 system.cpu.l2cache.overall_mshr_misses::cpu.data 1958158 # number of overall MSHR misses
360 system.cpu.l2cache.overall_mshr_misses::total 1958774 # number of overall MSHR misses
361 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24707000 # number of ReadReq MSHR miss cycles
362 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47098171000 # number of ReadReq MSHR miss cycles
363 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47122878000 # number of ReadReq MSHR miss cycles
364 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31238317000 # number of ReadExReq MSHR miss cycles
365 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31238317000 # number of ReadExReq MSHR miss cycles
366 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24707000 # number of demand (read+write) MSHR miss cycles
367 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78336488000 # number of demand (read+write) MSHR miss cycles
368 system.cpu.l2cache.demand_mshr_miss_latency::total 78361195000 # number of demand (read+write) MSHR miss cycles
369 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24707000 # number of overall MSHR miss cycles
370 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78336488000 # number of overall MSHR miss cycles
371 system.cpu.l2cache.overall_mshr_miss_latency::total 78361195000 # number of overall MSHR miss cycles
372 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadReq accesses
373 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162921 # mshr miss rate for ReadReq accesses
374 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.162992 # mshr miss rate for ReadReq accesses
375 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413348 # mshr miss rate for ReadExReq accesses
376 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413348 # mshr miss rate for ReadExReq accesses
377 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for demand accesses
378 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214823 # mshr miss rate for demand accesses
379 system.cpu.l2cache.demand_mshr_miss_rate::total 0.214875 # mshr miss rate for demand accesses
380 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses
381 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214823 # mshr miss rate for overall accesses
382 system.cpu.l2cache.overall_mshr_miss_rate::total 0.214875 # mshr miss rate for overall accesses
383 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40108.766234 # average ReadReq mshr miss latency
384 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40005.853313 # average ReadReq mshr miss latency
385 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40005.907133 # average ReadReq mshr miss latency
386 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40004.196569 # average ReadExReq mshr miss latency
387 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40004.196569 # average ReadExReq mshr miss latency
388 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40108.766234 # average overall mshr miss latency
389 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40005.192635 # average overall mshr miss latency
390 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.225207 # average overall mshr miss latency
391 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40108.766234 # average overall mshr miss latency
392 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.192635 # average overall mshr miss latency
393 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.225207 # average overall mshr miss latency
394 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
395 system.cpu.dcache.tags.replacements 9111140 # number of replacements
396 system.cpu.dcache.tags.tagsinuse 4083.522356 # Cycle average of tags in use
397 system.cpu.dcache.tags.total_refs 645855059 # Total number of references to valid blocks.
398 system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks.
399 system.cpu.dcache.tags.avg_refs 70.854453 # Average number of references to valid blocks.
400 system.cpu.dcache.tags.warmup_cycle 25914401000 # Cycle when the warmup percentage was hit.
401 system.cpu.dcache.tags.occ_blocks::cpu.data 4083.522356 # Average occupied blocks per requestor
402 system.cpu.dcache.tags.occ_percent::cpu.data 0.996954 # Average percentage of cache occupancy
403 system.cpu.dcache.tags.occ_percent::total 0.996954 # Average percentage of cache occupancy
404 system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
405 system.cpu.dcache.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id
406 system.cpu.dcache.tags.age_task_id_blocks_1024::1 1214 # Occupied blocks per task id
407 system.cpu.dcache.tags.age_task_id_blocks_1024::2 2578 # Occupied blocks per task id
408 system.cpu.dcache.tags.age_task_id_blocks_1024::3 146 # Occupied blocks per task id
409 system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
410 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
411 system.cpu.dcache.tags.tag_accesses 1319055826 # Number of tag accesses
412 system.cpu.dcache.tags.data_accesses 1319055826 # Number of data accesses
413 system.cpu.dcache.ReadReq_hits::cpu.data 475158039 # number of ReadReq hits
414 system.cpu.dcache.ReadReq_hits::total 475158039 # number of ReadReq hits
415 system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits
416 system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits
417 system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits
418 system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits
419 system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
420 system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
421 system.cpu.dcache.demand_hits::cpu.data 645854937 # number of demand (read+write) hits
422 system.cpu.dcache.demand_hits::total 645854937 # number of demand (read+write) hits
423 system.cpu.dcache.overall_hits::cpu.data 645854937 # number of overall hits
424 system.cpu.dcache.overall_hits::total 645854937 # number of overall hits
425 system.cpu.dcache.ReadReq_misses::cpu.data 7226087 # number of ReadReq misses
426 system.cpu.dcache.ReadReq_misses::total 7226087 # number of ReadReq misses
427 system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses
428 system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses
429 system.cpu.dcache.demand_misses::cpu.data 9115236 # number of demand (read+write) misses
430 system.cpu.dcache.demand_misses::total 9115236 # number of demand (read+write) misses
431 system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses
432 system.cpu.dcache.overall_misses::total 9115236 # number of overall misses
433 system.cpu.dcache.ReadReq_miss_latency::cpu.data 143391866000 # number of ReadReq miss cycles
434 system.cpu.dcache.ReadReq_miss_latency::total 143391866000 # number of ReadReq miss cycles
435 system.cpu.dcache.WriteReq_miss_latency::cpu.data 57359006000 # number of WriteReq miss cycles
436 system.cpu.dcache.WriteReq_miss_latency::total 57359006000 # number of WriteReq miss cycles
437 system.cpu.dcache.demand_miss_latency::cpu.data 200750872000 # number of demand (read+write) miss cycles
438 system.cpu.dcache.demand_miss_latency::total 200750872000 # number of demand (read+write) miss cycles
439 system.cpu.dcache.overall_miss_latency::cpu.data 200750872000 # number of overall miss cycles
440 system.cpu.dcache.overall_miss_latency::total 200750872000 # number of overall miss cycles
441 system.cpu.dcache.ReadReq_accesses::cpu.data 482384126 # number of ReadReq accesses(hits+misses)
442 system.cpu.dcache.ReadReq_accesses::total 482384126 # number of ReadReq accesses(hits+misses)
443 system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
444 system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
445 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
446 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
447 system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
448 system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
449 system.cpu.dcache.demand_accesses::cpu.data 654970173 # number of demand (read+write) accesses
450 system.cpu.dcache.demand_accesses::total 654970173 # number of demand (read+write) accesses
451 system.cpu.dcache.overall_accesses::cpu.data 654970173 # number of overall (read+write) accesses
452 system.cpu.dcache.overall_accesses::total 654970173 # number of overall (read+write) accesses
453 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.014980 # miss rate for ReadReq accesses
454 system.cpu.dcache.ReadReq_miss_rate::total 0.014980 # miss rate for ReadReq accesses
455 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses
456 system.cpu.dcache.WriteReq_miss_rate::total 0.010946 # miss rate for WriteReq accesses
457 system.cpu.dcache.demand_miss_rate::cpu.data 0.013917 # miss rate for demand accesses
458 system.cpu.dcache.demand_miss_rate::total 0.013917 # miss rate for demand accesses
459 system.cpu.dcache.overall_miss_rate::cpu.data 0.013917 # miss rate for overall accesses
460 system.cpu.dcache.overall_miss_rate::total 0.013917 # miss rate for overall accesses
461 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19843.639580 # average ReadReq miss latency
462 system.cpu.dcache.ReadReq_avg_miss_latency::total 19843.639580 # average ReadReq miss latency
463 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.351514 # average WriteReq miss latency
464 system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.351514 # average WriteReq miss latency
465 system.cpu.dcache.demand_avg_miss_latency::cpu.data 22023.661483 # average overall miss latency
466 system.cpu.dcache.demand_avg_miss_latency::total 22023.661483 # average overall miss latency
467 system.cpu.dcache.overall_avg_miss_latency::cpu.data 22023.661483 # average overall miss latency
468 system.cpu.dcache.overall_avg_miss_latency::total 22023.661483 # average overall miss latency
469 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
470 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
471 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
472 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
473 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
474 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
475 system.cpu.dcache.fast_writes 0 # number of fast writes performed
476 system.cpu.dcache.cache_copies 0 # number of cache copies performed
477 system.cpu.dcache.writebacks::writebacks 3697418 # number of writebacks
478 system.cpu.dcache.writebacks::total 3697418 # number of writebacks
479 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226087 # number of ReadReq MSHR misses
480 system.cpu.dcache.ReadReq_mshr_misses::total 7226087 # number of ReadReq MSHR misses
481 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses
482 system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses
483 system.cpu.dcache.demand_mshr_misses::cpu.data 9115236 # number of demand (read+write) MSHR misses
484 system.cpu.dcache.demand_mshr_misses::total 9115236 # number of demand (read+write) MSHR misses
485 system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses
486 system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses
487 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128939692000 # number of ReadReq MSHR miss cycles
488 system.cpu.dcache.ReadReq_mshr_miss_latency::total 128939692000 # number of ReadReq MSHR miss cycles
489 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53580708000 # number of WriteReq MSHR miss cycles
490 system.cpu.dcache.WriteReq_mshr_miss_latency::total 53580708000 # number of WriteReq MSHR miss cycles
491 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182520400000 # number of demand (read+write) MSHR miss cycles
492 system.cpu.dcache.demand_mshr_miss_latency::total 182520400000 # number of demand (read+write) MSHR miss cycles
493 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182520400000 # number of overall MSHR miss cycles
494 system.cpu.dcache.overall_mshr_miss_latency::total 182520400000 # number of overall MSHR miss cycles
495 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.014980 # mshr miss rate for ReadReq accesses
496 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.014980 # mshr miss rate for ReadReq accesses
497 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses
498 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010946 # mshr miss rate for WriteReq accesses
499 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for demand accesses
500 system.cpu.dcache.demand_mshr_miss_rate::total 0.013917 # mshr miss rate for demand accesses
501 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for overall accesses
502 system.cpu.dcache.overall_mshr_miss_rate::total 0.013917 # mshr miss rate for overall accesses
503 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17843.639580 # average ReadReq mshr miss latency
504 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17843.639580 # average ReadReq mshr miss latency
505 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28362.351514 # average WriteReq mshr miss latency
506 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28362.351514 # average WriteReq mshr miss latency
507 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20023.661483 # average overall mshr miss latency
508 system.cpu.dcache.demand_avg_mshr_miss_latency::total 20023.661483 # average overall mshr miss latency
509 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20023.661483 # average overall mshr miss latency
510 system.cpu.dcache.overall_avg_mshr_miss_latency::total 20023.661483 # average overall mshr miss latency
511 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
512 system.cpu.toL2Bus.throughput 342944519 # Throughput (bytes/s)
513 system.cpu.toL2Bus.trans_dist::ReadReq 7226725 # Transaction distribution
514 system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution
515 system.cpu.toL2Bus.trans_dist::Writeback 3697418 # Transaction distribution
516 system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution
517 system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution
518 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1276 # Packet count per connected master and slave (bytes)
519 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21927890 # Packet count per connected master and slave (bytes)
520 system.cpu.toL2Bus.pkt_count::total 21929166 # Packet count per connected master and slave (bytes)
521 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes)
522 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820009856 # Cumulative packet size per connected master and slave (bytes)
523 system.cpu.toL2Bus.tot_pkt_size::total 820050688 # Cumulative packet size per connected master and slave (bytes)
524 system.cpu.toL2Bus.data_through_bus 820050688 # Total data (bytes)
525 system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
526 system.cpu.toL2Bus.reqLayer0.occupancy 10104064000 # Layer occupancy (ticks)
527 system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%)
528 system.cpu.toL2Bus.respLayer0.occupancy 957000 # Layer occupancy (ticks)
529 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
530 system.cpu.toL2Bus.respLayer1.occupancy 13672854000 # Layer occupancy (ticks)
531 system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%)
533 ---------- End Simulation Statistics ----------
projects / gem5.git / blob