2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 2.431420 # Number of seconds simulated
4 sim_ticks 2431419954000 # Number of ticks simulated
5 final_tick 2431419954000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 1031283 # Simulator instruction rate (inst/s)
8 host_op_rate 1150922 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 1629547552 # Simulator tick rate (ticks/s)
10 host_mem_usage 230584 # Number of bytes of host memory used
11 host_seconds 1492.08 # Real time elapsed on the host
12 sim_insts 1538759609 # Number of instructions simulated
13 sim_ops 1717270343 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 172726592 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 172766016 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory
19 system.physmem.bytes_written::writebacks 75006720 # Number of bytes written to this memory
20 system.physmem.bytes_written::total 75006720 # Number of bytes written to this memory
21 system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory
22 system.physmem.num_reads::cpu.data 2698853 # Number of read requests responded to by this memory
23 system.physmem.num_reads::total 2699469 # Number of read requests responded to by this memory
24 system.physmem.num_writes::writebacks 1171980 # Number of write requests responded to by this memory
25 system.physmem.num_writes::total 1171980 # Number of write requests responded to by this memory
26 system.physmem.bw_read::cpu.inst 16214 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_read::cpu.data 71039391 # Total read bandwidth from this memory (bytes/s)
28 system.physmem.bw_read::total 71055605 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_inst_read::cpu.inst 16214 # Instruction read bandwidth from this memory (bytes/s)
30 system.physmem.bw_inst_read::total 16214 # Instruction read bandwidth from this memory (bytes/s)
31 system.physmem.bw_write::writebacks 30848937 # Write bandwidth from this memory (bytes/s)
32 system.physmem.bw_write::total 30848937 # Write bandwidth from this memory (bytes/s)
33 system.physmem.bw_total::writebacks 30848937 # Total bandwidth to/from this memory (bytes/s)
34 system.physmem.bw_total::cpu.inst 16214 # Total bandwidth to/from this memory (bytes/s)
35 system.physmem.bw_total::cpu.data 71039391 # Total bandwidth to/from this memory (bytes/s)
36 system.physmem.bw_total::total 101904542 # Total bandwidth to/from this memory (bytes/s)
37 system.cpu.dtb.inst_hits 0 # ITB inst hits
38 system.cpu.dtb.inst_misses 0 # ITB inst misses
39 system.cpu.dtb.read_hits 0 # DTB read hits
40 system.cpu.dtb.read_misses 0 # DTB read misses
41 system.cpu.dtb.write_hits 0 # DTB write hits
42 system.cpu.dtb.write_misses 0 # DTB write misses
43 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
44 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
45 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
46 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
47 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
48 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
49 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
50 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
51 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
52 system.cpu.dtb.read_accesses 0 # DTB read accesses
53 system.cpu.dtb.write_accesses 0 # DTB write accesses
54 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
55 system.cpu.dtb.hits 0 # DTB hits
56 system.cpu.dtb.misses 0 # DTB misses
57 system.cpu.dtb.accesses 0 # DTB accesses
58 system.cpu.itb.inst_hits 0 # ITB inst hits
59 system.cpu.itb.inst_misses 0 # ITB inst misses
60 system.cpu.itb.read_hits 0 # DTB read hits
61 system.cpu.itb.read_misses 0 # DTB read misses
62 system.cpu.itb.write_hits 0 # DTB write hits
63 system.cpu.itb.write_misses 0 # DTB write misses
64 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
65 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
66 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
67 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
68 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
69 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
70 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
71 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
72 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
73 system.cpu.itb.read_accesses 0 # DTB read accesses
74 system.cpu.itb.write_accesses 0 # DTB write accesses
75 system.cpu.itb.inst_accesses 0 # ITB inst accesses
76 system.cpu.itb.hits 0 # DTB hits
77 system.cpu.itb.misses 0 # DTB misses
78 system.cpu.itb.accesses 0 # DTB accesses
79 system.cpu.workload.num_syscalls 46 # Number of system calls
80 system.cpu.numCycles 4862839908 # number of cpu cycles simulated
81 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
82 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
83 system.cpu.committedInsts 1538759609 # Number of instructions committed
84 system.cpu.committedOps 1717270343 # Number of ops (including micro ops) committed
85 system.cpu.num_int_alu_accesses 1536941850 # Number of integer alu accesses
86 system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses
87 system.cpu.num_func_calls 27330134 # number of times a function call or return occured
88 system.cpu.num_conditional_control_insts 177498328 # number of instructions that are conditional controls
89 system.cpu.num_int_insts 1536941850 # number of integer instructions
90 system.cpu.num_fp_insts 36 # number of float instructions
91 system.cpu.num_int_register_reads 9304894713 # number of times the integer registers were read
92 system.cpu.num_int_register_writes 1675132418 # number of times the integer registers were written
93 system.cpu.num_fp_register_reads 24 # number of times the floating registers were read
94 system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
95 system.cpu.num_mem_refs 660773816 # number of memory refs
96 system.cpu.num_load_insts 485926770 # Number of load instructions
97 system.cpu.num_store_insts 174847046 # Number of store instructions
98 system.cpu.num_idle_cycles 0 # Number of idle cycles
99 system.cpu.num_busy_cycles 4862839908 # Number of busy cycles
100 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
101 system.cpu.idle_fraction 0 # Percentage of idle cycles
102 system.cpu.icache.replacements 7 # number of replacements
103 system.cpu.icache.tagsinuse 514.872896 # Cycle average of tags in use
104 system.cpu.icache.total_refs 1544564961 # Total number of references to valid blocks.
105 system.cpu.icache.sampled_refs 638 # Sample count of references to valid blocks.
106 system.cpu.icache.avg_refs 2420948.214734 # Average number of references to valid blocks.
107 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
108 system.cpu.icache.occ_blocks::cpu.inst 514.872896 # Average occupied blocks per requestor
109 system.cpu.icache.occ_percent::cpu.inst 0.251403 # Average percentage of cache occupancy
110 system.cpu.icache.occ_percent::total 0.251403 # Average percentage of cache occupancy
111 system.cpu.icache.ReadReq_hits::cpu.inst 1544564961 # number of ReadReq hits
112 system.cpu.icache.ReadReq_hits::total 1544564961 # number of ReadReq hits
113 system.cpu.icache.demand_hits::cpu.inst 1544564961 # number of demand (read+write) hits
114 system.cpu.icache.demand_hits::total 1544564961 # number of demand (read+write) hits
115 system.cpu.icache.overall_hits::cpu.inst 1544564961 # number of overall hits
116 system.cpu.icache.overall_hits::total 1544564961 # number of overall hits
117 system.cpu.icache.ReadReq_misses::cpu.inst 638 # number of ReadReq misses
118 system.cpu.icache.ReadReq_misses::total 638 # number of ReadReq misses
119 system.cpu.icache.demand_misses::cpu.inst 638 # number of demand (read+write) misses
120 system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses
121 system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses
122 system.cpu.icache.overall_misses::total 638 # number of overall misses
123 system.cpu.icache.ReadReq_miss_latency::cpu.inst 34804000 # number of ReadReq miss cycles
124 system.cpu.icache.ReadReq_miss_latency::total 34804000 # number of ReadReq miss cycles
125 system.cpu.icache.demand_miss_latency::cpu.inst 34804000 # number of demand (read+write) miss cycles
126 system.cpu.icache.demand_miss_latency::total 34804000 # number of demand (read+write) miss cycles
127 system.cpu.icache.overall_miss_latency::cpu.inst 34804000 # number of overall miss cycles
128 system.cpu.icache.overall_miss_latency::total 34804000 # number of overall miss cycles
129 system.cpu.icache.ReadReq_accesses::cpu.inst 1544565599 # number of ReadReq accesses(hits+misses)
130 system.cpu.icache.ReadReq_accesses::total 1544565599 # number of ReadReq accesses(hits+misses)
131 system.cpu.icache.demand_accesses::cpu.inst 1544565599 # number of demand (read+write) accesses
132 system.cpu.icache.demand_accesses::total 1544565599 # number of demand (read+write) accesses
133 system.cpu.icache.overall_accesses::cpu.inst 1544565599 # number of overall (read+write) accesses
134 system.cpu.icache.overall_accesses::total 1544565599 # number of overall (read+write) accesses
135 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses
136 system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses
137 system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses
138 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
139 system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
140 system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses
141 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54551.724138 # average ReadReq miss latency
142 system.cpu.icache.ReadReq_avg_miss_latency::total 54551.724138 # average ReadReq miss latency
143 system.cpu.icache.demand_avg_miss_latency::cpu.inst 54551.724138 # average overall miss latency
144 system.cpu.icache.demand_avg_miss_latency::total 54551.724138 # average overall miss latency
145 system.cpu.icache.overall_avg_miss_latency::cpu.inst 54551.724138 # average overall miss latency
146 system.cpu.icache.overall_avg_miss_latency::total 54551.724138 # average overall miss latency
147 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
148 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
149 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
150 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
151 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
152 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
153 system.cpu.icache.fast_writes 0 # number of fast writes performed
154 system.cpu.icache.cache_copies 0 # number of cache copies performed
155 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 638 # number of ReadReq MSHR misses
156 system.cpu.icache.ReadReq_mshr_misses::total 638 # number of ReadReq MSHR misses
157 system.cpu.icache.demand_mshr_misses::cpu.inst 638 # number of demand (read+write) MSHR misses
158 system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses
159 system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses
160 system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses
161 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32890000 # number of ReadReq MSHR miss cycles
162 system.cpu.icache.ReadReq_mshr_miss_latency::total 32890000 # number of ReadReq MSHR miss cycles
163 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32890000 # number of demand (read+write) MSHR miss cycles
164 system.cpu.icache.demand_mshr_miss_latency::total 32890000 # number of demand (read+write) MSHR miss cycles
165 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32890000 # number of overall MSHR miss cycles
166 system.cpu.icache.overall_mshr_miss_latency::total 32890000 # number of overall MSHR miss cycles
167 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
168 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
169 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
170 system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
171 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
172 system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses
173 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51551.724138 # average ReadReq mshr miss latency
174 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51551.724138 # average ReadReq mshr miss latency
175 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51551.724138 # average overall mshr miss latency
176 system.cpu.icache.demand_avg_mshr_miss_latency::total 51551.724138 # average overall mshr miss latency
177 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51551.724138 # average overall mshr miss latency
178 system.cpu.icache.overall_avg_mshr_miss_latency::total 51551.724138 # average overall mshr miss latency
179 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
180 system.cpu.dcache.replacements 9111140 # number of replacements
181 system.cpu.dcache.tagsinuse 4083.719979 # Cycle average of tags in use
182 system.cpu.dcache.total_refs 645855060 # Total number of references to valid blocks.
183 system.cpu.dcache.sampled_refs 9115236 # Sample count of references to valid blocks.
184 system.cpu.dcache.avg_refs 70.854453 # Average number of references to valid blocks.
185 system.cpu.dcache.warmup_cycle 25923025000 # Cycle when the warmup percentage was hit.
186 system.cpu.dcache.occ_blocks::cpu.data 4083.719979 # Average occupied blocks per requestor
187 system.cpu.dcache.occ_percent::cpu.data 0.997002 # Average percentage of cache occupancy
188 system.cpu.dcache.occ_percent::total 0.997002 # Average percentage of cache occupancy
189 system.cpu.dcache.ReadReq_hits::cpu.data 475158040 # number of ReadReq hits
190 system.cpu.dcache.ReadReq_hits::total 475158040 # number of ReadReq hits
191 system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits
192 system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits
193 system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits
194 system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits
195 system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
196 system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
197 system.cpu.dcache.demand_hits::cpu.data 645854938 # number of demand (read+write) hits
198 system.cpu.dcache.demand_hits::total 645854938 # number of demand (read+write) hits
199 system.cpu.dcache.overall_hits::cpu.data 645854938 # number of overall hits
200 system.cpu.dcache.overall_hits::total 645854938 # number of overall hits
201 system.cpu.dcache.ReadReq_misses::cpu.data 7226087 # number of ReadReq misses
202 system.cpu.dcache.ReadReq_misses::total 7226087 # number of ReadReq misses
203 system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses
204 system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses
205 system.cpu.dcache.demand_misses::cpu.data 9115236 # number of demand (read+write) misses
206 system.cpu.dcache.demand_misses::total 9115236 # number of demand (read+write) misses
207 system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses
208 system.cpu.dcache.overall_misses::total 9115236 # number of overall misses
209 system.cpu.dcache.ReadReq_miss_latency::cpu.data 177140908000 # number of ReadReq miss cycles
210 system.cpu.dcache.ReadReq_miss_latency::total 177140908000 # number of ReadReq miss cycles
211 system.cpu.dcache.WriteReq_miss_latency::cpu.data 63824222000 # number of WriteReq miss cycles
212 system.cpu.dcache.WriteReq_miss_latency::total 63824222000 # number of WriteReq miss cycles
213 system.cpu.dcache.demand_miss_latency::cpu.data 240965130000 # number of demand (read+write) miss cycles
214 system.cpu.dcache.demand_miss_latency::total 240965130000 # number of demand (read+write) miss cycles
215 system.cpu.dcache.overall_miss_latency::cpu.data 240965130000 # number of overall miss cycles
216 system.cpu.dcache.overall_miss_latency::total 240965130000 # number of overall miss cycles
217 system.cpu.dcache.ReadReq_accesses::cpu.data 482384127 # number of ReadReq accesses(hits+misses)
218 system.cpu.dcache.ReadReq_accesses::total 482384127 # number of ReadReq accesses(hits+misses)
219 system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
220 system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
221 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
222 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
223 system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
224 system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
225 system.cpu.dcache.demand_accesses::cpu.data 654970174 # number of demand (read+write) accesses
226 system.cpu.dcache.demand_accesses::total 654970174 # number of demand (read+write) accesses
227 system.cpu.dcache.overall_accesses::cpu.data 654970174 # number of overall (read+write) accesses
228 system.cpu.dcache.overall_accesses::total 654970174 # number of overall (read+write) accesses
229 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.014980 # miss rate for ReadReq accesses
230 system.cpu.dcache.ReadReq_miss_rate::total 0.014980 # miss rate for ReadReq accesses
231 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses
232 system.cpu.dcache.WriteReq_miss_rate::total 0.010946 # miss rate for WriteReq accesses
233 system.cpu.dcache.demand_miss_rate::cpu.data 0.013917 # miss rate for demand accesses
234 system.cpu.dcache.demand_miss_rate::total 0.013917 # miss rate for demand accesses
235 system.cpu.dcache.overall_miss_rate::cpu.data 0.013917 # miss rate for overall accesses
236 system.cpu.dcache.overall_miss_rate::total 0.013917 # miss rate for overall accesses
237 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24514.084594 # average ReadReq miss latency
238 system.cpu.dcache.ReadReq_avg_miss_latency::total 24514.084594 # average ReadReq miss latency
239 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33784.641656 # average WriteReq miss latency
240 system.cpu.dcache.WriteReq_avg_miss_latency::total 33784.641656 # average WriteReq miss latency
241 system.cpu.dcache.demand_avg_miss_latency::cpu.data 26435.424162 # average overall miss latency
242 system.cpu.dcache.demand_avg_miss_latency::total 26435.424162 # average overall miss latency
243 system.cpu.dcache.overall_avg_miss_latency::cpu.data 26435.424162 # average overall miss latency
244 system.cpu.dcache.overall_avg_miss_latency::total 26435.424162 # average overall miss latency
245 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
246 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
247 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
248 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
249 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
250 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
251 system.cpu.dcache.fast_writes 0 # number of fast writes performed
252 system.cpu.dcache.cache_copies 0 # number of cache copies performed
253 system.cpu.dcache.writebacks::writebacks 3061985 # number of writebacks
254 system.cpu.dcache.writebacks::total 3061985 # number of writebacks
255 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226087 # number of ReadReq MSHR misses
256 system.cpu.dcache.ReadReq_mshr_misses::total 7226087 # number of ReadReq MSHR misses
257 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses
258 system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses
259 system.cpu.dcache.demand_mshr_misses::cpu.data 9115236 # number of demand (read+write) MSHR misses
260 system.cpu.dcache.demand_mshr_misses::total 9115236 # number of demand (read+write) MSHR misses
261 system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses
262 system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses
263 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 155462647000 # number of ReadReq MSHR miss cycles
264 system.cpu.dcache.ReadReq_mshr_miss_latency::total 155462647000 # number of ReadReq MSHR miss cycles
265 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 58156775000 # number of WriteReq MSHR miss cycles
266 system.cpu.dcache.WriteReq_mshr_miss_latency::total 58156775000 # number of WriteReq MSHR miss cycles
267 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 213619422000 # number of demand (read+write) MSHR miss cycles
268 system.cpu.dcache.demand_mshr_miss_latency::total 213619422000 # number of demand (read+write) MSHR miss cycles
269 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 213619422000 # number of overall MSHR miss cycles
270 system.cpu.dcache.overall_mshr_miss_latency::total 213619422000 # number of overall MSHR miss cycles
271 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.014980 # mshr miss rate for ReadReq accesses
272 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.014980 # mshr miss rate for ReadReq accesses
273 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses
274 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010946 # mshr miss rate for WriteReq accesses
275 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for demand accesses
276 system.cpu.dcache.demand_mshr_miss_rate::total 0.013917 # mshr miss rate for demand accesses
277 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for overall accesses
278 system.cpu.dcache.overall_mshr_miss_rate::total 0.013917 # mshr miss rate for overall accesses
279 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21514.084594 # average ReadReq mshr miss latency
280 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21514.084594 # average ReadReq mshr miss latency
281 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30784.641656 # average WriteReq mshr miss latency
282 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30784.641656 # average WriteReq mshr miss latency
283 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23435.424162 # average overall mshr miss latency
284 system.cpu.dcache.demand_avg_mshr_miss_latency::total 23435.424162 # average overall mshr miss latency
285 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23435.424162 # average overall mshr miss latency
286 system.cpu.dcache.overall_avg_mshr_miss_latency::total 23435.424162 # average overall mshr miss latency
287 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
288 system.cpu.l2cache.replacements 2687066 # number of replacements
289 system.cpu.l2cache.tagsinuse 26134.517233 # Cycle average of tags in use
290 system.cpu.l2cache.total_refs 7569171 # Total number of references to valid blocks.
291 system.cpu.l2cache.sampled_refs 2714383 # Sample count of references to valid blocks.
292 system.cpu.l2cache.avg_refs 2.788542 # Average number of references to valid blocks.
293 system.cpu.l2cache.warmup_cycle 538044123000 # Cycle when the warmup percentage was hit.
294 system.cpu.l2cache.occ_blocks::writebacks 11106.896016 # Average occupied blocks per requestor
295 system.cpu.l2cache.occ_blocks::cpu.inst 11.181020 # Average occupied blocks per requestor
296 system.cpu.l2cache.occ_blocks::cpu.data 15016.440197 # Average occupied blocks per requestor
297 system.cpu.l2cache.occ_percent::writebacks 0.338956 # Average percentage of cache occupancy
298 system.cpu.l2cache.occ_percent::cpu.inst 0.000341 # Average percentage of cache occupancy
299 system.cpu.l2cache.occ_percent::cpu.data 0.458265 # Average percentage of cache occupancy
300 system.cpu.l2cache.occ_percent::total 0.797562 # Average percentage of cache occupancy
301 system.cpu.l2cache.ReadReq_hits::cpu.inst 22 # number of ReadReq hits
302 system.cpu.l2cache.ReadReq_hits::cpu.data 5417142 # number of ReadReq hits
303 system.cpu.l2cache.ReadReq_hits::total 5417164 # number of ReadReq hits
304 system.cpu.l2cache.Writeback_hits::writebacks 3061985 # number of Writeback hits
305 system.cpu.l2cache.Writeback_hits::total 3061985 # number of Writeback hits
306 system.cpu.l2cache.ReadExReq_hits::cpu.data 999241 # number of ReadExReq hits
307 system.cpu.l2cache.ReadExReq_hits::total 999241 # number of ReadExReq hits
308 system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits
309 system.cpu.l2cache.demand_hits::cpu.data 6416383 # number of demand (read+write) hits
310 system.cpu.l2cache.demand_hits::total 6416405 # number of demand (read+write) hits
311 system.cpu.l2cache.overall_hits::cpu.inst 22 # number of overall hits
312 system.cpu.l2cache.overall_hits::cpu.data 6416383 # number of overall hits
313 system.cpu.l2cache.overall_hits::total 6416405 # number of overall hits
314 system.cpu.l2cache.ReadReq_misses::cpu.inst 616 # number of ReadReq misses
315 system.cpu.l2cache.ReadReq_misses::cpu.data 1808945 # number of ReadReq misses
316 system.cpu.l2cache.ReadReq_misses::total 1809561 # number of ReadReq misses
317 system.cpu.l2cache.ReadExReq_misses::cpu.data 889908 # number of ReadExReq misses
318 system.cpu.l2cache.ReadExReq_misses::total 889908 # number of ReadExReq misses
319 system.cpu.l2cache.demand_misses::cpu.inst 616 # number of demand (read+write) misses
320 system.cpu.l2cache.demand_misses::cpu.data 2698853 # number of demand (read+write) misses
321 system.cpu.l2cache.demand_misses::total 2699469 # number of demand (read+write) misses
322 system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses
323 system.cpu.l2cache.overall_misses::cpu.data 2698853 # number of overall misses
324 system.cpu.l2cache.overall_misses::total 2699469 # number of overall misses
325 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32032000 # number of ReadReq miss cycles
326 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 94065140000 # number of ReadReq miss cycles
327 system.cpu.l2cache.ReadReq_miss_latency::total 94097172000 # number of ReadReq miss cycles
328 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46275216000 # number of ReadExReq miss cycles
329 system.cpu.l2cache.ReadExReq_miss_latency::total 46275216000 # number of ReadExReq miss cycles
330 system.cpu.l2cache.demand_miss_latency::cpu.inst 32032000 # number of demand (read+write) miss cycles
331 system.cpu.l2cache.demand_miss_latency::cpu.data 140340356000 # number of demand (read+write) miss cycles
332 system.cpu.l2cache.demand_miss_latency::total 140372388000 # number of demand (read+write) miss cycles
333 system.cpu.l2cache.overall_miss_latency::cpu.inst 32032000 # number of overall miss cycles
334 system.cpu.l2cache.overall_miss_latency::cpu.data 140340356000 # number of overall miss cycles
335 system.cpu.l2cache.overall_miss_latency::total 140372388000 # number of overall miss cycles
336 system.cpu.l2cache.ReadReq_accesses::cpu.inst 638 # number of ReadReq accesses(hits+misses)
337 system.cpu.l2cache.ReadReq_accesses::cpu.data 7226087 # number of ReadReq accesses(hits+misses)
338 system.cpu.l2cache.ReadReq_accesses::total 7226725 # number of ReadReq accesses(hits+misses)
339 system.cpu.l2cache.Writeback_accesses::writebacks 3061985 # number of Writeback accesses(hits+misses)
340 system.cpu.l2cache.Writeback_accesses::total 3061985 # number of Writeback accesses(hits+misses)
341 system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889149 # number of ReadExReq accesses(hits+misses)
342 system.cpu.l2cache.ReadExReq_accesses::total 1889149 # number of ReadExReq accesses(hits+misses)
343 system.cpu.l2cache.demand_accesses::cpu.inst 638 # number of demand (read+write) accesses
344 system.cpu.l2cache.demand_accesses::cpu.data 9115236 # number of demand (read+write) accesses
345 system.cpu.l2cache.demand_accesses::total 9115874 # number of demand (read+write) accesses
346 system.cpu.l2cache.overall_accesses::cpu.inst 638 # number of overall (read+write) accesses
347 system.cpu.l2cache.overall_accesses::cpu.data 9115236 # number of overall (read+write) accesses
348 system.cpu.l2cache.overall_accesses::total 9115874 # number of overall (read+write) accesses
349 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.965517 # miss rate for ReadReq accesses
350 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250335 # miss rate for ReadReq accesses
351 system.cpu.l2cache.ReadReq_miss_rate::total 0.250398 # miss rate for ReadReq accesses
352 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.471063 # miss rate for ReadExReq accesses
353 system.cpu.l2cache.ReadExReq_miss_rate::total 0.471063 # miss rate for ReadExReq accesses
354 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965517 # miss rate for demand accesses
355 system.cpu.l2cache.demand_miss_rate::cpu.data 0.296082 # miss rate for demand accesses
356 system.cpu.l2cache.demand_miss_rate::total 0.296128 # miss rate for demand accesses
357 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses
358 system.cpu.l2cache.overall_miss_rate::cpu.data 0.296082 # miss rate for overall accesses
359 system.cpu.l2cache.overall_miss_rate::total 0.296128 # miss rate for overall accesses
360 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
361 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
362 system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
363 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
364 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
365 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
366 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
367 system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
368 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
369 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
370 system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
371 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
372 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
373 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
374 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
375 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
376 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
377 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
378 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
379 system.cpu.l2cache.writebacks::writebacks 1171980 # number of writebacks
380 system.cpu.l2cache.writebacks::total 1171980 # number of writebacks
381 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 616 # number of ReadReq MSHR misses
382 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1808945 # number of ReadReq MSHR misses
383 system.cpu.l2cache.ReadReq_mshr_misses::total 1809561 # number of ReadReq MSHR misses
384 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 889908 # number of ReadExReq MSHR misses
385 system.cpu.l2cache.ReadExReq_mshr_misses::total 889908 # number of ReadExReq MSHR misses
386 system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses
387 system.cpu.l2cache.demand_mshr_misses::cpu.data 2698853 # number of demand (read+write) MSHR misses
388 system.cpu.l2cache.demand_mshr_misses::total 2699469 # number of demand (read+write) MSHR misses
389 system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses
390 system.cpu.l2cache.overall_mshr_misses::cpu.data 2698853 # number of overall MSHR misses
391 system.cpu.l2cache.overall_mshr_misses::total 2699469 # number of overall MSHR misses
392 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24640000 # number of ReadReq MSHR miss cycles
393 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 72357800000 # number of ReadReq MSHR miss cycles
394 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 72382440000 # number of ReadReq MSHR miss cycles
395 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 35596320000 # number of ReadExReq MSHR miss cycles
396 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 35596320000 # number of ReadExReq MSHR miss cycles
397 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24640000 # number of demand (read+write) MSHR miss cycles
398 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 107954120000 # number of demand (read+write) MSHR miss cycles
399 system.cpu.l2cache.demand_mshr_miss_latency::total 107978760000 # number of demand (read+write) MSHR miss cycles
400 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24640000 # number of overall MSHR miss cycles
401 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 107954120000 # number of overall MSHR miss cycles
402 system.cpu.l2cache.overall_mshr_miss_latency::total 107978760000 # number of overall MSHR miss cycles
403 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadReq accesses
404 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250335 # mshr miss rate for ReadReq accesses
405 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.250398 # mshr miss rate for ReadReq accesses
406 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.471063 # mshr miss rate for ReadExReq accesses
407 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.471063 # mshr miss rate for ReadExReq accesses
408 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for demand accesses
409 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.296082 # mshr miss rate for demand accesses
410 system.cpu.l2cache.demand_mshr_miss_rate::total 0.296128 # mshr miss rate for demand accesses
411 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses
412 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.296082 # mshr miss rate for overall accesses
413 system.cpu.l2cache.overall_mshr_miss_rate::total 0.296128 # mshr miss rate for overall accesses
414 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
415 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
416 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
417 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
418 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
419 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
420 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
421 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
422 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
423 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
424 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
425 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
427 ---------- End Simulation Statistics ----------
projects / gem5.git / blob