2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 5.898831 # Number of seconds simulated
4 sim_ticks 5898831348500 # Number of ticks simulated
5 final_tick 5898831348500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 1175665 # Simulator instruction rate (inst/s)
8 host_op_rate 1831792 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 2305472192 # Simulator tick rate (ticks/s)
10 host_mem_usage 275096 # Number of bytes of host memory used
11 host_seconds 2558.62 # Real time elapsed on the host
12 sim_insts 3008081022 # Number of instructions simulated
13 sim_ops 4686862596 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
17 system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.data 126068992 # Number of bytes read from this memory
19 system.physmem.bytes_read::total 126112192 # Number of bytes read from this memory
20 system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory
21 system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory
22 system.physmem.bytes_written::writebacks 66108032 # Number of bytes written to this memory
23 system.physmem.bytes_written::total 66108032 # Number of bytes written to this memory
24 system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory
25 system.physmem.num_reads::cpu.data 1969828 # Number of read requests responded to by this memory
26 system.physmem.num_reads::total 1970503 # Number of read requests responded to by this memory
27 system.physmem.num_writes::writebacks 1032938 # Number of write requests responded to by this memory
28 system.physmem.num_writes::total 1032938 # Number of write requests responded to by this memory
29 system.physmem.bw_read::cpu.inst 7323 # Total read bandwidth from this memory (bytes/s)
30 system.physmem.bw_read::cpu.data 21371859 # Total read bandwidth from this memory (bytes/s)
31 system.physmem.bw_read::total 21379183 # Total read bandwidth from this memory (bytes/s)
32 system.physmem.bw_inst_read::cpu.inst 7323 # Instruction read bandwidth from this memory (bytes/s)
33 system.physmem.bw_inst_read::total 7323 # Instruction read bandwidth from this memory (bytes/s)
34 system.physmem.bw_write::writebacks 11206971 # Write bandwidth from this memory (bytes/s)
35 system.physmem.bw_write::total 11206971 # Write bandwidth from this memory (bytes/s)
36 system.physmem.bw_total::writebacks 11206971 # Total bandwidth to/from this memory (bytes/s)
37 system.physmem.bw_total::cpu.inst 7323 # Total bandwidth to/from this memory (bytes/s)
38 system.physmem.bw_total::cpu.data 21371859 # Total bandwidth to/from this memory (bytes/s)
39 system.physmem.bw_total::total 32586154 # Total bandwidth to/from this memory (bytes/s)
40 system.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
41 system.cpu_clk_domain.clock 500 # Clock period in ticks
42 system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
43 system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
44 system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
45 system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
46 system.cpu.workload.num_syscalls 46 # Number of system calls
47 system.cpu.pwrStateResidencyTicks::ON 5898831348500 # Cumulative time (in ticks) in various power states
48 system.cpu.numCycles 11797662697 # number of cpu cycles simulated
49 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
50 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
51 system.cpu.committedInsts 3008081022 # Number of instructions committed
52 system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed
53 system.cpu.num_int_alu_accesses 4684368009 # Number of integer alu accesses
54 system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
55 system.cpu.num_func_calls 33534539 # number of times a function call or return occured
56 system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls
57 system.cpu.num_int_insts 4684368009 # number of integer instructions
58 system.cpu.num_fp_insts 0 # number of float instructions
59 system.cpu.num_int_register_reads 10688755601 # number of times the integer registers were read
60 system.cpu.num_int_register_writes 3999841477 # number of times the integer registers were written
61 system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
62 system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
63 system.cpu.num_cc_register_reads 1226718827 # number of times the CC registers were read
64 system.cpu.num_cc_register_writes 1355930461 # number of times the CC registers were written
65 system.cpu.num_mem_refs 1677713084 # number of memory refs
66 system.cpu.num_load_insts 1239184746 # Number of load instructions
67 system.cpu.num_store_insts 438528338 # Number of store instructions
68 system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
69 system.cpu.num_busy_cycles 11797662696.997999 # Number of busy cycles
70 system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
71 system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
72 system.cpu.Branches 248500691 # Number of branches fetched
73 system.cpu.op_class::No_OpClass 2494522 0.05% 0.05% # Class of executed instruction
74 system.cpu.op_class::IntAlu 3006647871 64.15% 64.20% # Class of executed instruction
75 system.cpu.op_class::IntMult 6215 0.00% 64.20% # Class of executed instruction
76 system.cpu.op_class::IntDiv 904 0.00% 64.20% # Class of executed instruction
77 system.cpu.op_class::FloatAdd 0 0.00% 64.20% # Class of executed instruction
78 system.cpu.op_class::FloatCmp 0 0.00% 64.20% # Class of executed instruction
79 system.cpu.op_class::FloatCvt 0 0.00% 64.20% # Class of executed instruction
80 system.cpu.op_class::FloatMult 0 0.00% 64.20% # Class of executed instruction
81 system.cpu.op_class::FloatMultAcc 0 0.00% 64.20% # Class of executed instruction
82 system.cpu.op_class::FloatDiv 0 0.00% 64.20% # Class of executed instruction
83 system.cpu.op_class::FloatMisc 0 0.00% 64.20% # Class of executed instruction
84 system.cpu.op_class::FloatSqrt 0 0.00% 64.20% # Class of executed instruction
85 system.cpu.op_class::SimdAdd 0 0.00% 64.20% # Class of executed instruction
86 system.cpu.op_class::SimdAddAcc 0 0.00% 64.20% # Class of executed instruction
87 system.cpu.op_class::SimdAlu 0 0.00% 64.20% # Class of executed instruction
88 system.cpu.op_class::SimdCmp 0 0.00% 64.20% # Class of executed instruction
89 system.cpu.op_class::SimdCvt 0 0.00% 64.20% # Class of executed instruction
90 system.cpu.op_class::SimdMisc 0 0.00% 64.20% # Class of executed instruction
91 system.cpu.op_class::SimdMult 0 0.00% 64.20% # Class of executed instruction
92 system.cpu.op_class::SimdMultAcc 0 0.00% 64.20% # Class of executed instruction
93 system.cpu.op_class::SimdShift 0 0.00% 64.20% # Class of executed instruction
94 system.cpu.op_class::SimdShiftAcc 0 0.00% 64.20% # Class of executed instruction
95 system.cpu.op_class::SimdSqrt 0 0.00% 64.20% # Class of executed instruction
96 system.cpu.op_class::SimdFloatAdd 0 0.00% 64.20% # Class of executed instruction
97 system.cpu.op_class::SimdFloatAlu 0 0.00% 64.20% # Class of executed instruction
98 system.cpu.op_class::SimdFloatCmp 0 0.00% 64.20% # Class of executed instruction
99 system.cpu.op_class::SimdFloatCvt 0 0.00% 64.20% # Class of executed instruction
100 system.cpu.op_class::SimdFloatDiv 0 0.00% 64.20% # Class of executed instruction
101 system.cpu.op_class::SimdFloatMisc 0 0.00% 64.20% # Class of executed instruction
102 system.cpu.op_class::SimdFloatMult 0 0.00% 64.20% # Class of executed instruction
103 system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.20% # Class of executed instruction
104 system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.20% # Class of executed instruction
105 system.cpu.op_class::MemRead 1239184746 26.44% 90.64% # Class of executed instruction
106 system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Class of executed instruction
107 system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
108 system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
109 system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
110 system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
111 system.cpu.op_class::total 4686862596 # Class of executed instruction
112 system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
113 system.cpu.dcache.tags.replacements 9108581 # number of replacements
114 system.cpu.dcache.tags.tagsinuse 4084.589706 # Cycle average of tags in use
115 system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks.
116 system.cpu.dcache.tags.sampled_refs 9112677 # Sample count of references to valid blocks.
117 system.cpu.dcache.tags.avg_refs 183.107599 # Average number of references to valid blocks.
118 system.cpu.dcache.tags.warmup_cycle 58922805500 # Cycle when the warmup percentage was hit.
119 system.cpu.dcache.tags.occ_blocks::cpu.data 4084.589706 # Average occupied blocks per requestor
120 system.cpu.dcache.tags.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy
121 system.cpu.dcache.tags.occ_percent::total 0.997214 # Average percentage of cache occupancy
122 system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
123 system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
124 system.cpu.dcache.tags.age_task_id_blocks_1024::1 898 # Occupied blocks per task id
125 system.cpu.dcache.tags.age_task_id_blocks_1024::2 2768 # Occupied blocks per task id
126 system.cpu.dcache.tags.age_task_id_blocks_1024::3 329 # Occupied blocks per task id
127 system.cpu.dcache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id
128 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
129 system.cpu.dcache.tags.tag_accesses 3364538845 # Number of tag accesses
130 system.cpu.dcache.tags.data_accesses 3364538845 # Number of data accesses
131 system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
132 system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits
133 system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits
134 system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits
135 system.cpu.dcache.WriteReq_hits::total 436638511 # number of WriteReq hits
136 system.cpu.dcache.demand_hits::cpu.data 1668600407 # number of demand (read+write) hits
137 system.cpu.dcache.demand_hits::total 1668600407 # number of demand (read+write) hits
138 system.cpu.dcache.overall_hits::cpu.data 1668600407 # number of overall hits
139 system.cpu.dcache.overall_hits::total 1668600407 # number of overall hits
140 system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses
141 system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses
142 system.cpu.dcache.WriteReq_misses::cpu.data 1889827 # number of WriteReq misses
143 system.cpu.dcache.WriteReq_misses::total 1889827 # number of WriteReq misses
144 system.cpu.dcache.demand_misses::cpu.data 9112677 # number of demand (read+write) misses
145 system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses
146 system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses
147 system.cpu.dcache.overall_misses::total 9112677 # number of overall misses
148 system.cpu.dcache.ReadReq_miss_latency::cpu.data 152690255000 # number of ReadReq miss cycles
149 system.cpu.dcache.ReadReq_miss_latency::total 152690255000 # number of ReadReq miss cycles
150 system.cpu.dcache.WriteReq_miss_latency::cpu.data 64265951000 # number of WriteReq miss cycles
151 system.cpu.dcache.WriteReq_miss_latency::total 64265951000 # number of WriteReq miss cycles
152 system.cpu.dcache.demand_miss_latency::cpu.data 216956206000 # number of demand (read+write) miss cycles
153 system.cpu.dcache.demand_miss_latency::total 216956206000 # number of demand (read+write) miss cycles
154 system.cpu.dcache.overall_miss_latency::cpu.data 216956206000 # number of overall miss cycles
155 system.cpu.dcache.overall_miss_latency::total 216956206000 # number of overall miss cycles
156 system.cpu.dcache.ReadReq_accesses::cpu.data 1239184746 # number of ReadReq accesses(hits+misses)
157 system.cpu.dcache.ReadReq_accesses::total 1239184746 # number of ReadReq accesses(hits+misses)
158 system.cpu.dcache.WriteReq_accesses::cpu.data 438528338 # number of WriteReq accesses(hits+misses)
159 system.cpu.dcache.WriteReq_accesses::total 438528338 # number of WriteReq accesses(hits+misses)
160 system.cpu.dcache.demand_accesses::cpu.data 1677713084 # number of demand (read+write) accesses
161 system.cpu.dcache.demand_accesses::total 1677713084 # number of demand (read+write) accesses
162 system.cpu.dcache.overall_accesses::cpu.data 1677713084 # number of overall (read+write) accesses
163 system.cpu.dcache.overall_accesses::total 1677713084 # number of overall (read+write) accesses
164 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses
165 system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses
166 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses
167 system.cpu.dcache.WriteReq_miss_rate::total 0.004309 # miss rate for WriteReq accesses
168 system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 # miss rate for demand accesses
169 system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses
170 system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses
171 system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses
172 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21139.890071 # average ReadReq miss latency
173 system.cpu.dcache.ReadReq_avg_miss_latency::total 21139.890071 # average ReadReq miss latency
174 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34006.261420 # average WriteReq miss latency
175 system.cpu.dcache.WriteReq_avg_miss_latency::total 34006.261420 # average WriteReq miss latency
176 system.cpu.dcache.demand_avg_miss_latency::cpu.data 23808.174700 # average overall miss latency
177 system.cpu.dcache.demand_avg_miss_latency::total 23808.174700 # average overall miss latency
178 system.cpu.dcache.overall_avg_miss_latency::cpu.data 23808.174700 # average overall miss latency
179 system.cpu.dcache.overall_avg_miss_latency::total 23808.174700 # average overall miss latency
180 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
181 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
182 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
183 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
184 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
185 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
186 system.cpu.dcache.writebacks::writebacks 3669049 # number of writebacks
187 system.cpu.dcache.writebacks::total 3669049 # number of writebacks
188 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses
189 system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses
190 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses
191 system.cpu.dcache.WriteReq_mshr_misses::total 1889827 # number of WriteReq MSHR misses
192 system.cpu.dcache.demand_mshr_misses::cpu.data 9112677 # number of demand (read+write) MSHR misses
193 system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses
194 system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses
195 system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses
196 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 145467405000 # number of ReadReq MSHR miss cycles
197 system.cpu.dcache.ReadReq_mshr_miss_latency::total 145467405000 # number of ReadReq MSHR miss cycles
198 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 62376124000 # number of WriteReq MSHR miss cycles
199 system.cpu.dcache.WriteReq_mshr_miss_latency::total 62376124000 # number of WriteReq MSHR miss cycles
200 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 207843529000 # number of demand (read+write) MSHR miss cycles
201 system.cpu.dcache.demand_mshr_miss_latency::total 207843529000 # number of demand (read+write) MSHR miss cycles
202 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 207843529000 # number of overall MSHR miss cycles
203 system.cpu.dcache.overall_mshr_miss_latency::total 207843529000 # number of overall MSHR miss cycles
204 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses
205 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses
206 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses
207 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004309 # mshr miss rate for WriteReq accesses
208 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for demand accesses
209 system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses
210 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses
211 system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses
212 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20139.890071 # average ReadReq mshr miss latency
213 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20139.890071 # average ReadReq mshr miss latency
214 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33006.261420 # average WriteReq mshr miss latency
215 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33006.261420 # average WriteReq mshr miss latency
216 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22808.174700 # average overall mshr miss latency
217 system.cpu.dcache.demand_avg_mshr_miss_latency::total 22808.174700 # average overall mshr miss latency
218 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22808.174700 # average overall mshr miss latency
219 system.cpu.dcache.overall_avg_mshr_miss_latency::total 22808.174700 # average overall mshr miss latency
220 system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
221 system.cpu.icache.tags.replacements 10 # number of replacements
222 system.cpu.icache.tags.tagsinuse 555.760511 # Cycle average of tags in use
223 system.cpu.icache.tags.total_refs 4013232207 # Total number of references to valid blocks.
224 system.cpu.icache.tags.sampled_refs 675 # Sample count of references to valid blocks.
225 system.cpu.icache.tags.avg_refs 5945529.195556 # Average number of references to valid blocks.
226 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
227 system.cpu.icache.tags.occ_blocks::cpu.inst 555.760511 # Average occupied blocks per requestor
228 system.cpu.icache.tags.occ_percent::cpu.inst 0.271367 # Average percentage of cache occupancy
229 system.cpu.icache.tags.occ_percent::total 0.271367 # Average percentage of cache occupancy
230 system.cpu.icache.tags.occ_task_id_blocks::1024 665 # Occupied blocks per task id
231 system.cpu.icache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id
232 system.cpu.icache.tags.age_task_id_blocks_1024::4 632 # Occupied blocks per task id
233 system.cpu.icache.tags.occ_task_id_percent::1024 0.324707 # Percentage of cache occupancy per task id
234 system.cpu.icache.tags.tag_accesses 8026466439 # Number of tag accesses
235 system.cpu.icache.tags.data_accesses 8026466439 # Number of data accesses
236 system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
237 system.cpu.icache.ReadReq_hits::cpu.inst 4013232207 # number of ReadReq hits
238 system.cpu.icache.ReadReq_hits::total 4013232207 # number of ReadReq hits
239 system.cpu.icache.demand_hits::cpu.inst 4013232207 # number of demand (read+write) hits
240 system.cpu.icache.demand_hits::total 4013232207 # number of demand (read+write) hits
241 system.cpu.icache.overall_hits::cpu.inst 4013232207 # number of overall hits
242 system.cpu.icache.overall_hits::total 4013232207 # number of overall hits
243 system.cpu.icache.ReadReq_misses::cpu.inst 675 # number of ReadReq misses
244 system.cpu.icache.ReadReq_misses::total 675 # number of ReadReq misses
245 system.cpu.icache.demand_misses::cpu.inst 675 # number of demand (read+write) misses
246 system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses
247 system.cpu.icache.overall_misses::cpu.inst 675 # number of overall misses
248 system.cpu.icache.overall_misses::total 675 # number of overall misses
249 system.cpu.icache.ReadReq_miss_latency::cpu.inst 42528500 # number of ReadReq miss cycles
250 system.cpu.icache.ReadReq_miss_latency::total 42528500 # number of ReadReq miss cycles
251 system.cpu.icache.demand_miss_latency::cpu.inst 42528500 # number of demand (read+write) miss cycles
252 system.cpu.icache.demand_miss_latency::total 42528500 # number of demand (read+write) miss cycles
253 system.cpu.icache.overall_miss_latency::cpu.inst 42528500 # number of overall miss cycles
254 system.cpu.icache.overall_miss_latency::total 42528500 # number of overall miss cycles
255 system.cpu.icache.ReadReq_accesses::cpu.inst 4013232882 # number of ReadReq accesses(hits+misses)
256 system.cpu.icache.ReadReq_accesses::total 4013232882 # number of ReadReq accesses(hits+misses)
257 system.cpu.icache.demand_accesses::cpu.inst 4013232882 # number of demand (read+write) accesses
258 system.cpu.icache.demand_accesses::total 4013232882 # number of demand (read+write) accesses
259 system.cpu.icache.overall_accesses::cpu.inst 4013232882 # number of overall (read+write) accesses
260 system.cpu.icache.overall_accesses::total 4013232882 # number of overall (read+write) accesses
261 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses
262 system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses
263 system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses
264 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
265 system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
266 system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses
267 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63005.185185 # average ReadReq miss latency
268 system.cpu.icache.ReadReq_avg_miss_latency::total 63005.185185 # average ReadReq miss latency
269 system.cpu.icache.demand_avg_miss_latency::cpu.inst 63005.185185 # average overall miss latency
270 system.cpu.icache.demand_avg_miss_latency::total 63005.185185 # average overall miss latency
271 system.cpu.icache.overall_avg_miss_latency::cpu.inst 63005.185185 # average overall miss latency
272 system.cpu.icache.overall_avg_miss_latency::total 63005.185185 # average overall miss latency
273 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
274 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
275 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
276 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
277 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
278 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
279 system.cpu.icache.writebacks::writebacks 10 # number of writebacks
280 system.cpu.icache.writebacks::total 10 # number of writebacks
281 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses
282 system.cpu.icache.ReadReq_mshr_misses::total 675 # number of ReadReq MSHR misses
283 system.cpu.icache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses
284 system.cpu.icache.demand_mshr_misses::total 675 # number of demand (read+write) MSHR misses
285 system.cpu.icache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses
286 system.cpu.icache.overall_mshr_misses::total 675 # number of overall MSHR misses
287 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41853500 # number of ReadReq MSHR miss cycles
288 system.cpu.icache.ReadReq_mshr_miss_latency::total 41853500 # number of ReadReq MSHR miss cycles
289 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41853500 # number of demand (read+write) MSHR miss cycles
290 system.cpu.icache.demand_mshr_miss_latency::total 41853500 # number of demand (read+write) MSHR miss cycles
291 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41853500 # number of overall MSHR miss cycles
292 system.cpu.icache.overall_mshr_miss_latency::total 41853500 # number of overall MSHR miss cycles
293 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
294 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
295 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
296 system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
297 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
298 system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses
299 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62005.185185 # average ReadReq mshr miss latency
300 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62005.185185 # average ReadReq mshr miss latency
301 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62005.185185 # average overall mshr miss latency
302 system.cpu.icache.demand_avg_mshr_miss_latency::total 62005.185185 # average overall mshr miss latency
303 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62005.185185 # average overall mshr miss latency
304 system.cpu.icache.overall_avg_mshr_miss_latency::total 62005.185185 # average overall mshr miss latency
305 system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
306 system.cpu.l2cache.tags.replacements 1938075 # number of replacements
307 system.cpu.l2cache.tags.tagsinuse 31745.660470 # Cycle average of tags in use
308 system.cpu.l2cache.tags.total_refs 16250887 # Total number of references to valid blocks.
309 system.cpu.l2cache.tags.sampled_refs 1970843 # Sample count of references to valid blocks.
310 system.cpu.l2cache.tags.avg_refs 8.245653 # Average number of references to valid blocks.
311 system.cpu.l2cache.tags.warmup_cycle 320350195000 # Cycle when the warmup percentage was hit.
312 system.cpu.l2cache.tags.occ_blocks::writebacks 11.856683 # Average occupied blocks per requestor
313 system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.308015 # Average occupied blocks per requestor
314 system.cpu.l2cache.tags.occ_blocks::cpu.data 31708.495772 # Average occupied blocks per requestor
315 system.cpu.l2cache.tags.occ_percent::writebacks 0.000362 # Average percentage of cache occupancy
316 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000772 # Average percentage of cache occupancy
317 system.cpu.l2cache.tags.occ_percent::cpu.data 0.967666 # Average percentage of cache occupancy
318 system.cpu.l2cache.tags.occ_percent::total 0.968801 # Average percentage of cache occupancy
319 system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id
320 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
321 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 435 # Occupied blocks per task id
322 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3097 # Occupied blocks per task id
323 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 786 # Occupied blocks per task id
324 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 28399 # Occupied blocks per task id
325 system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
326 system.cpu.l2cache.tags.tag_accesses 147746387 # Number of tag accesses
327 system.cpu.l2cache.tags.data_accesses 147746387 # Number of data accesses
328 system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
329 system.cpu.l2cache.WritebackDirty_hits::writebacks 3669049 # number of WritebackDirty hits
330 system.cpu.l2cache.WritebackDirty_hits::total 3669049 # number of WritebackDirty hits
331 system.cpu.l2cache.WritebackClean_hits::writebacks 10 # number of WritebackClean hits
332 system.cpu.l2cache.WritebackClean_hits::total 10 # number of WritebackClean hits
333 system.cpu.l2cache.ReadExReq_hits::cpu.data 1095863 # number of ReadExReq hits
334 system.cpu.l2cache.ReadExReq_hits::total 1095863 # number of ReadExReq hits
335 system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6046986 # number of ReadSharedReq hits
336 system.cpu.l2cache.ReadSharedReq_hits::total 6046986 # number of ReadSharedReq hits
337 system.cpu.l2cache.demand_hits::cpu.data 7142849 # number of demand (read+write) hits
338 system.cpu.l2cache.demand_hits::total 7142849 # number of demand (read+write) hits
339 system.cpu.l2cache.overall_hits::cpu.data 7142849 # number of overall hits
340 system.cpu.l2cache.overall_hits::total 7142849 # number of overall hits
341 system.cpu.l2cache.ReadExReq_misses::cpu.data 793964 # number of ReadExReq misses
342 system.cpu.l2cache.ReadExReq_misses::total 793964 # number of ReadExReq misses
343 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 675 # number of ReadCleanReq misses
344 system.cpu.l2cache.ReadCleanReq_misses::total 675 # number of ReadCleanReq misses
345 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1175864 # number of ReadSharedReq misses
346 system.cpu.l2cache.ReadSharedReq_misses::total 1175864 # number of ReadSharedReq misses
347 system.cpu.l2cache.demand_misses::cpu.inst 675 # number of demand (read+write) misses
348 system.cpu.l2cache.demand_misses::cpu.data 1969828 # number of demand (read+write) misses
349 system.cpu.l2cache.demand_misses::total 1970503 # number of demand (read+write) misses
350 system.cpu.l2cache.overall_misses::cpu.inst 675 # number of overall misses
351 system.cpu.l2cache.overall_misses::cpu.data 1969828 # number of overall misses
352 system.cpu.l2cache.overall_misses::total 1970503 # number of overall misses
353 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 48034822000 # number of ReadExReq miss cycles
354 system.cpu.l2cache.ReadExReq_miss_latency::total 48034822000 # number of ReadExReq miss cycles
355 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 40839500 # number of ReadCleanReq miss cycles
356 system.cpu.l2cache.ReadCleanReq_miss_latency::total 40839500 # number of ReadCleanReq miss cycles
357 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 71139776000 # number of ReadSharedReq miss cycles
358 system.cpu.l2cache.ReadSharedReq_miss_latency::total 71139776000 # number of ReadSharedReq miss cycles
359 system.cpu.l2cache.demand_miss_latency::cpu.inst 40839500 # number of demand (read+write) miss cycles
360 system.cpu.l2cache.demand_miss_latency::cpu.data 119174598000 # number of demand (read+write) miss cycles
361 system.cpu.l2cache.demand_miss_latency::total 119215437500 # number of demand (read+write) miss cycles
362 system.cpu.l2cache.overall_miss_latency::cpu.inst 40839500 # number of overall miss cycles
363 system.cpu.l2cache.overall_miss_latency::cpu.data 119174598000 # number of overall miss cycles
364 system.cpu.l2cache.overall_miss_latency::total 119215437500 # number of overall miss cycles
365 system.cpu.l2cache.WritebackDirty_accesses::writebacks 3669049 # number of WritebackDirty accesses(hits+misses)
366 system.cpu.l2cache.WritebackDirty_accesses::total 3669049 # number of WritebackDirty accesses(hits+misses)
367 system.cpu.l2cache.WritebackClean_accesses::writebacks 10 # number of WritebackClean accesses(hits+misses)
368 system.cpu.l2cache.WritebackClean_accesses::total 10 # number of WritebackClean accesses(hits+misses)
369 system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889827 # number of ReadExReq accesses(hits+misses)
370 system.cpu.l2cache.ReadExReq_accesses::total 1889827 # number of ReadExReq accesses(hits+misses)
371 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 675 # number of ReadCleanReq accesses(hits+misses)
372 system.cpu.l2cache.ReadCleanReq_accesses::total 675 # number of ReadCleanReq accesses(hits+misses)
373 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7222850 # number of ReadSharedReq accesses(hits+misses)
374 system.cpu.l2cache.ReadSharedReq_accesses::total 7222850 # number of ReadSharedReq accesses(hits+misses)
375 system.cpu.l2cache.demand_accesses::cpu.inst 675 # number of demand (read+write) accesses
376 system.cpu.l2cache.demand_accesses::cpu.data 9112677 # number of demand (read+write) accesses
377 system.cpu.l2cache.demand_accesses::total 9113352 # number of demand (read+write) accesses
378 system.cpu.l2cache.overall_accesses::cpu.inst 675 # number of overall (read+write) accesses
379 system.cpu.l2cache.overall_accesses::cpu.data 9112677 # number of overall (read+write) accesses
380 system.cpu.l2cache.overall_accesses::total 9113352 # number of overall (read+write) accesses
381 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.420125 # miss rate for ReadExReq accesses
382 system.cpu.l2cache.ReadExReq_miss_rate::total 0.420125 # miss rate for ReadExReq accesses
383 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses
384 system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses
385 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.162798 # miss rate for ReadSharedReq accesses
386 system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.162798 # miss rate for ReadSharedReq accesses
387 system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
388 system.cpu.l2cache.demand_miss_rate::cpu.data 0.216163 # miss rate for demand accesses
389 system.cpu.l2cache.demand_miss_rate::total 0.216222 # miss rate for demand accesses
390 system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
391 system.cpu.l2cache.overall_miss_rate::cpu.data 0.216163 # miss rate for overall accesses
392 system.cpu.l2cache.overall_miss_rate::total 0.216222 # miss rate for overall accesses
393 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency
394 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency
395 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60502.962963 # average ReadCleanReq miss latency
396 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60502.962963 # average ReadCleanReq miss latency
397 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500.003402 # average ReadSharedReq miss latency
398 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500.003402 # average ReadSharedReq miss latency
399 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60502.962963 # average overall miss latency
400 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500.002031 # average overall miss latency
401 system.cpu.l2cache.demand_avg_miss_latency::total 60500.003045 # average overall miss latency
402 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60502.962963 # average overall miss latency
403 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500.002031 # average overall miss latency
404 system.cpu.l2cache.overall_avg_miss_latency::total 60500.003045 # average overall miss latency
405 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
406 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
407 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
408 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
409 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
410 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
411 system.cpu.l2cache.writebacks::writebacks 1032938 # number of writebacks
412 system.cpu.l2cache.writebacks::total 1032938 # number of writebacks
413 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 213 # number of CleanEvict MSHR misses
414 system.cpu.l2cache.CleanEvict_mshr_misses::total 213 # number of CleanEvict MSHR misses
415 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 793964 # number of ReadExReq MSHR misses
416 system.cpu.l2cache.ReadExReq_mshr_misses::total 793964 # number of ReadExReq MSHR misses
417 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 675 # number of ReadCleanReq MSHR misses
418 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 675 # number of ReadCleanReq MSHR misses
419 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1175864 # number of ReadSharedReq MSHR misses
420 system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1175864 # number of ReadSharedReq MSHR misses
421 system.cpu.l2cache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses
422 system.cpu.l2cache.demand_mshr_misses::cpu.data 1969828 # number of demand (read+write) MSHR misses
423 system.cpu.l2cache.demand_mshr_misses::total 1970503 # number of demand (read+write) MSHR misses
424 system.cpu.l2cache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses
425 system.cpu.l2cache.overall_mshr_misses::cpu.data 1969828 # number of overall MSHR misses
426 system.cpu.l2cache.overall_mshr_misses::total 1970503 # number of overall MSHR misses
427 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 40095182000 # number of ReadExReq MSHR miss cycles
428 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 40095182000 # number of ReadExReq MSHR miss cycles
429 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 34089500 # number of ReadCleanReq MSHR miss cycles
430 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 34089500 # number of ReadCleanReq MSHR miss cycles
431 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59381136000 # number of ReadSharedReq MSHR miss cycles
432 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59381136000 # number of ReadSharedReq MSHR miss cycles
433 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34089500 # number of demand (read+write) MSHR miss cycles
434 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 99476318000 # number of demand (read+write) MSHR miss cycles
435 system.cpu.l2cache.demand_mshr_miss_latency::total 99510407500 # number of demand (read+write) MSHR miss cycles
436 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34089500 # number of overall MSHR miss cycles
437 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 99476318000 # number of overall MSHR miss cycles
438 system.cpu.l2cache.overall_mshr_miss_latency::total 99510407500 # number of overall MSHR miss cycles
439 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
440 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
441 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.420125 # mshr miss rate for ReadExReq accesses
442 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.420125 # mshr miss rate for ReadExReq accesses
443 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
444 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses
445 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162798 # mshr miss rate for ReadSharedReq accesses
446 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162798 # mshr miss rate for ReadSharedReq accesses
447 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
448 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216163 # mshr miss rate for demand accesses
449 system.cpu.l2cache.demand_mshr_miss_rate::total 0.216222 # mshr miss rate for demand accesses
450 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
451 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216163 # mshr miss rate for overall accesses
452 system.cpu.l2cache.overall_mshr_miss_rate::total 0.216222 # mshr miss rate for overall accesses
453 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency
454 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency
455 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50502.962963 # average ReadCleanReq mshr miss latency
456 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50502.962963 # average ReadCleanReq mshr miss latency
457 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500.003402 # average ReadSharedReq mshr miss latency
458 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500.003402 # average ReadSharedReq mshr miss latency
459 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50502.962963 # average overall mshr miss latency
460 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.002031 # average overall mshr miss latency
461 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.003045 # average overall mshr miss latency
462 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50502.962963 # average overall mshr miss latency
463 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.002031 # average overall mshr miss latency
464 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.003045 # average overall mshr miss latency
465 system.cpu.toL2Bus.snoop_filter.tot_requests 18221943 # Total number of requests made to the snoop filter.
466 system.cpu.toL2Bus.snoop_filter.hit_single_requests 9108591 # Number of requests hitting in the snoop filter with a single holder of the requested data.
467 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
468 system.cpu.toL2Bus.snoop_filter.tot_snoops 1186 # Total number of snoops made to the snoop filter.
469 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1186 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
470 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
471 system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
472 system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution
473 system.cpu.toL2Bus.trans_dist::WritebackDirty 4701987 # Transaction distribution
474 system.cpu.toL2Bus.trans_dist::WritebackClean 10 # Transaction distribution
475 system.cpu.toL2Bus.trans_dist::CleanEvict 6344669 # Transaction distribution
476 system.cpu.toL2Bus.trans_dist::ReadExReq 1889827 # Transaction distribution
477 system.cpu.toL2Bus.trans_dist::ReadExResp 1889827 # Transaction distribution
478 system.cpu.toL2Bus.trans_dist::ReadCleanReq 675 # Transaction distribution
479 system.cpu.toL2Bus.trans_dist::ReadSharedReq 7222850 # Transaction distribution
480 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1360 # Packet count per connected master and slave (bytes)
481 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27333935 # Packet count per connected master and slave (bytes)
482 system.cpu.toL2Bus.pkt_count::total 27335295 # Packet count per connected master and slave (bytes)
483 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43840 # Cumulative packet size per connected master and slave (bytes)
484 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818030464 # Cumulative packet size per connected master and slave (bytes)
485 system.cpu.toL2Bus.pkt_size::total 818074304 # Cumulative packet size per connected master and slave (bytes)
486 system.cpu.toL2Bus.snoops 1938075 # Total snoops (count)
487 system.cpu.toL2Bus.snoopTraffic 66108032 # Total snoop traffic (bytes)
488 system.cpu.toL2Bus.snoop_fanout::samples 11051427 # Request fanout histogram
489 system.cpu.toL2Bus.snoop_fanout::mean 0.000107 # Request fanout histogram
490 system.cpu.toL2Bus.snoop_fanout::stdev 0.010359 # Request fanout histogram
491 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
492 system.cpu.toL2Bus.snoop_fanout::0 11050241 99.99% 99.99% # Request fanout histogram
493 system.cpu.toL2Bus.snoop_fanout::1 1186 0.01% 100.00% # Request fanout histogram
494 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
495 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
496 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
497 system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
498 system.cpu.toL2Bus.snoop_fanout::total 11051427 # Request fanout histogram
499 system.cpu.toL2Bus.reqLayer0.occupancy 12780030500 # Layer occupancy (ticks)
500 system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
501 system.cpu.toL2Bus.respLayer0.occupancy 1012500 # Layer occupancy (ticks)
502 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
503 system.cpu.toL2Bus.respLayer1.occupancy 13669015500 # Layer occupancy (ticks)
504 system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
505 system.membus.snoop_filter.tot_requests 3907605 # Total number of requests made to the snoop filter.
506 system.membus.snoop_filter.hit_single_requests 1937102 # Number of requests hitting in the snoop filter with a single holder of the requested data.
507 system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
508 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
509 system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
510 system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
511 system.membus.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
512 system.membus.trans_dist::ReadResp 1176539 # Transaction distribution
513 system.membus.trans_dist::WritebackDirty 1032938 # Transaction distribution
514 system.membus.trans_dist::CleanEvict 904164 # Transaction distribution
515 system.membus.trans_dist::ReadExReq 793964 # Transaction distribution
516 system.membus.trans_dist::ReadExResp 793964 # Transaction distribution
517 system.membus.trans_dist::ReadSharedReq 1176539 # Transaction distribution
518 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5878108 # Packet count per connected master and slave (bytes)
519 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5878108 # Packet count per connected master and slave (bytes)
520 system.membus.pkt_count::total 5878108 # Packet count per connected master and slave (bytes)
521 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192220224 # Cumulative packet size per connected master and slave (bytes)
522 system.membus.pkt_size_system.cpu.l2cache.mem_side::total 192220224 # Cumulative packet size per connected master and slave (bytes)
523 system.membus.pkt_size::total 192220224 # Cumulative packet size per connected master and slave (bytes)
524 system.membus.snoops 0 # Total snoops (count)
525 system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
526 system.membus.snoop_fanout::samples 1970503 # Request fanout histogram
527 system.membus.snoop_fanout::mean 0 # Request fanout histogram
528 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
529 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
530 system.membus.snoop_fanout::0 1970503 100.00% 100.00% # Request fanout histogram
531 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
532 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
533 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
534 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
535 system.membus.snoop_fanout::total 1970503 # Request fanout histogram
536 system.membus.reqLayer0.occupancy 8039359500 # Layer occupancy (ticks)
537 system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
538 system.membus.respLayer1.occupancy 9852515000 # Layer occupancy (ticks)
539 system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
541 ---------- End Simulation Statistics ----------
projects / gem5.git / blob