2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 5.882581 # Number of seconds simulated
4 sim_ticks 5882580526000 # Number of ticks simulated
5 final_tick 5882580526000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 912016 # Simulator instruction rate (inst/s)
8 host_op_rate 1421004 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 1783532526 # Simulator tick rate (ticks/s)
10 host_mem_usage 308940 # Number of bytes of host memory used
11 host_seconds 3298.27 # Real time elapsed on the host
12 sim_insts 3008081022 # Number of instructions simulated
13 sim_ops 4686862596 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 125326976 # Number of bytes read from this memory
18 system.physmem.bytes_read::total 125370176 # Number of bytes read from this memory
19 system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory
20 system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory
21 system.physmem.bytes_written::writebacks 65178944 # Number of bytes written to this memory
22 system.physmem.bytes_written::total 65178944 # Number of bytes written to this memory
23 system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory
24 system.physmem.num_reads::cpu.data 1958234 # Number of read requests responded to by this memory
25 system.physmem.num_reads::total 1958909 # Number of read requests responded to by this memory
26 system.physmem.num_writes::writebacks 1018421 # Number of write requests responded to by this memory
27 system.physmem.num_writes::total 1018421 # Number of write requests responded to by this memory
28 system.physmem.bw_read::cpu.inst 7344 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_read::cpu.data 21304762 # Total read bandwidth from this memory (bytes/s)
30 system.physmem.bw_read::total 21312105 # Total read bandwidth from this memory (bytes/s)
31 system.physmem.bw_inst_read::cpu.inst 7344 # Instruction read bandwidth from this memory (bytes/s)
32 system.physmem.bw_inst_read::total 7344 # Instruction read bandwidth from this memory (bytes/s)
33 system.physmem.bw_write::writebacks 11079992 # Write bandwidth from this memory (bytes/s)
34 system.physmem.bw_write::total 11079992 # Write bandwidth from this memory (bytes/s)
35 system.physmem.bw_total::writebacks 11079992 # Total bandwidth to/from this memory (bytes/s)
36 system.physmem.bw_total::cpu.inst 7344 # Total bandwidth to/from this memory (bytes/s)
37 system.physmem.bw_total::cpu.data 21304762 # Total bandwidth to/from this memory (bytes/s)
38 system.physmem.bw_total::total 32392097 # Total bandwidth to/from this memory (bytes/s)
39 system.membus.trans_dist::ReadReq 1177614 # Transaction distribution
40 system.membus.trans_dist::ReadResp 1177614 # Transaction distribution
41 system.membus.trans_dist::Writeback 1018421 # Transaction distribution
42 system.membus.trans_dist::ReadExReq 781295 # Transaction distribution
43 system.membus.trans_dist::ReadExResp 781295 # Transaction distribution
44 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4936239 # Packet count per connected master and slave (bytes)
45 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4936239 # Packet count per connected master and slave (bytes)
46 system.membus.pkt_count::total 4936239 # Packet count per connected master and slave (bytes)
47 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190549120 # Cumulative packet size per connected master and slave (bytes)
48 system.membus.pkt_size_system.cpu.l2cache.mem_side::total 190549120 # Cumulative packet size per connected master and slave (bytes)
49 system.membus.pkt_size::total 190549120 # Cumulative packet size per connected master and slave (bytes)
50 system.membus.snoops 0 # Total snoops (count)
51 system.membus.snoop_fanout::samples 2977330 # Request fanout histogram
52 system.membus.snoop_fanout::mean 0 # Request fanout histogram
53 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
54 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
55 system.membus.snoop_fanout::0 2977330 100.00% 100.00% # Request fanout histogram
56 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
57 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
58 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
59 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
60 system.membus.snoop_fanout::total 2977330 # Request fanout histogram
61 system.membus.reqLayer0.occupancy 11124698000 # Layer occupancy (ticks)
62 system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
63 system.membus.respLayer1.occupancy 17630181000 # Layer occupancy (ticks)
64 system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
65 system.cpu_clk_domain.clock 500 # Clock period in ticks
66 system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
67 system.cpu.workload.num_syscalls 46 # Number of system calls
68 system.cpu.numCycles 11765161052 # number of cpu cycles simulated
69 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
70 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
71 system.cpu.committedInsts 3008081022 # Number of instructions committed
72 system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed
73 system.cpu.num_int_alu_accesses 4684368009 # Number of integer alu accesses
74 system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
75 system.cpu.num_func_calls 33534539 # number of times a function call or return occured
76 system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls
77 system.cpu.num_int_insts 4684368009 # number of integer instructions
78 system.cpu.num_fp_insts 0 # number of float instructions
79 system.cpu.num_int_register_reads 10688755601 # number of times the integer registers were read
80 system.cpu.num_int_register_writes 3999841477 # number of times the integer registers were written
81 system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
82 system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
83 system.cpu.num_cc_register_reads 1226718827 # number of times the CC registers were read
84 system.cpu.num_cc_register_writes 1355930461 # number of times the CC registers were written
85 system.cpu.num_mem_refs 1677713084 # number of memory refs
86 system.cpu.num_load_insts 1239184746 # Number of load instructions
87 system.cpu.num_store_insts 438528338 # Number of store instructions
88 system.cpu.num_idle_cycles 0 # Number of idle cycles
89 system.cpu.num_busy_cycles 11765161052 # Number of busy cycles
90 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
91 system.cpu.idle_fraction 0 # Percentage of idle cycles
92 system.cpu.Branches 248500691 # Number of branches fetched
93 system.cpu.op_class::No_OpClass 2494522 0.05% 0.05% # Class of executed instruction
94 system.cpu.op_class::IntAlu 3006647871 64.15% 64.20% # Class of executed instruction
95 system.cpu.op_class::IntMult 6215 0.00% 64.20% # Class of executed instruction
96 system.cpu.op_class::IntDiv 904 0.00% 64.20% # Class of executed instruction
97 system.cpu.op_class::FloatAdd 0 0.00% 64.20% # Class of executed instruction
98 system.cpu.op_class::FloatCmp 0 0.00% 64.20% # Class of executed instruction
99 system.cpu.op_class::FloatCvt 0 0.00% 64.20% # Class of executed instruction
100 system.cpu.op_class::FloatMult 0 0.00% 64.20% # Class of executed instruction
101 system.cpu.op_class::FloatDiv 0 0.00% 64.20% # Class of executed instruction
102 system.cpu.op_class::FloatSqrt 0 0.00% 64.20% # Class of executed instruction
103 system.cpu.op_class::SimdAdd 0 0.00% 64.20% # Class of executed instruction
104 system.cpu.op_class::SimdAddAcc 0 0.00% 64.20% # Class of executed instruction
105 system.cpu.op_class::SimdAlu 0 0.00% 64.20% # Class of executed instruction
106 system.cpu.op_class::SimdCmp 0 0.00% 64.20% # Class of executed instruction
107 system.cpu.op_class::SimdCvt 0 0.00% 64.20% # Class of executed instruction
108 system.cpu.op_class::SimdMisc 0 0.00% 64.20% # Class of executed instruction
109 system.cpu.op_class::SimdMult 0 0.00% 64.20% # Class of executed instruction
110 system.cpu.op_class::SimdMultAcc 0 0.00% 64.20% # Class of executed instruction
111 system.cpu.op_class::SimdShift 0 0.00% 64.20% # Class of executed instruction
112 system.cpu.op_class::SimdShiftAcc 0 0.00% 64.20% # Class of executed instruction
113 system.cpu.op_class::SimdSqrt 0 0.00% 64.20% # Class of executed instruction
114 system.cpu.op_class::SimdFloatAdd 0 0.00% 64.20% # Class of executed instruction
115 system.cpu.op_class::SimdFloatAlu 0 0.00% 64.20% # Class of executed instruction
116 system.cpu.op_class::SimdFloatCmp 0 0.00% 64.20% # Class of executed instruction
117 system.cpu.op_class::SimdFloatCvt 0 0.00% 64.20% # Class of executed instruction
118 system.cpu.op_class::SimdFloatDiv 0 0.00% 64.20% # Class of executed instruction
119 system.cpu.op_class::SimdFloatMisc 0 0.00% 64.20% # Class of executed instruction
120 system.cpu.op_class::SimdFloatMult 0 0.00% 64.20% # Class of executed instruction
121 system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.20% # Class of executed instruction
122 system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.20% # Class of executed instruction
123 system.cpu.op_class::MemRead 1239184746 26.44% 90.64% # Class of executed instruction
124 system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Class of executed instruction
125 system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
126 system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
127 system.cpu.op_class::total 4686862596 # Class of executed instruction
128 system.cpu.icache.tags.replacements 10 # number of replacements
129 system.cpu.icache.tags.tagsinuse 555.705054 # Cycle average of tags in use
130 system.cpu.icache.tags.total_refs 4013232208 # Total number of references to valid blocks.
131 system.cpu.icache.tags.sampled_refs 675 # Sample count of references to valid blocks.
132 system.cpu.icache.tags.avg_refs 5945529.197037 # Average number of references to valid blocks.
133 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
134 system.cpu.icache.tags.occ_blocks::cpu.inst 555.705054 # Average occupied blocks per requestor
135 system.cpu.icache.tags.occ_percent::cpu.inst 0.271340 # Average percentage of cache occupancy
136 system.cpu.icache.tags.occ_percent::total 0.271340 # Average percentage of cache occupancy
137 system.cpu.icache.tags.occ_task_id_blocks::1024 665 # Occupied blocks per task id
138 system.cpu.icache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id
139 system.cpu.icache.tags.age_task_id_blocks_1024::4 632 # Occupied blocks per task id
140 system.cpu.icache.tags.occ_task_id_percent::1024 0.324707 # Percentage of cache occupancy per task id
141 system.cpu.icache.tags.tag_accesses 8026466441 # Number of tag accesses
142 system.cpu.icache.tags.data_accesses 8026466441 # Number of data accesses
143 system.cpu.icache.ReadReq_hits::cpu.inst 4013232208 # number of ReadReq hits
144 system.cpu.icache.ReadReq_hits::total 4013232208 # number of ReadReq hits
145 system.cpu.icache.demand_hits::cpu.inst 4013232208 # number of demand (read+write) hits
146 system.cpu.icache.demand_hits::total 4013232208 # number of demand (read+write) hits
147 system.cpu.icache.overall_hits::cpu.inst 4013232208 # number of overall hits
148 system.cpu.icache.overall_hits::total 4013232208 # number of overall hits
149 system.cpu.icache.ReadReq_misses::cpu.inst 675 # number of ReadReq misses
150 system.cpu.icache.ReadReq_misses::total 675 # number of ReadReq misses
151 system.cpu.icache.demand_misses::cpu.inst 675 # number of demand (read+write) misses
152 system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses
153 system.cpu.icache.overall_misses::cpu.inst 675 # number of overall misses
154 system.cpu.icache.overall_misses::total 675 # number of overall misses
155 system.cpu.icache.ReadReq_miss_latency::cpu.inst 37156000 # number of ReadReq miss cycles
156 system.cpu.icache.ReadReq_miss_latency::total 37156000 # number of ReadReq miss cycles
157 system.cpu.icache.demand_miss_latency::cpu.inst 37156000 # number of demand (read+write) miss cycles
158 system.cpu.icache.demand_miss_latency::total 37156000 # number of demand (read+write) miss cycles
159 system.cpu.icache.overall_miss_latency::cpu.inst 37156000 # number of overall miss cycles
160 system.cpu.icache.overall_miss_latency::total 37156000 # number of overall miss cycles
161 system.cpu.icache.ReadReq_accesses::cpu.inst 4013232883 # number of ReadReq accesses(hits+misses)
162 system.cpu.icache.ReadReq_accesses::total 4013232883 # number of ReadReq accesses(hits+misses)
163 system.cpu.icache.demand_accesses::cpu.inst 4013232883 # number of demand (read+write) accesses
164 system.cpu.icache.demand_accesses::total 4013232883 # number of demand (read+write) accesses
165 system.cpu.icache.overall_accesses::cpu.inst 4013232883 # number of overall (read+write) accesses
166 system.cpu.icache.overall_accesses::total 4013232883 # number of overall (read+write) accesses
167 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses
168 system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses
169 system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses
170 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
171 system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
172 system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses
173 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55045.925926 # average ReadReq miss latency
174 system.cpu.icache.ReadReq_avg_miss_latency::total 55045.925926 # average ReadReq miss latency
175 system.cpu.icache.demand_avg_miss_latency::cpu.inst 55045.925926 # average overall miss latency
176 system.cpu.icache.demand_avg_miss_latency::total 55045.925926 # average overall miss latency
177 system.cpu.icache.overall_avg_miss_latency::cpu.inst 55045.925926 # average overall miss latency
178 system.cpu.icache.overall_avg_miss_latency::total 55045.925926 # average overall miss latency
179 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
180 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
181 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
182 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
183 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
184 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
185 system.cpu.icache.fast_writes 0 # number of fast writes performed
186 system.cpu.icache.cache_copies 0 # number of cache copies performed
187 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses
188 system.cpu.icache.ReadReq_mshr_misses::total 675 # number of ReadReq MSHR misses
189 system.cpu.icache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses
190 system.cpu.icache.demand_mshr_misses::total 675 # number of demand (read+write) MSHR misses
191 system.cpu.icache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses
192 system.cpu.icache.overall_mshr_misses::total 675 # number of overall MSHR misses
193 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35806000 # number of ReadReq MSHR miss cycles
194 system.cpu.icache.ReadReq_mshr_miss_latency::total 35806000 # number of ReadReq MSHR miss cycles
195 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35806000 # number of demand (read+write) MSHR miss cycles
196 system.cpu.icache.demand_mshr_miss_latency::total 35806000 # number of demand (read+write) MSHR miss cycles
197 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35806000 # number of overall MSHR miss cycles
198 system.cpu.icache.overall_mshr_miss_latency::total 35806000 # number of overall MSHR miss cycles
199 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
200 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
201 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
202 system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
203 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
204 system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses
205 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53045.925926 # average ReadReq mshr miss latency
206 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53045.925926 # average ReadReq mshr miss latency
207 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53045.925926 # average overall mshr miss latency
208 system.cpu.icache.demand_avg_mshr_miss_latency::total 53045.925926 # average overall mshr miss latency
209 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53045.925926 # average overall mshr miss latency
210 system.cpu.icache.overall_avg_mshr_miss_latency::total 53045.925926 # average overall mshr miss latency
211 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
212 system.cpu.l2cache.tags.replacements 1926197 # number of replacements
213 system.cpu.l2cache.tags.tagsinuse 31136.249379 # Cycle average of tags in use
214 system.cpu.l2cache.tags.total_refs 8965026 # Total number of references to valid blocks.
215 system.cpu.l2cache.tags.sampled_refs 1955980 # Sample count of references to valid blocks.
216 system.cpu.l2cache.tags.avg_refs 4.583393 # Average number of references to valid blocks.
217 system.cpu.l2cache.tags.warmup_cycle 340768635000 # Cycle when the warmup percentage was hit.
218 system.cpu.l2cache.tags.occ_blocks::writebacks 15396.795533 # Average occupied blocks per requestor
219 system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.641016 # Average occupied blocks per requestor
220 system.cpu.l2cache.tags.occ_blocks::cpu.data 15713.812830 # Average occupied blocks per requestor
221 system.cpu.l2cache.tags.occ_percent::writebacks 0.469873 # Average percentage of cache occupancy
222 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000783 # Average percentage of cache occupancy
223 system.cpu.l2cache.tags.occ_percent::cpu.data 0.479548 # Average percentage of cache occupancy
224 system.cpu.l2cache.tags.occ_percent::total 0.950203 # Average percentage of cache occupancy
225 system.cpu.l2cache.tags.occ_task_id_blocks::1024 29783 # Occupied blocks per task id
226 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
227 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
228 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 996 # Occupied blocks per task id
229 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 743 # Occupied blocks per task id
230 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27921 # Occupied blocks per task id
231 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908905 # Percentage of cache occupancy per task id
232 system.cpu.l2cache.tags.tag_accesses 106336271 # Number of tag accesses
233 system.cpu.l2cache.tags.data_accesses 106336271 # Number of data accesses
234 system.cpu.l2cache.ReadReq_hits::cpu.data 6045911 # number of ReadReq hits
235 system.cpu.l2cache.ReadReq_hits::total 6045911 # number of ReadReq hits
236 system.cpu.l2cache.Writeback_hits::writebacks 3697956 # number of Writeback hits
237 system.cpu.l2cache.Writeback_hits::total 3697956 # number of Writeback hits
238 system.cpu.l2cache.ReadExReq_hits::cpu.data 1108532 # number of ReadExReq hits
239 system.cpu.l2cache.ReadExReq_hits::total 1108532 # number of ReadExReq hits
240 system.cpu.l2cache.demand_hits::cpu.data 7154443 # number of demand (read+write) hits
241 system.cpu.l2cache.demand_hits::total 7154443 # number of demand (read+write) hits
242 system.cpu.l2cache.overall_hits::cpu.data 7154443 # number of overall hits
243 system.cpu.l2cache.overall_hits::total 7154443 # number of overall hits
244 system.cpu.l2cache.ReadReq_misses::cpu.inst 675 # number of ReadReq misses
245 system.cpu.l2cache.ReadReq_misses::cpu.data 1176939 # number of ReadReq misses
246 system.cpu.l2cache.ReadReq_misses::total 1177614 # number of ReadReq misses
247 system.cpu.l2cache.ReadExReq_misses::cpu.data 781295 # number of ReadExReq misses
248 system.cpu.l2cache.ReadExReq_misses::total 781295 # number of ReadExReq misses
249 system.cpu.l2cache.demand_misses::cpu.inst 675 # number of demand (read+write) misses
250 system.cpu.l2cache.demand_misses::cpu.data 1958234 # number of demand (read+write) misses
251 system.cpu.l2cache.demand_misses::total 1958909 # number of demand (read+write) misses
252 system.cpu.l2cache.overall_misses::cpu.inst 675 # number of overall misses
253 system.cpu.l2cache.overall_misses::cpu.data 1958234 # number of overall misses
254 system.cpu.l2cache.overall_misses::total 1958909 # number of overall misses
255 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35131000 # number of ReadReq miss cycles
256 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61200881000 # number of ReadReq miss cycles
257 system.cpu.l2cache.ReadReq_miss_latency::total 61236012000 # number of ReadReq miss cycles
258 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40627414000 # number of ReadExReq miss cycles
259 system.cpu.l2cache.ReadExReq_miss_latency::total 40627414000 # number of ReadExReq miss cycles
260 system.cpu.l2cache.demand_miss_latency::cpu.inst 35131000 # number of demand (read+write) miss cycles
261 system.cpu.l2cache.demand_miss_latency::cpu.data 101828295000 # number of demand (read+write) miss cycles
262 system.cpu.l2cache.demand_miss_latency::total 101863426000 # number of demand (read+write) miss cycles
263 system.cpu.l2cache.overall_miss_latency::cpu.inst 35131000 # number of overall miss cycles
264 system.cpu.l2cache.overall_miss_latency::cpu.data 101828295000 # number of overall miss cycles
265 system.cpu.l2cache.overall_miss_latency::total 101863426000 # number of overall miss cycles
266 system.cpu.l2cache.ReadReq_accesses::cpu.inst 675 # number of ReadReq accesses(hits+misses)
267 system.cpu.l2cache.ReadReq_accesses::cpu.data 7222850 # number of ReadReq accesses(hits+misses)
268 system.cpu.l2cache.ReadReq_accesses::total 7223525 # number of ReadReq accesses(hits+misses)
269 system.cpu.l2cache.Writeback_accesses::writebacks 3697956 # number of Writeback accesses(hits+misses)
270 system.cpu.l2cache.Writeback_accesses::total 3697956 # number of Writeback accesses(hits+misses)
271 system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889827 # number of ReadExReq accesses(hits+misses)
272 system.cpu.l2cache.ReadExReq_accesses::total 1889827 # number of ReadExReq accesses(hits+misses)
273 system.cpu.l2cache.demand_accesses::cpu.inst 675 # number of demand (read+write) accesses
274 system.cpu.l2cache.demand_accesses::cpu.data 9112677 # number of demand (read+write) accesses
275 system.cpu.l2cache.demand_accesses::total 9113352 # number of demand (read+write) accesses
276 system.cpu.l2cache.overall_accesses::cpu.inst 675 # number of overall (read+write) accesses
277 system.cpu.l2cache.overall_accesses::cpu.data 9112677 # number of overall (read+write) accesses
278 system.cpu.l2cache.overall_accesses::total 9113352 # number of overall (read+write) accesses
279 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
280 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.162947 # miss rate for ReadReq accesses
281 system.cpu.l2cache.ReadReq_miss_rate::total 0.163025 # miss rate for ReadReq accesses
282 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413421 # miss rate for ReadExReq accesses
283 system.cpu.l2cache.ReadExReq_miss_rate::total 0.413421 # miss rate for ReadExReq accesses
284 system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
285 system.cpu.l2cache.demand_miss_rate::cpu.data 0.214891 # miss rate for demand accesses
286 system.cpu.l2cache.demand_miss_rate::total 0.214949 # miss rate for demand accesses
287 system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
288 system.cpu.l2cache.overall_miss_rate::cpu.data 0.214891 # miss rate for overall accesses
289 system.cpu.l2cache.overall_miss_rate::total 0.214949 # miss rate for overall accesses
290 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52045.925926 # average ReadReq miss latency
291 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.045032 # average ReadReq miss latency
292 system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.071331 # average ReadReq miss latency
293 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.094715 # average ReadExReq miss latency
294 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.094715 # average ReadExReq miss latency
295 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52045.925926 # average overall miss latency
296 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.064854 # average overall miss latency
297 system.cpu.l2cache.demand_avg_miss_latency::total 52000.080657 # average overall miss latency
298 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52045.925926 # average overall miss latency
299 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.064854 # average overall miss latency
300 system.cpu.l2cache.overall_avg_miss_latency::total 52000.080657 # average overall miss latency
301 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
302 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
303 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
304 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
305 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
306 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
307 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
308 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
309 system.cpu.l2cache.writebacks::writebacks 1018421 # number of writebacks
310 system.cpu.l2cache.writebacks::total 1018421 # number of writebacks
311 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses
312 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1176939 # number of ReadReq MSHR misses
313 system.cpu.l2cache.ReadReq_mshr_misses::total 1177614 # number of ReadReq MSHR misses
314 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 781295 # number of ReadExReq MSHR misses
315 system.cpu.l2cache.ReadExReq_mshr_misses::total 781295 # number of ReadExReq MSHR misses
316 system.cpu.l2cache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses
317 system.cpu.l2cache.demand_mshr_misses::cpu.data 1958234 # number of demand (read+write) MSHR misses
318 system.cpu.l2cache.demand_mshr_misses::total 1958909 # number of demand (read+write) MSHR misses
319 system.cpu.l2cache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses
320 system.cpu.l2cache.overall_mshr_misses::cpu.data 1958234 # number of overall MSHR misses
321 system.cpu.l2cache.overall_mshr_misses::total 1958909 # number of overall MSHR misses
322 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27031000 # number of ReadReq MSHR miss cycles
323 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47077613000 # number of ReadReq MSHR miss cycles
324 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47104644000 # number of ReadReq MSHR miss cycles
325 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31251874000 # number of ReadExReq MSHR miss cycles
326 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31251874000 # number of ReadExReq MSHR miss cycles
327 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27031000 # number of demand (read+write) MSHR miss cycles
328 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78329487000 # number of demand (read+write) MSHR miss cycles
329 system.cpu.l2cache.demand_mshr_miss_latency::total 78356518000 # number of demand (read+write) MSHR miss cycles
330 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27031000 # number of overall MSHR miss cycles
331 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78329487000 # number of overall MSHR miss cycles
332 system.cpu.l2cache.overall_mshr_miss_latency::total 78356518000 # number of overall MSHR miss cycles
333 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
334 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162947 # mshr miss rate for ReadReq accesses
335 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163025 # mshr miss rate for ReadReq accesses
336 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413421 # mshr miss rate for ReadExReq accesses
337 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413421 # mshr miss rate for ReadExReq accesses
338 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
339 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214891 # mshr miss rate for demand accesses
340 system.cpu.l2cache.demand_mshr_miss_rate::total 0.214949 # mshr miss rate for demand accesses
341 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
342 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214891 # mshr miss rate for overall accesses
343 system.cpu.l2cache.overall_mshr_miss_rate::total 0.214949 # mshr miss rate for overall accesses
344 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40045.925926 # average ReadReq mshr miss latency
345 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.045032 # average ReadReq mshr miss latency
346 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.071331 # average ReadReq mshr miss latency
347 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.094715 # average ReadExReq mshr miss latency
348 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.094715 # average ReadExReq mshr miss latency
349 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40045.925926 # average overall mshr miss latency
350 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.064854 # average overall mshr miss latency
351 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.080657 # average overall mshr miss latency
352 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40045.925926 # average overall mshr miss latency
353 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.064854 # average overall mshr miss latency
354 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.080657 # average overall mshr miss latency
355 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
356 system.cpu.dcache.tags.replacements 9108581 # number of replacements
357 system.cpu.dcache.tags.tagsinuse 4084.587030 # Cycle average of tags in use
358 system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks.
359 system.cpu.dcache.tags.sampled_refs 9112677 # Sample count of references to valid blocks.
360 system.cpu.dcache.tags.avg_refs 183.107599 # Average number of references to valid blocks.
361 system.cpu.dcache.tags.warmup_cycle 58853922000 # Cycle when the warmup percentage was hit.
362 system.cpu.dcache.tags.occ_blocks::cpu.data 4084.587030 # Average occupied blocks per requestor
363 system.cpu.dcache.tags.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy
364 system.cpu.dcache.tags.occ_percent::total 0.997214 # Average percentage of cache occupancy
365 system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
366 system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id
367 system.cpu.dcache.tags.age_task_id_blocks_1024::1 926 # Occupied blocks per task id
368 system.cpu.dcache.tags.age_task_id_blocks_1024::2 2744 # Occupied blocks per task id
369 system.cpu.dcache.tags.age_task_id_blocks_1024::3 320 # Occupied blocks per task id
370 system.cpu.dcache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id
371 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
372 system.cpu.dcache.tags.tag_accesses 3364538845 # Number of tag accesses
373 system.cpu.dcache.tags.data_accesses 3364538845 # Number of data accesses
374 system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits
375 system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits
376 system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits
377 system.cpu.dcache.WriteReq_hits::total 436638511 # number of WriteReq hits
378 system.cpu.dcache.demand_hits::cpu.data 1668600407 # number of demand (read+write) hits
379 system.cpu.dcache.demand_hits::total 1668600407 # number of demand (read+write) hits
380 system.cpu.dcache.overall_hits::cpu.data 1668600407 # number of overall hits
381 system.cpu.dcache.overall_hits::total 1668600407 # number of overall hits
382 system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses
383 system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses
384 system.cpu.dcache.WriteReq_misses::cpu.data 1889827 # number of WriteReq misses
385 system.cpu.dcache.WriteReq_misses::total 1889827 # number of WriteReq misses
386 system.cpu.dcache.demand_misses::cpu.data 9112677 # number of demand (read+write) misses
387 system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses
388 system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses
389 system.cpu.dcache.overall_misses::total 9112677 # number of overall misses
390 system.cpu.dcache.ReadReq_miss_latency::cpu.data 143328541000 # number of ReadReq miss cycles
391 system.cpu.dcache.ReadReq_miss_latency::total 143328541000 # number of ReadReq miss cycles
392 system.cpu.dcache.WriteReq_miss_latency::cpu.data 57382215000 # number of WriteReq miss cycles
393 system.cpu.dcache.WriteReq_miss_latency::total 57382215000 # number of WriteReq miss cycles
394 system.cpu.dcache.demand_miss_latency::cpu.data 200710756000 # number of demand (read+write) miss cycles
395 system.cpu.dcache.demand_miss_latency::total 200710756000 # number of demand (read+write) miss cycles
396 system.cpu.dcache.overall_miss_latency::cpu.data 200710756000 # number of overall miss cycles
397 system.cpu.dcache.overall_miss_latency::total 200710756000 # number of overall miss cycles
398 system.cpu.dcache.ReadReq_accesses::cpu.data 1239184746 # number of ReadReq accesses(hits+misses)
399 system.cpu.dcache.ReadReq_accesses::total 1239184746 # number of ReadReq accesses(hits+misses)
400 system.cpu.dcache.WriteReq_accesses::cpu.data 438528338 # number of WriteReq accesses(hits+misses)
401 system.cpu.dcache.WriteReq_accesses::total 438528338 # number of WriteReq accesses(hits+misses)
402 system.cpu.dcache.demand_accesses::cpu.data 1677713084 # number of demand (read+write) accesses
403 system.cpu.dcache.demand_accesses::total 1677713084 # number of demand (read+write) accesses
404 system.cpu.dcache.overall_accesses::cpu.data 1677713084 # number of overall (read+write) accesses
405 system.cpu.dcache.overall_accesses::total 1677713084 # number of overall (read+write) accesses
406 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses
407 system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses
408 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses
409 system.cpu.dcache.WriteReq_miss_rate::total 0.004309 # miss rate for WriteReq accesses
410 system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 # miss rate for demand accesses
411 system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses
412 system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses
413 system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses
414 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19843.765411 # average ReadReq miss latency
415 system.cpu.dcache.ReadReq_avg_miss_latency::total 19843.765411 # average ReadReq miss latency
416 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30363.739644 # average WriteReq miss latency
417 system.cpu.dcache.WriteReq_avg_miss_latency::total 30363.739644 # average WriteReq miss latency
418 system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.443895 # average overall miss latency
419 system.cpu.dcache.demand_avg_miss_latency::total 22025.443895 # average overall miss latency
420 system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.443895 # average overall miss latency
421 system.cpu.dcache.overall_avg_miss_latency::total 22025.443895 # average overall miss latency
422 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
423 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
424 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
425 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
426 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
427 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
428 system.cpu.dcache.fast_writes 0 # number of fast writes performed
429 system.cpu.dcache.cache_copies 0 # number of cache copies performed
430 system.cpu.dcache.writebacks::writebacks 3697956 # number of writebacks
431 system.cpu.dcache.writebacks::total 3697956 # number of writebacks
432 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses
433 system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses
434 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses
435 system.cpu.dcache.WriteReq_mshr_misses::total 1889827 # number of WriteReq MSHR misses
436 system.cpu.dcache.demand_mshr_misses::cpu.data 9112677 # number of demand (read+write) MSHR misses
437 system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses
438 system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses
439 system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses
440 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128882841000 # number of ReadReq MSHR miss cycles
441 system.cpu.dcache.ReadReq_mshr_miss_latency::total 128882841000 # number of ReadReq MSHR miss cycles
442 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53602561000 # number of WriteReq MSHR miss cycles
443 system.cpu.dcache.WriteReq_mshr_miss_latency::total 53602561000 # number of WriteReq MSHR miss cycles
444 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182485402000 # number of demand (read+write) MSHR miss cycles
445 system.cpu.dcache.demand_mshr_miss_latency::total 182485402000 # number of demand (read+write) MSHR miss cycles
446 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182485402000 # number of overall MSHR miss cycles
447 system.cpu.dcache.overall_mshr_miss_latency::total 182485402000 # number of overall MSHR miss cycles
448 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses
449 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses
450 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses
451 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004309 # mshr miss rate for WriteReq accesses
452 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for demand accesses
453 system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses
454 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses
455 system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses
456 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17843.765411 # average ReadReq mshr miss latency
457 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17843.765411 # average ReadReq mshr miss latency
458 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28363.739644 # average WriteReq mshr miss latency
459 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28363.739644 # average WriteReq mshr miss latency
460 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency
461 system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency
462 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency
463 system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency
464 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
465 system.cpu.toL2Bus.trans_dist::ReadReq 7223525 # Transaction distribution
466 system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution
467 system.cpu.toL2Bus.trans_dist::Writeback 3697956 # Transaction distribution
468 system.cpu.toL2Bus.trans_dist::ReadExReq 1889827 # Transaction distribution
469 system.cpu.toL2Bus.trans_dist::ReadExResp 1889827 # Transaction distribution
470 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1350 # Packet count per connected master and slave (bytes)
471 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21923310 # Packet count per connected master and slave (bytes)
472 system.cpu.toL2Bus.pkt_count::total 21924660 # Packet count per connected master and slave (bytes)
473 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43200 # Cumulative packet size per connected master and slave (bytes)
474 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819880512 # Cumulative packet size per connected master and slave (bytes)
475 system.cpu.toL2Bus.pkt_size::total 819923712 # Cumulative packet size per connected master and slave (bytes)
476 system.cpu.toL2Bus.snoops 0 # Total snoops (count)
477 system.cpu.toL2Bus.snoop_fanout::samples 12811308 # Request fanout histogram
478 system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
479 system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
480 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
481 system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
482 system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
483 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
484 system.cpu.toL2Bus.snoop_fanout::3 12811308 100.00% 100.00% # Request fanout histogram
485 system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
486 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
487 system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
488 system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
489 system.cpu.toL2Bus.snoop_fanout::total 12811308 # Request fanout histogram
490 system.cpu.toL2Bus.reqLayer0.occupancy 10103610000 # Layer occupancy (ticks)
491 system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
492 system.cpu.toL2Bus.respLayer0.occupancy 1012500 # Layer occupancy (ticks)
493 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
494 system.cpu.toL2Bus.respLayer1.occupancy 13669015500 # Layer occupancy (ticks)
495 system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
497 ---------- End Simulation Statistics ----------
projects / gem5.git / blob