2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 5.891582 # Number of seconds simulated
4 sim_ticks 5891581948000 # Number of ticks simulated
5 final_tick 5891581948000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 701685 # Simulator instruction rate (inst/s)
8 host_op_rate 1093289 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 1374310212 # Simulator tick rate (ticks/s)
10 host_mem_usage 228764 # Number of bytes of host memory used
11 host_seconds 4286.94 # Real time elapsed on the host
12 sim_insts 3008081022 # Number of instructions simulated
13 sim_ops 4686862594 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 139043584 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 139086784 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory
19 system.physmem.bytes_written::writebacks 67393856 # Number of bytes written to this memory
20 system.physmem.bytes_written::total 67393856 # Number of bytes written to this memory
21 system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory
22 system.physmem.num_reads::cpu.data 2172556 # Number of read requests responded to by this memory
23 system.physmem.num_reads::total 2173231 # Number of read requests responded to by this memory
24 system.physmem.num_writes::writebacks 1053029 # Number of write requests responded to by this memory
25 system.physmem.num_writes::total 1053029 # Number of write requests responded to by this memory
26 system.physmem.bw_read::cpu.inst 7332 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_read::cpu.data 23600382 # Total read bandwidth from this memory (bytes/s)
28 system.physmem.bw_read::total 23607714 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_inst_read::cpu.inst 7332 # Instruction read bandwidth from this memory (bytes/s)
30 system.physmem.bw_inst_read::total 7332 # Instruction read bandwidth from this memory (bytes/s)
31 system.physmem.bw_write::writebacks 11439009 # Write bandwidth from this memory (bytes/s)
32 system.physmem.bw_write::total 11439009 # Write bandwidth from this memory (bytes/s)
33 system.physmem.bw_total::writebacks 11439009 # Total bandwidth to/from this memory (bytes/s)
34 system.physmem.bw_total::cpu.inst 7332 # Total bandwidth to/from this memory (bytes/s)
35 system.physmem.bw_total::cpu.data 23600382 # Total bandwidth to/from this memory (bytes/s)
36 system.physmem.bw_total::total 35046723 # Total bandwidth to/from this memory (bytes/s)
37 system.cpu.workload.num_syscalls 46 # Number of system calls
38 system.cpu.numCycles 11783163896 # number of cpu cycles simulated
39 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
40 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
41 system.cpu.committedInsts 3008081022 # Number of instructions committed
42 system.cpu.committedOps 4686862594 # Number of ops (including micro ops) committed
43 system.cpu.num_int_alu_accesses 4686862523 # Number of integer alu accesses
44 system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
45 system.cpu.num_func_calls 0 # number of times a function call or return occured
46 system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls
47 system.cpu.num_int_insts 4686862523 # number of integer instructions
48 system.cpu.num_fp_insts 0 # number of float instructions
49 system.cpu.num_int_register_reads 11915474418 # number of times the integer registers were read
50 system.cpu.num_int_register_writes 5355771935 # number of times the integer registers were written
51 system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
52 system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
53 system.cpu.num_mem_refs 1677713082 # number of memory refs
54 system.cpu.num_load_insts 1239184745 # Number of load instructions
55 system.cpu.num_store_insts 438528337 # Number of store instructions
56 system.cpu.num_idle_cycles 0 # Number of idle cycles
57 system.cpu.num_busy_cycles 11783163896 # Number of busy cycles
58 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
59 system.cpu.idle_fraction 0 # Percentage of idle cycles
60 system.cpu.icache.replacements 10 # number of replacements
61 system.cpu.icache.tagsinuse 555.725129 # Cycle average of tags in use
62 system.cpu.icache.total_refs 4013232208 # Total number of references to valid blocks.
63 system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks.
64 system.cpu.icache.avg_refs 5945529.197037 # Average number of references to valid blocks.
65 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
66 system.cpu.icache.occ_blocks::cpu.inst 555.725129 # Average occupied blocks per requestor
67 system.cpu.icache.occ_percent::cpu.inst 0.271350 # Average percentage of cache occupancy
68 system.cpu.icache.occ_percent::total 0.271350 # Average percentage of cache occupancy
69 system.cpu.icache.ReadReq_hits::cpu.inst 4013232208 # number of ReadReq hits
70 system.cpu.icache.ReadReq_hits::total 4013232208 # number of ReadReq hits
71 system.cpu.icache.demand_hits::cpu.inst 4013232208 # number of demand (read+write) hits
72 system.cpu.icache.demand_hits::total 4013232208 # number of demand (read+write) hits
73 system.cpu.icache.overall_hits::cpu.inst 4013232208 # number of overall hits
74 system.cpu.icache.overall_hits::total 4013232208 # number of overall hits
75 system.cpu.icache.ReadReq_misses::cpu.inst 675 # number of ReadReq misses
76 system.cpu.icache.ReadReq_misses::total 675 # number of ReadReq misses
77 system.cpu.icache.demand_misses::cpu.inst 675 # number of demand (read+write) misses
78 system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses
79 system.cpu.icache.overall_misses::cpu.inst 675 # number of overall misses
80 system.cpu.icache.overall_misses::total 675 # number of overall misses
81 system.cpu.icache.ReadReq_miss_latency::cpu.inst 37130000 # number of ReadReq miss cycles
82 system.cpu.icache.ReadReq_miss_latency::total 37130000 # number of ReadReq miss cycles
83 system.cpu.icache.demand_miss_latency::cpu.inst 37130000 # number of demand (read+write) miss cycles
84 system.cpu.icache.demand_miss_latency::total 37130000 # number of demand (read+write) miss cycles
85 system.cpu.icache.overall_miss_latency::cpu.inst 37130000 # number of overall miss cycles
86 system.cpu.icache.overall_miss_latency::total 37130000 # number of overall miss cycles
87 system.cpu.icache.ReadReq_accesses::cpu.inst 4013232883 # number of ReadReq accesses(hits+misses)
88 system.cpu.icache.ReadReq_accesses::total 4013232883 # number of ReadReq accesses(hits+misses)
89 system.cpu.icache.demand_accesses::cpu.inst 4013232883 # number of demand (read+write) accesses
90 system.cpu.icache.demand_accesses::total 4013232883 # number of demand (read+write) accesses
91 system.cpu.icache.overall_accesses::cpu.inst 4013232883 # number of overall (read+write) accesses
92 system.cpu.icache.overall_accesses::total 4013232883 # number of overall (read+write) accesses
93 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses
94 system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses
95 system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses
96 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
97 system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
98 system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses
99 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55007.407407 # average ReadReq miss latency
100 system.cpu.icache.ReadReq_avg_miss_latency::total 55007.407407 # average ReadReq miss latency
101 system.cpu.icache.demand_avg_miss_latency::cpu.inst 55007.407407 # average overall miss latency
102 system.cpu.icache.demand_avg_miss_latency::total 55007.407407 # average overall miss latency
103 system.cpu.icache.overall_avg_miss_latency::cpu.inst 55007.407407 # average overall miss latency
104 system.cpu.icache.overall_avg_miss_latency::total 55007.407407 # average overall miss latency
105 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
106 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
107 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
108 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
109 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
110 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
111 system.cpu.icache.fast_writes 0 # number of fast writes performed
112 system.cpu.icache.cache_copies 0 # number of cache copies performed
113 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses
114 system.cpu.icache.ReadReq_mshr_misses::total 675 # number of ReadReq MSHR misses
115 system.cpu.icache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses
116 system.cpu.icache.demand_mshr_misses::total 675 # number of demand (read+write) MSHR misses
117 system.cpu.icache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses
118 system.cpu.icache.overall_mshr_misses::total 675 # number of overall MSHR misses
119 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35780000 # number of ReadReq MSHR miss cycles
120 system.cpu.icache.ReadReq_mshr_miss_latency::total 35780000 # number of ReadReq MSHR miss cycles
121 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35780000 # number of demand (read+write) MSHR miss cycles
122 system.cpu.icache.demand_mshr_miss_latency::total 35780000 # number of demand (read+write) MSHR miss cycles
123 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35780000 # number of overall MSHR miss cycles
124 system.cpu.icache.overall_mshr_miss_latency::total 35780000 # number of overall MSHR miss cycles
125 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
126 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
127 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
128 system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
129 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
130 system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses
131 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53007.407407 # average ReadReq mshr miss latency
132 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53007.407407 # average ReadReq mshr miss latency
133 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53007.407407 # average overall mshr miss latency
134 system.cpu.icache.demand_avg_mshr_miss_latency::total 53007.407407 # average overall mshr miss latency
135 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53007.407407 # average overall mshr miss latency
136 system.cpu.icache.overall_avg_mshr_miss_latency::total 53007.407407 # average overall mshr miss latency
137 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
138 system.cpu.dcache.replacements 9108581 # number of replacements
139 system.cpu.dcache.tagsinuse 4084.604436 # Cycle average of tags in use
140 system.cpu.dcache.total_refs 1668600405 # Total number of references to valid blocks.
141 system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks.
142 system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks.
143 system.cpu.dcache.warmup_cycle 58853994000 # Cycle when the warmup percentage was hit.
144 system.cpu.dcache.occ_blocks::cpu.data 4084.604436 # Average occupied blocks per requestor
145 system.cpu.dcache.occ_percent::cpu.data 0.997218 # Average percentage of cache occupancy
146 system.cpu.dcache.occ_percent::total 0.997218 # Average percentage of cache occupancy
147 system.cpu.dcache.ReadReq_hits::cpu.data 1231961895 # number of ReadReq hits
148 system.cpu.dcache.ReadReq_hits::total 1231961895 # number of ReadReq hits
149 system.cpu.dcache.WriteReq_hits::cpu.data 436638510 # number of WriteReq hits
150 system.cpu.dcache.WriteReq_hits::total 436638510 # number of WriteReq hits
151 system.cpu.dcache.demand_hits::cpu.data 1668600405 # number of demand (read+write) hits
152 system.cpu.dcache.demand_hits::total 1668600405 # number of demand (read+write) hits
153 system.cpu.dcache.overall_hits::cpu.data 1668600405 # number of overall hits
154 system.cpu.dcache.overall_hits::total 1668600405 # number of overall hits
155 system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses
156 system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses
157 system.cpu.dcache.WriteReq_misses::cpu.data 1889827 # number of WriteReq misses
158 system.cpu.dcache.WriteReq_misses::total 1889827 # number of WriteReq misses
159 system.cpu.dcache.demand_misses::cpu.data 9112677 # number of demand (read+write) misses
160 system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses
161 system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses
162 system.cpu.dcache.overall_misses::total 9112677 # number of overall misses
163 system.cpu.dcache.ReadReq_miss_latency::cpu.data 151971083000 # number of ReadReq miss cycles
164 system.cpu.dcache.ReadReq_miss_latency::total 151971083000 # number of ReadReq miss cycles
165 system.cpu.dcache.WriteReq_miss_latency::cpu.data 57741123000 # number of WriteReq miss cycles
166 system.cpu.dcache.WriteReq_miss_latency::total 57741123000 # number of WriteReq miss cycles
167 system.cpu.dcache.demand_miss_latency::cpu.data 209712206000 # number of demand (read+write) miss cycles
168 system.cpu.dcache.demand_miss_latency::total 209712206000 # number of demand (read+write) miss cycles
169 system.cpu.dcache.overall_miss_latency::cpu.data 209712206000 # number of overall miss cycles
170 system.cpu.dcache.overall_miss_latency::total 209712206000 # number of overall miss cycles
171 system.cpu.dcache.ReadReq_accesses::cpu.data 1239184745 # number of ReadReq accesses(hits+misses)
172 system.cpu.dcache.ReadReq_accesses::total 1239184745 # number of ReadReq accesses(hits+misses)
173 system.cpu.dcache.WriteReq_accesses::cpu.data 438528337 # number of WriteReq accesses(hits+misses)
174 system.cpu.dcache.WriteReq_accesses::total 438528337 # number of WriteReq accesses(hits+misses)
175 system.cpu.dcache.demand_accesses::cpu.data 1677713082 # number of demand (read+write) accesses
176 system.cpu.dcache.demand_accesses::total 1677713082 # number of demand (read+write) accesses
177 system.cpu.dcache.overall_accesses::cpu.data 1677713082 # number of overall (read+write) accesses
178 system.cpu.dcache.overall_accesses::total 1677713082 # number of overall (read+write) accesses
179 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses
180 system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses
181 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses
182 system.cpu.dcache.WriteReq_miss_rate::total 0.004309 # miss rate for WriteReq accesses
183 system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 # miss rate for demand accesses
184 system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses
185 system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses
186 system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses
187 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21040.321064 # average ReadReq miss latency
188 system.cpu.dcache.ReadReq_avg_miss_latency::total 21040.321064 # average ReadReq miss latency
189 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30553.655440 # average WriteReq miss latency
190 system.cpu.dcache.WriteReq_avg_miss_latency::total 30553.655440 # average WriteReq miss latency
191 system.cpu.dcache.demand_avg_miss_latency::cpu.data 23013.238152 # average overall miss latency
192 system.cpu.dcache.demand_avg_miss_latency::total 23013.238152 # average overall miss latency
193 system.cpu.dcache.overall_avg_miss_latency::cpu.data 23013.238152 # average overall miss latency
194 system.cpu.dcache.overall_avg_miss_latency::total 23013.238152 # average overall miss latency
195 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
196 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
197 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
198 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
199 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
200 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
201 system.cpu.dcache.fast_writes 0 # number of fast writes performed
202 system.cpu.dcache.cache_copies 0 # number of cache copies performed
203 system.cpu.dcache.writebacks::writebacks 3375759 # number of writebacks
204 system.cpu.dcache.writebacks::total 3375759 # number of writebacks
205 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses
206 system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses
207 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses
208 system.cpu.dcache.WriteReq_mshr_misses::total 1889827 # number of WriteReq MSHR misses
209 system.cpu.dcache.demand_mshr_misses::cpu.data 9112677 # number of demand (read+write) MSHR misses
210 system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses
211 system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses
212 system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses
213 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137525383000 # number of ReadReq MSHR miss cycles
214 system.cpu.dcache.ReadReq_mshr_miss_latency::total 137525383000 # number of ReadReq MSHR miss cycles
215 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53961469000 # number of WriteReq MSHR miss cycles
216 system.cpu.dcache.WriteReq_mshr_miss_latency::total 53961469000 # number of WriteReq MSHR miss cycles
217 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191486852000 # number of demand (read+write) MSHR miss cycles
218 system.cpu.dcache.demand_mshr_miss_latency::total 191486852000 # number of demand (read+write) MSHR miss cycles
219 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191486852000 # number of overall MSHR miss cycles
220 system.cpu.dcache.overall_mshr_miss_latency::total 191486852000 # number of overall MSHR miss cycles
221 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses
222 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses
223 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses
224 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004309 # mshr miss rate for WriteReq accesses
225 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for demand accesses
226 system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses
227 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses
228 system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses
229 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19040.321064 # average ReadReq mshr miss latency
230 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19040.321064 # average ReadReq mshr miss latency
231 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28553.655440 # average WriteReq mshr miss latency
232 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28553.655440 # average WriteReq mshr miss latency
233 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21013.238152 # average overall mshr miss latency
234 system.cpu.dcache.demand_avg_mshr_miss_latency::total 21013.238152 # average overall mshr miss latency
235 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21013.238152 # average overall mshr miss latency
236 system.cpu.dcache.overall_avg_mshr_miss_latency::total 21013.238152 # average overall mshr miss latency
237 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
238 system.cpu.l2cache.replacements 2158210 # number of replacements
239 system.cpu.l2cache.tagsinuse 30849.854795 # Cycle average of tags in use
240 system.cpu.l2cache.total_refs 8410861 # Total number of references to valid blocks.
241 system.cpu.l2cache.sampled_refs 2187939 # Sample count of references to valid blocks.
242 system.cpu.l2cache.avg_refs 3.844194 # Average number of references to valid blocks.
243 system.cpu.l2cache.warmup_cycle 1315499445000 # Cycle when the warmup percentage was hit.
244 system.cpu.l2cache.occ_blocks::writebacks 14663.466685 # Average occupied blocks per requestor
245 system.cpu.l2cache.occ_blocks::cpu.inst 21.611649 # Average occupied blocks per requestor
246 system.cpu.l2cache.occ_blocks::cpu.data 16164.776461 # Average occupied blocks per requestor
247 system.cpu.l2cache.occ_percent::writebacks 0.447493 # Average percentage of cache occupancy
248 system.cpu.l2cache.occ_percent::cpu.inst 0.000660 # Average percentage of cache occupancy
249 system.cpu.l2cache.occ_percent::cpu.data 0.493310 # Average percentage of cache occupancy
250 system.cpu.l2cache.occ_percent::total 0.941463 # Average percentage of cache occupancy
251 system.cpu.l2cache.ReadReq_hits::cpu.data 5840135 # number of ReadReq hits
252 system.cpu.l2cache.ReadReq_hits::total 5840135 # number of ReadReq hits
253 system.cpu.l2cache.Writeback_hits::writebacks 3375759 # number of Writeback hits
254 system.cpu.l2cache.Writeback_hits::total 3375759 # number of Writeback hits
255 system.cpu.l2cache.ReadExReq_hits::cpu.data 1099986 # number of ReadExReq hits
256 system.cpu.l2cache.ReadExReq_hits::total 1099986 # number of ReadExReq hits
257 system.cpu.l2cache.demand_hits::cpu.data 6940121 # number of demand (read+write) hits
258 system.cpu.l2cache.demand_hits::total 6940121 # number of demand (read+write) hits
259 system.cpu.l2cache.overall_hits::cpu.data 6940121 # number of overall hits
260 system.cpu.l2cache.overall_hits::total 6940121 # number of overall hits
261 system.cpu.l2cache.ReadReq_misses::cpu.inst 675 # number of ReadReq misses
262 system.cpu.l2cache.ReadReq_misses::cpu.data 1382715 # number of ReadReq misses
263 system.cpu.l2cache.ReadReq_misses::total 1383390 # number of ReadReq misses
264 system.cpu.l2cache.ReadExReq_misses::cpu.data 789841 # number of ReadExReq misses
265 system.cpu.l2cache.ReadExReq_misses::total 789841 # number of ReadExReq misses
266 system.cpu.l2cache.demand_misses::cpu.inst 675 # number of demand (read+write) misses
267 system.cpu.l2cache.demand_misses::cpu.data 2172556 # number of demand (read+write) misses
268 system.cpu.l2cache.demand_misses::total 2173231 # number of demand (read+write) misses
269 system.cpu.l2cache.overall_misses::cpu.inst 675 # number of overall misses
270 system.cpu.l2cache.overall_misses::cpu.data 2172556 # number of overall misses
271 system.cpu.l2cache.overall_misses::total 2173231 # number of overall misses
272 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35105000 # number of ReadReq miss cycles
273 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71901183000 # number of ReadReq miss cycles
274 system.cpu.l2cache.ReadReq_miss_latency::total 71936288000 # number of ReadReq miss cycles
275 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41071782000 # number of ReadExReq miss cycles
276 system.cpu.l2cache.ReadExReq_miss_latency::total 41071782000 # number of ReadExReq miss cycles
277 system.cpu.l2cache.demand_miss_latency::cpu.inst 35105000 # number of demand (read+write) miss cycles
278 system.cpu.l2cache.demand_miss_latency::cpu.data 112972965000 # number of demand (read+write) miss cycles
279 system.cpu.l2cache.demand_miss_latency::total 113008070000 # number of demand (read+write) miss cycles
280 system.cpu.l2cache.overall_miss_latency::cpu.inst 35105000 # number of overall miss cycles
281 system.cpu.l2cache.overall_miss_latency::cpu.data 112972965000 # number of overall miss cycles
282 system.cpu.l2cache.overall_miss_latency::total 113008070000 # number of overall miss cycles
283 system.cpu.l2cache.ReadReq_accesses::cpu.inst 675 # number of ReadReq accesses(hits+misses)
284 system.cpu.l2cache.ReadReq_accesses::cpu.data 7222850 # number of ReadReq accesses(hits+misses)
285 system.cpu.l2cache.ReadReq_accesses::total 7223525 # number of ReadReq accesses(hits+misses)
286 system.cpu.l2cache.Writeback_accesses::writebacks 3375759 # number of Writeback accesses(hits+misses)
287 system.cpu.l2cache.Writeback_accesses::total 3375759 # number of Writeback accesses(hits+misses)
288 system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889827 # number of ReadExReq accesses(hits+misses)
289 system.cpu.l2cache.ReadExReq_accesses::total 1889827 # number of ReadExReq accesses(hits+misses)
290 system.cpu.l2cache.demand_accesses::cpu.inst 675 # number of demand (read+write) accesses
291 system.cpu.l2cache.demand_accesses::cpu.data 9112677 # number of demand (read+write) accesses
292 system.cpu.l2cache.demand_accesses::total 9113352 # number of demand (read+write) accesses
293 system.cpu.l2cache.overall_accesses::cpu.inst 675 # number of overall (read+write) accesses
294 system.cpu.l2cache.overall_accesses::cpu.data 9112677 # number of overall (read+write) accesses
295 system.cpu.l2cache.overall_accesses::total 9113352 # number of overall (read+write) accesses
296 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
297 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.191436 # miss rate for ReadReq accesses
298 system.cpu.l2cache.ReadReq_miss_rate::total 0.191512 # miss rate for ReadReq accesses
299 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.417944 # miss rate for ReadExReq accesses
300 system.cpu.l2cache.ReadExReq_miss_rate::total 0.417944 # miss rate for ReadExReq accesses
301 system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
302 system.cpu.l2cache.demand_miss_rate::cpu.data 0.238410 # miss rate for demand accesses
303 system.cpu.l2cache.demand_miss_rate::total 0.238467 # miss rate for demand accesses
304 system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
305 system.cpu.l2cache.overall_miss_rate::cpu.data 0.238410 # miss rate for overall accesses
306 system.cpu.l2cache.overall_miss_rate::total 0.238467 # miss rate for overall accesses
307 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52007.407407 # average ReadReq miss latency
308 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.002170 # average ReadReq miss latency
309 system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.005783 # average ReadReq miss latency
310 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.063304 # average ReadExReq miss latency
311 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.063304 # average ReadExReq miss latency
312 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52007.407407 # average overall miss latency
313 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.024395 # average overall miss latency
314 system.cpu.l2cache.demand_avg_miss_latency::total 52000.026688 # average overall miss latency
315 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52007.407407 # average overall miss latency
316 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.024395 # average overall miss latency
317 system.cpu.l2cache.overall_avg_miss_latency::total 52000.026688 # average overall miss latency
318 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
319 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
320 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
321 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
322 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
323 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
324 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
325 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
326 system.cpu.l2cache.writebacks::writebacks 1053029 # number of writebacks
327 system.cpu.l2cache.writebacks::total 1053029 # number of writebacks
328 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses
329 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1382715 # number of ReadReq MSHR misses
330 system.cpu.l2cache.ReadReq_mshr_misses::total 1383390 # number of ReadReq MSHR misses
331 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 789841 # number of ReadExReq MSHR misses
332 system.cpu.l2cache.ReadExReq_mshr_misses::total 789841 # number of ReadExReq MSHR misses
333 system.cpu.l2cache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses
334 system.cpu.l2cache.demand_mshr_misses::cpu.data 2172556 # number of demand (read+write) MSHR misses
335 system.cpu.l2cache.demand_mshr_misses::total 2173231 # number of demand (read+write) MSHR misses
336 system.cpu.l2cache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses
337 system.cpu.l2cache.overall_mshr_misses::cpu.data 2172556 # number of overall MSHR misses
338 system.cpu.l2cache.overall_mshr_misses::total 2173231 # number of overall MSHR misses
339 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27005000 # number of ReadReq MSHR miss cycles
340 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 55308603000 # number of ReadReq MSHR miss cycles
341 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 55335608000 # number of ReadReq MSHR miss cycles
342 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31593690000 # number of ReadExReq MSHR miss cycles
343 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31593690000 # number of ReadExReq MSHR miss cycles
344 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27005000 # number of demand (read+write) MSHR miss cycles
345 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86902293000 # number of demand (read+write) MSHR miss cycles
346 system.cpu.l2cache.demand_mshr_miss_latency::total 86929298000 # number of demand (read+write) MSHR miss cycles
347 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27005000 # number of overall MSHR miss cycles
348 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86902293000 # number of overall MSHR miss cycles
349 system.cpu.l2cache.overall_mshr_miss_latency::total 86929298000 # number of overall MSHR miss cycles
350 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
351 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.191436 # mshr miss rate for ReadReq accesses
352 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.191512 # mshr miss rate for ReadReq accesses
353 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.417944 # mshr miss rate for ReadExReq accesses
354 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.417944 # mshr miss rate for ReadExReq accesses
355 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
356 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.238410 # mshr miss rate for demand accesses
357 system.cpu.l2cache.demand_mshr_miss_rate::total 0.238467 # mshr miss rate for demand accesses
358 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
359 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.238410 # mshr miss rate for overall accesses
360 system.cpu.l2cache.overall_mshr_miss_rate::total 0.238467 # mshr miss rate for overall accesses
361 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40007.407407 # average ReadReq mshr miss latency
362 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.002170 # average ReadReq mshr miss latency
363 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.005783 # average ReadReq mshr miss latency
364 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.063304 # average ReadExReq mshr miss latency
365 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.063304 # average ReadExReq mshr miss latency
366 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40007.407407 # average overall mshr miss latency
367 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.024395 # average overall mshr miss latency
368 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.026688 # average overall mshr miss latency
369 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40007.407407 # average overall mshr miss latency
370 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.024395 # average overall mshr miss latency
371 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.026688 # average overall mshr miss latency
372 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
374 ---------- End Simulation Statistics ----------
projects / gem5.git / blob