2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.041680 # Number of seconds simulated
4 sim_ticks 41680207000 # Number of ticks simulated
5 final_tick 41680207000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 93645 # Simulator instruction rate (inst/s)
8 host_op_rate 93645 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 42470141 # Simulator tick rate (ticks/s)
10 host_mem_usage 279708 # Number of bytes of host memory used
11 host_seconds 981.40 # Real time elapsed on the host
12 sim_insts 91903056 # Number of instructions simulated
13 sim_ops 91903056 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 137216 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 316032 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 178816 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 178816 # Number of instructions bytes read from this memory
19 system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory
20 system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory
21 system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory
22 system.physmem.bw_read::cpu.inst 4290190 # Total read bandwidth from this memory (bytes/s)
23 system.physmem.bw_read::cpu.data 3292114 # Total read bandwidth from this memory (bytes/s)
24 system.physmem.bw_read::total 7582304 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_inst_read::cpu.inst 4290190 # Instruction read bandwidth from this memory (bytes/s)
26 system.physmem.bw_inst_read::total 4290190 # Instruction read bandwidth from this memory (bytes/s)
27 system.physmem.bw_total::cpu.inst 4290190 # Total bandwidth to/from this memory (bytes/s)
28 system.physmem.bw_total::cpu.data 3292114 # Total bandwidth to/from this memory (bytes/s)
29 system.physmem.bw_total::total 7582304 # Total bandwidth to/from this memory (bytes/s)
30 system.physmem.readReqs 4938 # Number of read requests accepted
31 system.physmem.writeReqs 0 # Number of write requests accepted
32 system.physmem.readBursts 4938 # Number of DRAM read bursts, including those serviced by the write queue
33 system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
34 system.physmem.bytesReadDRAM 316032 # Total number of bytes read from DRAM
35 system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
36 system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
37 system.physmem.bytesReadSys 316032 # Total read bytes from the system interface side
38 system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
39 system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
40 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
41 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
42 system.physmem.perBankRdBursts::0 443 # Per bank write bursts
43 system.physmem.perBankRdBursts::1 270 # Per bank write bursts
44 system.physmem.perBankRdBursts::2 295 # Per bank write bursts
45 system.physmem.perBankRdBursts::3 499 # Per bank write bursts
46 system.physmem.perBankRdBursts::4 209 # Per bank write bursts
47 system.physmem.perBankRdBursts::5 212 # Per bank write bursts
48 system.physmem.perBankRdBursts::6 207 # Per bank write bursts
49 system.physmem.perBankRdBursts::7 265 # Per bank write bursts
50 system.physmem.perBankRdBursts::8 219 # Per bank write bursts
51 system.physmem.perBankRdBursts::9 249 # Per bank write bursts
52 system.physmem.perBankRdBursts::10 238 # Per bank write bursts
53 system.physmem.perBankRdBursts::11 236 # Per bank write bursts
54 system.physmem.perBankRdBursts::12 379 # Per bank write bursts
55 system.physmem.perBankRdBursts::13 325 # Per bank write bursts
56 system.physmem.perBankRdBursts::14 469 # Per bank write bursts
57 system.physmem.perBankRdBursts::15 423 # Per bank write bursts
58 system.physmem.perBankWrBursts::0 0 # Per bank write bursts
59 system.physmem.perBankWrBursts::1 0 # Per bank write bursts
60 system.physmem.perBankWrBursts::2 0 # Per bank write bursts
61 system.physmem.perBankWrBursts::3 0 # Per bank write bursts
62 system.physmem.perBankWrBursts::4 0 # Per bank write bursts
63 system.physmem.perBankWrBursts::5 0 # Per bank write bursts
64 system.physmem.perBankWrBursts::6 0 # Per bank write bursts
65 system.physmem.perBankWrBursts::7 0 # Per bank write bursts
66 system.physmem.perBankWrBursts::8 0 # Per bank write bursts
67 system.physmem.perBankWrBursts::9 0 # Per bank write bursts
68 system.physmem.perBankWrBursts::10 0 # Per bank write bursts
69 system.physmem.perBankWrBursts::11 0 # Per bank write bursts
70 system.physmem.perBankWrBursts::12 0 # Per bank write bursts
71 system.physmem.perBankWrBursts::13 0 # Per bank write bursts
72 system.physmem.perBankWrBursts::14 0 # Per bank write bursts
73 system.physmem.perBankWrBursts::15 0 # Per bank write bursts
74 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
75 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
76 system.physmem.totGap 41680133000 # Total gap between requests
77 system.physmem.readPktSize::0 0 # Read request sizes (log2)
78 system.physmem.readPktSize::1 0 # Read request sizes (log2)
79 system.physmem.readPktSize::2 0 # Read request sizes (log2)
80 system.physmem.readPktSize::3 0 # Read request sizes (log2)
81 system.physmem.readPktSize::4 0 # Read request sizes (log2)
82 system.physmem.readPktSize::5 0 # Read request sizes (log2)
83 system.physmem.readPktSize::6 4938 # Read request sizes (log2)
84 system.physmem.writePktSize::0 0 # Write request sizes (log2)
85 system.physmem.writePktSize::1 0 # Write request sizes (log2)
86 system.physmem.writePktSize::2 0 # Write request sizes (log2)
87 system.physmem.writePktSize::3 0 # Write request sizes (log2)
88 system.physmem.writePktSize::4 0 # Write request sizes (log2)
89 system.physmem.writePktSize::5 0 # Write request sizes (log2)
90 system.physmem.writePktSize::6 0 # Write request sizes (log2)
91 system.physmem.rdQLenPdf::0 3403 # What read queue length does an incoming req see
92 system.physmem.rdQLenPdf::1 1090 # What read queue length does an incoming req see
93 system.physmem.rdQLenPdf::2 402 # What read queue length does an incoming req see
94 system.physmem.rdQLenPdf::3 39 # What read queue length does an incoming req see
95 system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
96 system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
97 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
98 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
99 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
100 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
123 system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
124 system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
125 system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
126 system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
127 system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
128 system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
129 system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
130 system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
131 system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
132 system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
155 system.physmem.bytesPerActivate::samples 743 # Bytes accessed per row activation
156 system.physmem.bytesPerActivate::mean 421.641992 # Bytes accessed per row activation
157 system.physmem.bytesPerActivate::gmean 209.527903 # Bytes accessed per row activation
158 system.physmem.bytesPerActivate::stdev 761.351186 # Bytes accessed per row activation
159 system.physmem.bytesPerActivate::64-65 254 34.19% 34.19% # Bytes accessed per row activation
160 system.physmem.bytesPerActivate::128-129 96 12.92% 47.11% # Bytes accessed per row activation
161 system.physmem.bytesPerActivate::192-193 62 8.34% 55.45% # Bytes accessed per row activation
162 system.physmem.bytesPerActivate::256-257 50 6.73% 62.18% # Bytes accessed per row activation
163 system.physmem.bytesPerActivate::320-321 29 3.90% 66.08% # Bytes accessed per row activation
164 system.physmem.bytesPerActivate::384-385 32 4.31% 70.39% # Bytes accessed per row activation
165 system.physmem.bytesPerActivate::448-449 22 2.96% 73.35% # Bytes accessed per row activation
166 system.physmem.bytesPerActivate::512-513 25 3.36% 76.72% # Bytes accessed per row activation
167 system.physmem.bytesPerActivate::576-577 15 2.02% 78.73% # Bytes accessed per row activation
168 system.physmem.bytesPerActivate::640-641 12 1.62% 80.35% # Bytes accessed per row activation
169 system.physmem.bytesPerActivate::704-705 14 1.88% 82.23% # Bytes accessed per row activation
170 system.physmem.bytesPerActivate::768-769 16 2.15% 84.39% # Bytes accessed per row activation
171 system.physmem.bytesPerActivate::832-833 32 4.31% 88.69% # Bytes accessed per row activation
172 system.physmem.bytesPerActivate::896-897 17 2.29% 90.98% # Bytes accessed per row activation
173 system.physmem.bytesPerActivate::960-961 5 0.67% 91.66% # Bytes accessed per row activation
174 system.physmem.bytesPerActivate::1024-1025 5 0.67% 92.33% # Bytes accessed per row activation
175 system.physmem.bytesPerActivate::1088-1089 8 1.08% 93.41% # Bytes accessed per row activation
176 system.physmem.bytesPerActivate::1152-1153 5 0.67% 94.08% # Bytes accessed per row activation
177 system.physmem.bytesPerActivate::1216-1217 6 0.81% 94.89% # Bytes accessed per row activation
178 system.physmem.bytesPerActivate::1280-1281 6 0.81% 95.69% # Bytes accessed per row activation
179 system.physmem.bytesPerActivate::1344-1345 2 0.27% 95.96% # Bytes accessed per row activation
180 system.physmem.bytesPerActivate::1408-1409 1 0.13% 96.10% # Bytes accessed per row activation
181 system.physmem.bytesPerActivate::1472-1473 1 0.13% 96.23% # Bytes accessed per row activation
182 system.physmem.bytesPerActivate::1536-1537 3 0.40% 96.64% # Bytes accessed per row activation
183 system.physmem.bytesPerActivate::1600-1601 2 0.27% 96.90% # Bytes accessed per row activation
184 system.physmem.bytesPerActivate::1664-1665 1 0.13% 97.04% # Bytes accessed per row activation
185 system.physmem.bytesPerActivate::1792-1793 2 0.27% 97.31% # Bytes accessed per row activation
186 system.physmem.bytesPerActivate::1856-1857 2 0.27% 97.58% # Bytes accessed per row activation
187 system.physmem.bytesPerActivate::1920-1921 1 0.13% 97.71% # Bytes accessed per row activation
188 system.physmem.bytesPerActivate::1984-1985 1 0.13% 97.85% # Bytes accessed per row activation
189 system.physmem.bytesPerActivate::2048-2049 1 0.13% 97.98% # Bytes accessed per row activation
190 system.physmem.bytesPerActivate::2112-2113 1 0.13% 98.12% # Bytes accessed per row activation
191 system.physmem.bytesPerActivate::2240-2241 1 0.13% 98.25% # Bytes accessed per row activation
192 system.physmem.bytesPerActivate::2432-2433 1 0.13% 98.38% # Bytes accessed per row activation
193 system.physmem.bytesPerActivate::2624-2625 1 0.13% 98.52% # Bytes accessed per row activation
194 system.physmem.bytesPerActivate::2880-2881 1 0.13% 98.65% # Bytes accessed per row activation
195 system.physmem.bytesPerActivate::2944-2945 1 0.13% 98.79% # Bytes accessed per row activation
196 system.physmem.bytesPerActivate::3328-3329 1 0.13% 98.92% # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::3520-3521 1 0.13% 99.06% # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::4032-4033 1 0.13% 99.19% # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::4608-4609 1 0.13% 99.33% # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::5568-5569 1 0.13% 99.46% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::7168-7169 1 0.13% 99.60% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::8064-8065 1 0.13% 99.73% # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::8128-8129 1 0.13% 99.87% # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::8192-8193 1 0.13% 100.00% # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::total 743 # Bytes accessed per row activation
206 system.physmem.totQLat 34070750 # Total ticks spent queuing
207 system.physmem.totMemAccLat 126424500 # Total ticks spent from burst creation until serviced by the DRAM
208 system.physmem.totBusLat 24690000 # Total ticks spent in databus transfers
209 system.physmem.totBankLat 67663750 # Total ticks spent accessing banks
210 system.physmem.avgQLat 6899.71 # Average queueing delay per DRAM burst
211 system.physmem.avgBankLat 13702.66 # Average bank access latency per DRAM burst
212 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
213 system.physmem.avgMemAccLat 25602.37 # Average memory access latency per DRAM burst
214 system.physmem.avgRdBW 7.58 # Average DRAM read bandwidth in MiByte/s
215 system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
216 system.physmem.avgRdBWSys 7.58 # Average system read bandwidth in MiByte/s
217 system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
218 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
219 system.physmem.busUtil 0.06 # Data bus utilization in percentage
220 system.physmem.busUtilRead 0.06 # Data bus utilization in percentage for reads
221 system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
222 system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing
223 system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
224 system.physmem.readRowHits 4195 # Number of row buffer hits during reads
225 system.physmem.writeRowHits 0 # Number of row buffer hits during writes
226 system.physmem.readRowHitRate 84.95 # Row buffer hit rate for reads
227 system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
228 system.physmem.avgGap 8440691.17 # Average gap between requests
229 system.physmem.pageHitRate 84.95 # Row buffer hit rate, read and write combined
230 system.physmem.prechargeAllPercent 0.90 # Percentage of time for which DRAM has all the banks in precharge state
231 system.membus.throughput 7582304 # Throughput (bytes/s)
232 system.membus.trans_dist::ReadReq 3216 # Transaction distribution
233 system.membus.trans_dist::ReadResp 3216 # Transaction distribution
234 system.membus.trans_dist::ReadExReq 1722 # Transaction distribution
235 system.membus.trans_dist::ReadExResp 1722 # Transaction distribution
236 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9876 # Packet count per connected master and slave (bytes)
237 system.membus.pkt_count::total 9876 # Packet count per connected master and slave (bytes)
238 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 316032 # Cumulative packet size per connected master and slave (bytes)
239 system.membus.tot_pkt_size::total 316032 # Cumulative packet size per connected master and slave (bytes)
240 system.membus.data_through_bus 316032 # Total data (bytes)
241 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
242 system.membus.reqLayer0.occupancy 5775000 # Layer occupancy (ticks)
243 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
244 system.membus.respLayer1.occupancy 45973500 # Layer occupancy (ticks)
245 system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
246 system.cpu.branchPred.lookups 13412627 # Number of BP lookups
247 system.cpu.branchPred.condPredicted 9650146 # Number of conditional branches predicted
248 system.cpu.branchPred.condIncorrect 4269214 # Number of conditional branches incorrect
249 system.cpu.branchPred.BTBLookups 7424479 # Number of BTB lookups
250 system.cpu.branchPred.BTBHits 3768497 # Number of BTB hits
251 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
252 system.cpu.branchPred.BTBHitPct 50.757730 # BTB Hit Percentage
253 system.cpu.branchPred.usedRAS 1029619 # Number of times the RAS was used to get a target.
254 system.cpu.branchPred.RASInCorrect 126 # Number of incorrect RAS predictions.
255 system.cpu.dtb.fetch_hits 0 # ITB hits
256 system.cpu.dtb.fetch_misses 0 # ITB misses
257 system.cpu.dtb.fetch_acv 0 # ITB acv
258 system.cpu.dtb.fetch_accesses 0 # ITB accesses
259 system.cpu.dtb.read_hits 19996265 # DTB read hits
260 system.cpu.dtb.read_misses 10 # DTB read misses
261 system.cpu.dtb.read_acv 0 # DTB read access violations
262 system.cpu.dtb.read_accesses 19996275 # DTB read accesses
263 system.cpu.dtb.write_hits 6501862 # DTB write hits
264 system.cpu.dtb.write_misses 23 # DTB write misses
265 system.cpu.dtb.write_acv 0 # DTB write access violations
266 system.cpu.dtb.write_accesses 6501885 # DTB write accesses
267 system.cpu.dtb.data_hits 26498127 # DTB hits
268 system.cpu.dtb.data_misses 33 # DTB misses
269 system.cpu.dtb.data_acv 0 # DTB access violations
270 system.cpu.dtb.data_accesses 26498160 # DTB accesses
271 system.cpu.itb.fetch_hits 9956950 # ITB hits
272 system.cpu.itb.fetch_misses 49 # ITB misses
273 system.cpu.itb.fetch_acv 0 # ITB acv
274 system.cpu.itb.fetch_accesses 9956999 # ITB accesses
275 system.cpu.itb.read_hits 0 # DTB read hits
276 system.cpu.itb.read_misses 0 # DTB read misses
277 system.cpu.itb.read_acv 0 # DTB read access violations
278 system.cpu.itb.read_accesses 0 # DTB read accesses
279 system.cpu.itb.write_hits 0 # DTB write hits
280 system.cpu.itb.write_misses 0 # DTB write misses
281 system.cpu.itb.write_acv 0 # DTB write access violations
282 system.cpu.itb.write_accesses 0 # DTB write accesses
283 system.cpu.itb.data_hits 0 # DTB hits
284 system.cpu.itb.data_misses 0 # DTB misses
285 system.cpu.itb.data_acv 0 # DTB access violations
286 system.cpu.itb.data_accesses 0 # DTB accesses
287 system.cpu.workload.num_syscalls 389 # Number of system calls
288 system.cpu.numCycles 83360415 # number of cpu cycles simulated
289 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
290 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
291 system.cpu.branch_predictor.predictedTaken 5905662 # Number of Branches Predicted As Taken (True).
292 system.cpu.branch_predictor.predictedNotTaken 7506965 # Number of Branches Predicted As Not Taken (False).
293 system.cpu.regfile_manager.intRegFileReads 73570552 # Number of Reads from Int. Register File
294 system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File
295 system.cpu.regfile_manager.intRegFileAccesses 136146024 # Total Accesses (Read+Write) to the Int. Register File
296 system.cpu.regfile_manager.floatRegFileReads 2206128 # Number of Reads from FP Register File
297 system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File
298 system.cpu.regfile_manager.floatRegFileAccesses 8058016 # Total Accesses (Read+Write) to the FP Register File
299 system.cpu.regfile_manager.regForwards 38521866 # Number of Registers Read Through Forwarding Logic
300 system.cpu.agen_unit.agens 26722393 # Number of Address Generations
301 system.cpu.execution_unit.predictedTakenIncorrect 3469296 # Number of Branches Incorrectly Predicted As Taken.
302 system.cpu.execution_unit.predictedNotTakenIncorrect 799060 # Number of Branches Incorrectly Predicted As Not Taken).
303 system.cpu.execution_unit.mispredicted 4268356 # Number of Branches Incorrectly Predicted
304 system.cpu.execution_unit.predicted 5972346 # Number of Branches Incorrectly Predicted
305 system.cpu.execution_unit.mispredictPct 41.680307 # Percentage of Incorrect Branches Predicts
306 system.cpu.execution_unit.executions 57404027 # Number of Instructions Executed.
307 system.cpu.mult_div_unit.multiplies 458253 # Number of Multipy Operations Executed
308 system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
309 system.cpu.contextSwitches 1 # Number of context switches
310 system.cpu.threadCycles 82971123 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
311 system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
312 system.cpu.timesIdled 10519 # Number of times that the entire CPU went into an idle state and unscheduled itself
313 system.cpu.idleCycles 7752655 # Number of cycles cpu's stages were not processed
314 system.cpu.runCycles 75607760 # Number of cycles cpu stages are processed.
315 system.cpu.activity 90.699836 # Percentage of cycles cpu is active
316 system.cpu.comLoads 19996198 # Number of Load instructions committed
317 system.cpu.comStores 6501103 # Number of Store instructions committed
318 system.cpu.comBranches 10240685 # Number of Branches instructions committed
319 system.cpu.comNops 7723346 # Number of Nop instructions committed
320 system.cpu.comNonSpec 389 # Number of Non-Speculative instructions committed
321 system.cpu.comInts 43665352 # Number of Integer instructions committed
322 system.cpu.comFloats 3775974 # Number of Floating Point instructions committed
323 system.cpu.committedInsts 91903056 # Number of Instructions committed (Per-Thread)
324 system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread)
325 system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
326 system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total)
327 system.cpu.cpi 0.907047 # CPI: Cycles Per Instruction (Per-Thread)
328 system.cpu.smt_cpi nan # CPI: Total SMT-CPI
329 system.cpu.cpi_total 0.907047 # CPI: Total CPI of All Threads
330 system.cpu.ipc 1.102478 # IPC: Instructions Per Cycle (Per-Thread)
331 system.cpu.smt_ipc nan # IPC: Total SMT-IPC
332 system.cpu.ipc_total 1.102478 # IPC: Total IPC of All Threads
333 system.cpu.stage0.idleCycles 27680069 # Number of cycles 0 instructions are processed.
334 system.cpu.stage0.runCycles 55680346 # Number of cycles 1+ instructions are processed.
335 system.cpu.stage0.utilization 66.794708 # Percentage of cycles stage was utilized (processing insts).
336 system.cpu.stage1.idleCycles 34108732 # Number of cycles 0 instructions are processed.
337 system.cpu.stage1.runCycles 49251683 # Number of cycles 1+ instructions are processed.
338 system.cpu.stage1.utilization 59.082819 # Percentage of cycles stage was utilized (processing insts).
339 system.cpu.stage2.idleCycles 33509067 # Number of cycles 0 instructions are processed.
340 system.cpu.stage2.runCycles 49851348 # Number of cycles 1+ instructions are processed.
341 system.cpu.stage2.utilization 59.802183 # Percentage of cycles stage was utilized (processing insts).
342 system.cpu.stage3.idleCycles 65333914 # Number of cycles 0 instructions are processed.
343 system.cpu.stage3.runCycles 18026501 # Number of cycles 1+ instructions are processed.
344 system.cpu.stage3.utilization 21.624774 # Percentage of cycles stage was utilized (processing insts).
345 system.cpu.stage4.idleCycles 29500658 # Number of cycles 0 instructions are processed.
346 system.cpu.stage4.runCycles 53859757 # Number of cycles 1+ instructions are processed.
347 system.cpu.stage4.utilization 64.610711 # Percentage of cycles stage was utilized (processing insts).
348 system.cpu.icache.tags.replacements 7635 # number of replacements
349 system.cpu.icache.tags.tagsinuse 1492.182806 # Cycle average of tags in use
350 system.cpu.icache.tags.total_refs 9945551 # Total number of references to valid blocks.
351 system.cpu.icache.tags.sampled_refs 9520 # Sample count of references to valid blocks.
352 system.cpu.icache.tags.avg_refs 1044.700735 # Average number of references to valid blocks.
353 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
354 system.cpu.icache.tags.occ_blocks::cpu.inst 1492.182806 # Average occupied blocks per requestor
355 system.cpu.icache.tags.occ_percent::cpu.inst 0.728605 # Average percentage of cache occupancy
356 system.cpu.icache.tags.occ_percent::total 0.728605 # Average percentage of cache occupancy
357 system.cpu.icache.ReadReq_hits::cpu.inst 9945551 # number of ReadReq hits
358 system.cpu.icache.ReadReq_hits::total 9945551 # number of ReadReq hits
359 system.cpu.icache.demand_hits::cpu.inst 9945551 # number of demand (read+write) hits
360 system.cpu.icache.demand_hits::total 9945551 # number of demand (read+write) hits
361 system.cpu.icache.overall_hits::cpu.inst 9945551 # number of overall hits
362 system.cpu.icache.overall_hits::total 9945551 # number of overall hits
363 system.cpu.icache.ReadReq_misses::cpu.inst 11399 # number of ReadReq misses
364 system.cpu.icache.ReadReq_misses::total 11399 # number of ReadReq misses
365 system.cpu.icache.demand_misses::cpu.inst 11399 # number of demand (read+write) misses
366 system.cpu.icache.demand_misses::total 11399 # number of demand (read+write) misses
367 system.cpu.icache.overall_misses::cpu.inst 11399 # number of overall misses
368 system.cpu.icache.overall_misses::total 11399 # number of overall misses
369 system.cpu.icache.ReadReq_miss_latency::cpu.inst 325866750 # number of ReadReq miss cycles
370 system.cpu.icache.ReadReq_miss_latency::total 325866750 # number of ReadReq miss cycles
371 system.cpu.icache.demand_miss_latency::cpu.inst 325866750 # number of demand (read+write) miss cycles
372 system.cpu.icache.demand_miss_latency::total 325866750 # number of demand (read+write) miss cycles
373 system.cpu.icache.overall_miss_latency::cpu.inst 325866750 # number of overall miss cycles
374 system.cpu.icache.overall_miss_latency::total 325866750 # number of overall miss cycles
375 system.cpu.icache.ReadReq_accesses::cpu.inst 9956950 # number of ReadReq accesses(hits+misses)
376 system.cpu.icache.ReadReq_accesses::total 9956950 # number of ReadReq accesses(hits+misses)
377 system.cpu.icache.demand_accesses::cpu.inst 9956950 # number of demand (read+write) accesses
378 system.cpu.icache.demand_accesses::total 9956950 # number of demand (read+write) accesses
379 system.cpu.icache.overall_accesses::cpu.inst 9956950 # number of overall (read+write) accesses
380 system.cpu.icache.overall_accesses::total 9956950 # number of overall (read+write) accesses
381 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001145 # miss rate for ReadReq accesses
382 system.cpu.icache.ReadReq_miss_rate::total 0.001145 # miss rate for ReadReq accesses
383 system.cpu.icache.demand_miss_rate::cpu.inst 0.001145 # miss rate for demand accesses
384 system.cpu.icache.demand_miss_rate::total 0.001145 # miss rate for demand accesses
385 system.cpu.icache.overall_miss_rate::cpu.inst 0.001145 # miss rate for overall accesses
386 system.cpu.icache.overall_miss_rate::total 0.001145 # miss rate for overall accesses
387 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28587.310290 # average ReadReq miss latency
388 system.cpu.icache.ReadReq_avg_miss_latency::total 28587.310290 # average ReadReq miss latency
389 system.cpu.icache.demand_avg_miss_latency::cpu.inst 28587.310290 # average overall miss latency
390 system.cpu.icache.demand_avg_miss_latency::total 28587.310290 # average overall miss latency
391 system.cpu.icache.overall_avg_miss_latency::cpu.inst 28587.310290 # average overall miss latency
392 system.cpu.icache.overall_avg_miss_latency::total 28587.310290 # average overall miss latency
393 system.cpu.icache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked
394 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
395 system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
396 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
397 system.cpu.icache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked
398 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
399 system.cpu.icache.fast_writes 0 # number of fast writes performed
400 system.cpu.icache.cache_copies 0 # number of cache copies performed
401 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1879 # number of ReadReq MSHR hits
402 system.cpu.icache.ReadReq_mshr_hits::total 1879 # number of ReadReq MSHR hits
403 system.cpu.icache.demand_mshr_hits::cpu.inst 1879 # number of demand (read+write) MSHR hits
404 system.cpu.icache.demand_mshr_hits::total 1879 # number of demand (read+write) MSHR hits
405 system.cpu.icache.overall_mshr_hits::cpu.inst 1879 # number of overall MSHR hits
406 system.cpu.icache.overall_mshr_hits::total 1879 # number of overall MSHR hits
407 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9520 # number of ReadReq MSHR misses
408 system.cpu.icache.ReadReq_mshr_misses::total 9520 # number of ReadReq MSHR misses
409 system.cpu.icache.demand_mshr_misses::cpu.inst 9520 # number of demand (read+write) MSHR misses
410 system.cpu.icache.demand_mshr_misses::total 9520 # number of demand (read+write) MSHR misses
411 system.cpu.icache.overall_mshr_misses::cpu.inst 9520 # number of overall MSHR misses
412 system.cpu.icache.overall_mshr_misses::total 9520 # number of overall MSHR misses
413 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 266339500 # number of ReadReq MSHR miss cycles
414 system.cpu.icache.ReadReq_mshr_miss_latency::total 266339500 # number of ReadReq MSHR miss cycles
415 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 266339500 # number of demand (read+write) MSHR miss cycles
416 system.cpu.icache.demand_mshr_miss_latency::total 266339500 # number of demand (read+write) MSHR miss cycles
417 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 266339500 # number of overall MSHR miss cycles
418 system.cpu.icache.overall_mshr_miss_latency::total 266339500 # number of overall MSHR miss cycles
419 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for ReadReq accesses
420 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000956 # mshr miss rate for ReadReq accesses
421 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for demand accesses
422 system.cpu.icache.demand_mshr_miss_rate::total 0.000956 # mshr miss rate for demand accesses
423 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for overall accesses
424 system.cpu.icache.overall_mshr_miss_rate::total 0.000956 # mshr miss rate for overall accesses
425 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27976.838235 # average ReadReq mshr miss latency
426 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27976.838235 # average ReadReq mshr miss latency
427 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27976.838235 # average overall mshr miss latency
428 system.cpu.icache.demand_avg_mshr_miss_latency::total 27976.838235 # average overall mshr miss latency
429 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27976.838235 # average overall mshr miss latency
430 system.cpu.icache.overall_avg_mshr_miss_latency::total 27976.838235 # average overall mshr miss latency
431 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
432 system.cpu.toL2Bus.throughput 18195687 # Throughput (bytes/s)
433 system.cpu.toL2Bus.trans_dist::ReadReq 9995 # Transaction distribution
434 system.cpu.toL2Bus.trans_dist::ReadResp 9995 # Transaction distribution
435 system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution
436 system.cpu.toL2Bus.trans_dist::ReadExReq 1748 # Transaction distribution
437 system.cpu.toL2Bus.trans_dist::ReadExResp 1748 # Transaction distribution
438 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19040 # Packet count per connected master and slave (bytes)
439 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4553 # Packet count per connected master and slave (bytes)
440 system.cpu.toL2Bus.pkt_count::total 23593 # Packet count per connected master and slave (bytes)
441 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 609280 # Cumulative packet size per connected master and slave (bytes)
442 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149120 # Cumulative packet size per connected master and slave (bytes)
443 system.cpu.toL2Bus.tot_pkt_size::total 758400 # Cumulative packet size per connected master and slave (bytes)
444 system.cpu.toL2Bus.data_through_bus 758400 # Total data (bytes)
445 system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
446 system.cpu.toL2Bus.reqLayer0.occupancy 6032000 # Layer occupancy (ticks)
447 system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
448 system.cpu.toL2Bus.respLayer0.occupancy 14812000 # Layer occupancy (ticks)
449 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
450 system.cpu.toL2Bus.respLayer1.occupancy 3559500 # Layer occupancy (ticks)
451 system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
452 system.cpu.l2cache.tags.replacements 0 # number of replacements
453 system.cpu.l2cache.tags.tagsinuse 2189.577948 # Cycle average of tags in use
454 system.cpu.l2cache.tags.total_refs 6793 # Total number of references to valid blocks.
455 system.cpu.l2cache.tags.sampled_refs 3282 # Sample count of references to valid blocks.
456 system.cpu.l2cache.tags.avg_refs 2.069775 # Average number of references to valid blocks.
457 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
458 system.cpu.l2cache.tags.occ_blocks::writebacks 17.842967 # Average occupied blocks per requestor
459 system.cpu.l2cache.tags.occ_blocks::cpu.inst 1820.748644 # Average occupied blocks per requestor
460 system.cpu.l2cache.tags.occ_blocks::cpu.data 350.986337 # Average occupied blocks per requestor
461 system.cpu.l2cache.tags.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy
462 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055565 # Average percentage of cache occupancy
463 system.cpu.l2cache.tags.occ_percent::cpu.data 0.010711 # Average percentage of cache occupancy
464 system.cpu.l2cache.tags.occ_percent::total 0.066821 # Average percentage of cache occupancy
465 system.cpu.l2cache.ReadReq_hits::cpu.inst 6726 # number of ReadReq hits
466 system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits
467 system.cpu.l2cache.ReadReq_hits::total 6779 # number of ReadReq hits
468 system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits
469 system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits
470 system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits
471 system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits
472 system.cpu.l2cache.demand_hits::cpu.inst 6726 # number of demand (read+write) hits
473 system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits
474 system.cpu.l2cache.demand_hits::total 6805 # number of demand (read+write) hits
475 system.cpu.l2cache.overall_hits::cpu.inst 6726 # number of overall hits
476 system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits
477 system.cpu.l2cache.overall_hits::total 6805 # number of overall hits
478 system.cpu.l2cache.ReadReq_misses::cpu.inst 2794 # number of ReadReq misses
479 system.cpu.l2cache.ReadReq_misses::cpu.data 422 # number of ReadReq misses
480 system.cpu.l2cache.ReadReq_misses::total 3216 # number of ReadReq misses
481 system.cpu.l2cache.ReadExReq_misses::cpu.data 1722 # number of ReadExReq misses
482 system.cpu.l2cache.ReadExReq_misses::total 1722 # number of ReadExReq misses
483 system.cpu.l2cache.demand_misses::cpu.inst 2794 # number of demand (read+write) misses
484 system.cpu.l2cache.demand_misses::cpu.data 2144 # number of demand (read+write) misses
485 system.cpu.l2cache.demand_misses::total 4938 # number of demand (read+write) misses
486 system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses
487 system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses
488 system.cpu.l2cache.overall_misses::total 4938 # number of overall misses
489 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 189282000 # number of ReadReq miss cycles
490 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32395250 # number of ReadReq miss cycles
491 system.cpu.l2cache.ReadReq_miss_latency::total 221677250 # number of ReadReq miss cycles
492 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 122425750 # number of ReadExReq miss cycles
493 system.cpu.l2cache.ReadExReq_miss_latency::total 122425750 # number of ReadExReq miss cycles
494 system.cpu.l2cache.demand_miss_latency::cpu.inst 189282000 # number of demand (read+write) miss cycles
495 system.cpu.l2cache.demand_miss_latency::cpu.data 154821000 # number of demand (read+write) miss cycles
496 system.cpu.l2cache.demand_miss_latency::total 344103000 # number of demand (read+write) miss cycles
497 system.cpu.l2cache.overall_miss_latency::cpu.inst 189282000 # number of overall miss cycles
498 system.cpu.l2cache.overall_miss_latency::cpu.data 154821000 # number of overall miss cycles
499 system.cpu.l2cache.overall_miss_latency::total 344103000 # number of overall miss cycles
500 system.cpu.l2cache.ReadReq_accesses::cpu.inst 9520 # number of ReadReq accesses(hits+misses)
501 system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses)
502 system.cpu.l2cache.ReadReq_accesses::total 9995 # number of ReadReq accesses(hits+misses)
503 system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses)
504 system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses)
505 system.cpu.l2cache.ReadExReq_accesses::cpu.data 1748 # number of ReadExReq accesses(hits+misses)
506 system.cpu.l2cache.ReadExReq_accesses::total 1748 # number of ReadExReq accesses(hits+misses)
507 system.cpu.l2cache.demand_accesses::cpu.inst 9520 # number of demand (read+write) accesses
508 system.cpu.l2cache.demand_accesses::cpu.data 2223 # number of demand (read+write) accesses
509 system.cpu.l2cache.demand_accesses::total 11743 # number of demand (read+write) accesses
510 system.cpu.l2cache.overall_accesses::cpu.inst 9520 # number of overall (read+write) accesses
511 system.cpu.l2cache.overall_accesses::cpu.data 2223 # number of overall (read+write) accesses
512 system.cpu.l2cache.overall_accesses::total 11743 # number of overall (read+write) accesses
513 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.293487 # miss rate for ReadReq accesses
514 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.888421 # miss rate for ReadReq accesses
515 system.cpu.l2cache.ReadReq_miss_rate::total 0.321761 # miss rate for ReadReq accesses
516 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses
517 system.cpu.l2cache.ReadExReq_miss_rate::total 0.985126 # miss rate for ReadExReq accesses
518 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.293487 # miss rate for demand accesses
519 system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses
520 system.cpu.l2cache.demand_miss_rate::total 0.420506 # miss rate for demand accesses
521 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.293487 # miss rate for overall accesses
522 system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses
523 system.cpu.l2cache.overall_miss_rate::total 0.420506 # miss rate for overall accesses
524 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67745.884037 # average ReadReq miss latency
525 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76765.995261 # average ReadReq miss latency
526 system.cpu.l2cache.ReadReq_avg_miss_latency::total 68929.493159 # average ReadReq miss latency
527 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71095.092915 # average ReadExReq miss latency
528 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71095.092915 # average ReadExReq miss latency
529 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67745.884037 # average overall miss latency
530 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72211.287313 # average overall miss latency
531 system.cpu.l2cache.demand_avg_miss_latency::total 69684.690158 # average overall miss latency
532 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67745.884037 # average overall miss latency
533 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72211.287313 # average overall miss latency
534 system.cpu.l2cache.overall_avg_miss_latency::total 69684.690158 # average overall miss latency
535 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
536 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
537 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
538 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
539 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
540 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
541 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
542 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
543 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2794 # number of ReadReq MSHR misses
544 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 422 # number of ReadReq MSHR misses
545 system.cpu.l2cache.ReadReq_mshr_misses::total 3216 # number of ReadReq MSHR misses
546 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1722 # number of ReadExReq MSHR misses
547 system.cpu.l2cache.ReadExReq_mshr_misses::total 1722 # number of ReadExReq MSHR misses
548 system.cpu.l2cache.demand_mshr_misses::cpu.inst 2794 # number of demand (read+write) MSHR misses
549 system.cpu.l2cache.demand_mshr_misses::cpu.data 2144 # number of demand (read+write) MSHR misses
550 system.cpu.l2cache.demand_mshr_misses::total 4938 # number of demand (read+write) MSHR misses
551 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses
552 system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses
553 system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses
554 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 154136500 # number of ReadReq MSHR miss cycles
555 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27132250 # number of ReadReq MSHR miss cycles
556 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 181268750 # number of ReadReq MSHR miss cycles
557 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 101289750 # number of ReadExReq MSHR miss cycles
558 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 101289750 # number of ReadExReq MSHR miss cycles
559 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 154136500 # number of demand (read+write) MSHR miss cycles
560 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 128422000 # number of demand (read+write) MSHR miss cycles
561 system.cpu.l2cache.demand_mshr_miss_latency::total 282558500 # number of demand (read+write) MSHR miss cycles
562 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 154136500 # number of overall MSHR miss cycles
563 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 128422000 # number of overall MSHR miss cycles
564 system.cpu.l2cache.overall_mshr_miss_latency::total 282558500 # number of overall MSHR miss cycles
565 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for ReadReq accesses
566 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses
567 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321761 # mshr miss rate for ReadReq accesses
568 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses
569 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985126 # mshr miss rate for ReadExReq accesses
570 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for demand accesses
571 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses
572 system.cpu.l2cache.demand_mshr_miss_rate::total 0.420506 # mshr miss rate for demand accesses
573 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for overall accesses
574 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses
575 system.cpu.l2cache.overall_mshr_miss_rate::total 0.420506 # mshr miss rate for overall accesses
576 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55166.964925 # average ReadReq mshr miss latency
577 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64294.431280 # average ReadReq mshr miss latency
578 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56364.661070 # average ReadReq mshr miss latency
579 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58820.993031 # average ReadExReq mshr miss latency
580 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58820.993031 # average ReadExReq mshr miss latency
581 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55166.964925 # average overall mshr miss latency
582 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59898.320896 # average overall mshr miss latency
583 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57221.243418 # average overall mshr miss latency
584 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55166.964925 # average overall mshr miss latency
585 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59898.320896 # average overall mshr miss latency
586 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57221.243418 # average overall mshr miss latency
587 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
588 system.cpu.dcache.tags.replacements 157 # number of replacements
589 system.cpu.dcache.tags.tagsinuse 1441.367780 # Cycle average of tags in use
590 system.cpu.dcache.tags.total_refs 26488450 # Total number of references to valid blocks.
591 system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks.
592 system.cpu.dcache.tags.avg_refs 11915.632029 # Average number of references to valid blocks.
593 system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
594 system.cpu.dcache.tags.occ_blocks::cpu.data 1441.367780 # Average occupied blocks per requestor
595 system.cpu.dcache.tags.occ_percent::cpu.data 0.351896 # Average percentage of cache occupancy
596 system.cpu.dcache.tags.occ_percent::total 0.351896 # Average percentage of cache occupancy
597 system.cpu.dcache.ReadReq_hits::cpu.data 19995621 # number of ReadReq hits
598 system.cpu.dcache.ReadReq_hits::total 19995621 # number of ReadReq hits
599 system.cpu.dcache.WriteReq_hits::cpu.data 6492829 # number of WriteReq hits
600 system.cpu.dcache.WriteReq_hits::total 6492829 # number of WriteReq hits
601 system.cpu.dcache.demand_hits::cpu.data 26488450 # number of demand (read+write) hits
602 system.cpu.dcache.demand_hits::total 26488450 # number of demand (read+write) hits
603 system.cpu.dcache.overall_hits::cpu.data 26488450 # number of overall hits
604 system.cpu.dcache.overall_hits::total 26488450 # number of overall hits
605 system.cpu.dcache.ReadReq_misses::cpu.data 577 # number of ReadReq misses
606 system.cpu.dcache.ReadReq_misses::total 577 # number of ReadReq misses
607 system.cpu.dcache.WriteReq_misses::cpu.data 8274 # number of WriteReq misses
608 system.cpu.dcache.WriteReq_misses::total 8274 # number of WriteReq misses
609 system.cpu.dcache.demand_misses::cpu.data 8851 # number of demand (read+write) misses
610 system.cpu.dcache.demand_misses::total 8851 # number of demand (read+write) misses
611 system.cpu.dcache.overall_misses::cpu.data 8851 # number of overall misses
612 system.cpu.dcache.overall_misses::total 8851 # number of overall misses
613 system.cpu.dcache.ReadReq_miss_latency::cpu.data 41023250 # number of ReadReq miss cycles
614 system.cpu.dcache.ReadReq_miss_latency::total 41023250 # number of ReadReq miss cycles
615 system.cpu.dcache.WriteReq_miss_latency::cpu.data 492650500 # number of WriteReq miss cycles
616 system.cpu.dcache.WriteReq_miss_latency::total 492650500 # number of WriteReq miss cycles
617 system.cpu.dcache.demand_miss_latency::cpu.data 533673750 # number of demand (read+write) miss cycles
618 system.cpu.dcache.demand_miss_latency::total 533673750 # number of demand (read+write) miss cycles
619 system.cpu.dcache.overall_miss_latency::cpu.data 533673750 # number of overall miss cycles
620 system.cpu.dcache.overall_miss_latency::total 533673750 # number of overall miss cycles
621 system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses)
622 system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses)
623 system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
624 system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses)
625 system.cpu.dcache.demand_accesses::cpu.data 26497301 # number of demand (read+write) accesses
626 system.cpu.dcache.demand_accesses::total 26497301 # number of demand (read+write) accesses
627 system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses
628 system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses
629 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000029 # miss rate for ReadReq accesses
630 system.cpu.dcache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses
631 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001273 # miss rate for WriteReq accesses
632 system.cpu.dcache.WriteReq_miss_rate::total 0.001273 # miss rate for WriteReq accesses
633 system.cpu.dcache.demand_miss_rate::cpu.data 0.000334 # miss rate for demand accesses
634 system.cpu.dcache.demand_miss_rate::total 0.000334 # miss rate for demand accesses
635 system.cpu.dcache.overall_miss_rate::cpu.data 0.000334 # miss rate for overall accesses
636 system.cpu.dcache.overall_miss_rate::total 0.000334 # miss rate for overall accesses
637 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71097.487002 # average ReadReq miss latency
638 system.cpu.dcache.ReadReq_avg_miss_latency::total 71097.487002 # average ReadReq miss latency
639 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59541.999033 # average WriteReq miss latency
640 system.cpu.dcache.WriteReq_avg_miss_latency::total 59541.999033 # average WriteReq miss latency
641 system.cpu.dcache.demand_avg_miss_latency::cpu.data 60295.305615 # average overall miss latency
642 system.cpu.dcache.demand_avg_miss_latency::total 60295.305615 # average overall miss latency
643 system.cpu.dcache.overall_avg_miss_latency::cpu.data 60295.305615 # average overall miss latency
644 system.cpu.dcache.overall_avg_miss_latency::total 60295.305615 # average overall miss latency
645 system.cpu.dcache.blocked_cycles::no_mshrs 23884 # number of cycles access was blocked
646 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
647 system.cpu.dcache.blocked::no_mshrs 841 # number of cycles access was blocked
648 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
649 system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.399524 # average number of cycles each access was blocked
650 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
651 system.cpu.dcache.fast_writes 0 # number of fast writes performed
652 system.cpu.dcache.cache_copies 0 # number of cache copies performed
653 system.cpu.dcache.writebacks::writebacks 107 # number of writebacks
654 system.cpu.dcache.writebacks::total 107 # number of writebacks
655 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 102 # number of ReadReq MSHR hits
656 system.cpu.dcache.ReadReq_mshr_hits::total 102 # number of ReadReq MSHR hits
657 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6526 # number of WriteReq MSHR hits
658 system.cpu.dcache.WriteReq_mshr_hits::total 6526 # number of WriteReq MSHR hits
659 system.cpu.dcache.demand_mshr_hits::cpu.data 6628 # number of demand (read+write) MSHR hits
660 system.cpu.dcache.demand_mshr_hits::total 6628 # number of demand (read+write) MSHR hits
661 system.cpu.dcache.overall_mshr_hits::cpu.data 6628 # number of overall MSHR hits
662 system.cpu.dcache.overall_mshr_hits::total 6628 # number of overall MSHR hits
663 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses
664 system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses
665 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses
666 system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses
667 system.cpu.dcache.demand_mshr_misses::cpu.data 2223 # number of demand (read+write) MSHR misses
668 system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses
669 system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses
670 system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses
671 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33418750 # number of ReadReq MSHR miss cycles
672 system.cpu.dcache.ReadReq_mshr_miss_latency::total 33418750 # number of ReadReq MSHR miss cycles
673 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 124443250 # number of WriteReq MSHR miss cycles
674 system.cpu.dcache.WriteReq_mshr_miss_latency::total 124443250 # number of WriteReq MSHR miss cycles
675 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 157862000 # number of demand (read+write) MSHR miss cycles
676 system.cpu.dcache.demand_mshr_miss_latency::total 157862000 # number of demand (read+write) MSHR miss cycles
677 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 157862000 # number of overall MSHR miss cycles
678 system.cpu.dcache.overall_mshr_miss_latency::total 157862000 # number of overall MSHR miss cycles
679 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
680 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
681 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses
682 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000269 # mshr miss rate for WriteReq accesses
683 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses
684 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
685 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
686 system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
687 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70355.263158 # average ReadReq mshr miss latency
688 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70355.263158 # average ReadReq mshr miss latency
689 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71191.790618 # average WriteReq mshr miss latency
690 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71191.790618 # average WriteReq mshr miss latency
691 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71013.045434 # average overall mshr miss latency
692 system.cpu.dcache.demand_avg_mshr_miss_latency::total 71013.045434 # average overall mshr miss latency
693 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71013.045434 # average overall mshr miss latency
694 system.cpu.dcache.overall_avg_mshr_miss_latency::total 71013.045434 # average overall mshr miss latency
695 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
697 ---------- End Simulation Statistics ----------
projects / gem5.git / blob