tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 eventq_index=0
  18 init_param=0
  19 kernel=
  20 load_addr_mask=1099511627775
  21 load_offset=0
  22 mem_mode=timing
  23 mem_ranges=
  24 memories=system.physmem
  25 num_work_ids=16
  26 readfile=
  27 symbolfile=
  28 work_begin_ckpt_count=0
  29 work_begin_cpu_id_exit=-1
  30 work_begin_exit_count=0
  31 work_cpus_ckpt_count=0
  32 work_end_ckpt_count=0
  33 work_end_exit_count=0
  34 work_item_id=-1
  35 system_port=system.membus.slave[0]
  36
  37 [system.clk_domain]
  38 type=SrcClockDomain
  39 clock=1000
  40 eventq_index=0
  41 voltage_domain=system.voltage_domain
  42
  43 [system.cpu]
  44 type=DerivO3CPU
  45 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
  46 LFSTSize=1024
  47 LQEntries=32
  48 LSQCheckLoads=true
  49 LSQDepCheckShift=4
  50 SQEntries=32
  51 SSITSize=1024
  52 activity=0
  53 backComSize=5
  54 branchPred=system.cpu.branchPred
  55 cachePorts=200
  56 checker=Null
  57 clk_domain=system.cpu_clk_domain
  58 commitToDecodeDelay=1
  59 commitToFetchDelay=1
  60 commitToIEWDelay=1
  61 commitToRenameDelay=1
  62 commitWidth=8
  63 cpu_id=0
  64 decodeToFetchDelay=1
  65 decodeToRenameDelay=1
  66 decodeWidth=8
  67 dispatchWidth=8
  68 do_checkpoint_insts=true
  69 do_quiesce=true
  70 do_statistics_insts=true
  71 dtb=system.cpu.dtb
  72 eventq_index=0
  73 fetchBufferSize=64
  74 fetchToDecodeDelay=1
  75 fetchTrapLatency=1
  76 fetchWidth=8
  77 forwardComSize=5
  78 fuPool=system.cpu.fuPool
  79 function_trace=false
  80 function_trace_start=0
  81 iewToCommitDelay=1
  82 iewToDecodeDelay=1
  83 iewToFetchDelay=1
  84 iewToRenameDelay=1
  85 interrupts=system.cpu.interrupts
  86 isa=system.cpu.isa
  87 issueToExecuteDelay=1
  88 issueWidth=8
  89 itb=system.cpu.itb
  90 max_insts_all_threads=0
  91 max_insts_any_thread=0
  92 max_loads_all_threads=0
  93 max_loads_any_thread=0
  94 needsTSO=false
  95 numIQEntries=64
  96 numPhysCCRegs=0
  97 numPhysFloatRegs=256
  98 numPhysIntRegs=256
  99 numROBEntries=192
 100 numRobs=1
 101 numThreads=1
 102 profile=0
 103 progress_interval=0
 104 renameToDecodeDelay=1
 105 renameToFetchDelay=1
 106 renameToIEWDelay=2
 107 renameToROBDelay=1
 108 renameWidth=8
 109 simpoint_start_insts=
 110 smtCommitPolicy=RoundRobin
 111 smtFetchPolicy=SingleThread
 112 smtIQPolicy=Partitioned
 113 smtIQThreshold=100
 114 smtLSQPolicy=Partitioned
 115 smtLSQThreshold=100
 116 smtNumFetchingThreads=1
 117 smtROBPolicy=Partitioned
 118 smtROBThreshold=100
 119 socket_id=0
 120 squashWidth=8
 121 store_set_clear_period=250000
 122 switched_out=false
 123 system=system
 124 tracer=system.cpu.tracer
 125 trapLatency=13
 126 wbDepth=1
 127 wbWidth=8
 128 workload=system.cpu.workload
 129 dcache_port=system.cpu.dcache.cpu_side
 130 icache_port=system.cpu.icache.cpu_side
 131
 132 [system.cpu.branchPred]
 133 type=BranchPredictor
 134 BTBEntries=4096
 135 BTBTagSize=16
 136 RASSize=16
 137 choiceCtrBits=2
 138 choicePredictorSize=8192
 139 eventq_index=0
 140 globalCtrBits=2
 141 globalPredictorSize=8192
 142 instShiftAmt=2
 143 localCtrBits=2
 144 localHistoryTableSize=2048
 145 localPredictorSize=2048
 146 numThreads=1
 147 predType=tournament
 148
 149 [system.cpu.dcache]
 150 type=BaseCache
 151 children=tags
 152 addr_ranges=0:18446744073709551615
 153 assoc=2
 154 clk_domain=system.cpu_clk_domain
 155 eventq_index=0
 156 forward_snoops=true
 157 hit_latency=2
 158 is_top_level=true
 159 max_miss_count=0
 160 mshrs=4
 161 prefetch_on_access=false
 162 prefetcher=Null
 163 response_latency=2
 164 sequential_access=false
 165 size=262144
 166 system=system
 167 tags=system.cpu.dcache.tags
 168 tgts_per_mshr=20
 169 two_queue=false
 170 write_buffers=8
 171 cpu_side=system.cpu.dcache_port
 172 mem_side=system.cpu.toL2Bus.slave[1]
 173
 174 [system.cpu.dcache.tags]
 175 type=LRU
 176 assoc=2
 177 block_size=64
 178 clk_domain=system.cpu_clk_domain
 179 eventq_index=0
 180 hit_latency=2
 181 sequential_access=false
 182 size=262144
 183
 184 [system.cpu.dtb]
 185 type=AlphaTLB
 186 eventq_index=0
 187 size=64
 188
 189 [system.cpu.fuPool]
 190 type=FUPool
 191 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 192 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 193 eventq_index=0
 194
 195 [system.cpu.fuPool.FUList0]
 196 type=FUDesc
 197 children=opList
 198 count=6
 199 eventq_index=0
 200 opList=system.cpu.fuPool.FUList0.opList
 201
 202 [system.cpu.fuPool.FUList0.opList]
 203 type=OpDesc
 204 eventq_index=0
 205 issueLat=1
 206 opClass=IntAlu
 207 opLat=1
 208
 209 [system.cpu.fuPool.FUList1]
 210 type=FUDesc
 211 children=opList0 opList1
 212 count=2
 213 eventq_index=0
 214 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 215
 216 [system.cpu.fuPool.FUList1.opList0]
 217 type=OpDesc
 218 eventq_index=0
 219 issueLat=1
 220 opClass=IntMult
 221 opLat=3
 222
 223 [system.cpu.fuPool.FUList1.opList1]
 224 type=OpDesc
 225 eventq_index=0
 226 issueLat=19
 227 opClass=IntDiv
 228 opLat=20
 229
 230 [system.cpu.fuPool.FUList2]
 231 type=FUDesc
 232 children=opList0 opList1 opList2
 233 count=4
 234 eventq_index=0
 235 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 236
 237 [system.cpu.fuPool.FUList2.opList0]
 238 type=OpDesc
 239 eventq_index=0
 240 issueLat=1
 241 opClass=FloatAdd
 242 opLat=2
 243
 244 [system.cpu.fuPool.FUList2.opList1]
 245 type=OpDesc
 246 eventq_index=0
 247 issueLat=1
 248 opClass=FloatCmp
 249 opLat=2
 250
 251 [system.cpu.fuPool.FUList2.opList2]
 252 type=OpDesc
 253 eventq_index=0
 254 issueLat=1
 255 opClass=FloatCvt
 256 opLat=2
 257
 258 [system.cpu.fuPool.FUList3]
 259 type=FUDesc
 260 children=opList0 opList1 opList2
 261 count=2
 262 eventq_index=0
 263 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 264
 265 [system.cpu.fuPool.FUList3.opList0]
 266 type=OpDesc
 267 eventq_index=0
 268 issueLat=1
 269 opClass=FloatMult
 270 opLat=4
 271
 272 [system.cpu.fuPool.FUList3.opList1]
 273 type=OpDesc
 274 eventq_index=0
 275 issueLat=12
 276 opClass=FloatDiv
 277 opLat=12
 278
 279 [system.cpu.fuPool.FUList3.opList2]
 280 type=OpDesc
 281 eventq_index=0
 282 issueLat=24
 283 opClass=FloatSqrt
 284 opLat=24
 285
 286 [system.cpu.fuPool.FUList4]
 287 type=FUDesc
 288 children=opList
 289 count=0
 290 eventq_index=0
 291 opList=system.cpu.fuPool.FUList4.opList
 292
 293 [system.cpu.fuPool.FUList4.opList]
 294 type=OpDesc
 295 eventq_index=0
 296 issueLat=1
 297 opClass=MemRead
 298 opLat=1
 299
 300 [system.cpu.fuPool.FUList5]
 301 type=FUDesc
 302 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 303 count=4
 304 eventq_index=0
 305 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 306
 307 [system.cpu.fuPool.FUList5.opList00]
 308 type=OpDesc
 309 eventq_index=0
 310 issueLat=1
 311 opClass=SimdAdd
 312 opLat=1
 313
 314 [system.cpu.fuPool.FUList5.opList01]
 315 type=OpDesc
 316 eventq_index=0
 317 issueLat=1
 318 opClass=SimdAddAcc
 319 opLat=1
 320
 321 [system.cpu.fuPool.FUList5.opList02]
 322 type=OpDesc
 323 eventq_index=0
 324 issueLat=1
 325 opClass=SimdAlu
 326 opLat=1
 327
 328 [system.cpu.fuPool.FUList5.opList03]
 329 type=OpDesc
 330 eventq_index=0
 331 issueLat=1
 332 opClass=SimdCmp
 333 opLat=1
 334
 335 [system.cpu.fuPool.FUList5.opList04]
 336 type=OpDesc
 337 eventq_index=0
 338 issueLat=1
 339 opClass=SimdCvt
 340 opLat=1
 341
 342 [system.cpu.fuPool.FUList5.opList05]
 343 type=OpDesc
 344 eventq_index=0
 345 issueLat=1
 346 opClass=SimdMisc
 347 opLat=1
 348
 349 [system.cpu.fuPool.FUList5.opList06]
 350 type=OpDesc
 351 eventq_index=0
 352 issueLat=1
 353 opClass=SimdMult
 354 opLat=1
 355
 356 [system.cpu.fuPool.FUList5.opList07]
 357 type=OpDesc
 358 eventq_index=0
 359 issueLat=1
 360 opClass=SimdMultAcc
 361 opLat=1
 362
 363 [system.cpu.fuPool.FUList5.opList08]
 364 type=OpDesc
 365 eventq_index=0
 366 issueLat=1
 367 opClass=SimdShift
 368 opLat=1
 369
 370 [system.cpu.fuPool.FUList5.opList09]
 371 type=OpDesc
 372 eventq_index=0
 373 issueLat=1
 374 opClass=SimdShiftAcc
 375 opLat=1
 376
 377 [system.cpu.fuPool.FUList5.opList10]
 378 type=OpDesc
 379 eventq_index=0
 380 issueLat=1
 381 opClass=SimdSqrt
 382 opLat=1
 383
 384 [system.cpu.fuPool.FUList5.opList11]
 385 type=OpDesc
 386 eventq_index=0
 387 issueLat=1
 388 opClass=SimdFloatAdd
 389 opLat=1
 390
 391 [system.cpu.fuPool.FUList5.opList12]
 392 type=OpDesc
 393 eventq_index=0
 394 issueLat=1
 395 opClass=SimdFloatAlu
 396 opLat=1
 397
 398 [system.cpu.fuPool.FUList5.opList13]
 399 type=OpDesc
 400 eventq_index=0
 401 issueLat=1
 402 opClass=SimdFloatCmp
 403 opLat=1
 404
 405 [system.cpu.fuPool.FUList5.opList14]
 406 type=OpDesc
 407 eventq_index=0
 408 issueLat=1
 409 opClass=SimdFloatCvt
 410 opLat=1
 411
 412 [system.cpu.fuPool.FUList5.opList15]
 413 type=OpDesc
 414 eventq_index=0
 415 issueLat=1
 416 opClass=SimdFloatDiv
 417 opLat=1
 418
 419 [system.cpu.fuPool.FUList5.opList16]
 420 type=OpDesc
 421 eventq_index=0
 422 issueLat=1
 423 opClass=SimdFloatMisc
 424 opLat=1
 425
 426 [system.cpu.fuPool.FUList5.opList17]
 427 type=OpDesc
 428 eventq_index=0
 429 issueLat=1
 430 opClass=SimdFloatMult
 431 opLat=1
 432
 433 [system.cpu.fuPool.FUList5.opList18]
 434 type=OpDesc
 435 eventq_index=0
 436 issueLat=1
 437 opClass=SimdFloatMultAcc
 438 opLat=1
 439
 440 [system.cpu.fuPool.FUList5.opList19]
 441 type=OpDesc
 442 eventq_index=0
 443 issueLat=1
 444 opClass=SimdFloatSqrt
 445 opLat=1
 446
 447 [system.cpu.fuPool.FUList6]
 448 type=FUDesc
 449 children=opList
 450 count=0
 451 eventq_index=0
 452 opList=system.cpu.fuPool.FUList6.opList
 453
 454 [system.cpu.fuPool.FUList6.opList]
 455 type=OpDesc
 456 eventq_index=0
 457 issueLat=1
 458 opClass=MemWrite
 459 opLat=1
 460
 461 [system.cpu.fuPool.FUList7]
 462 type=FUDesc
 463 children=opList0 opList1
 464 count=4
 465 eventq_index=0
 466 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 467
 468 [system.cpu.fuPool.FUList7.opList0]
 469 type=OpDesc
 470 eventq_index=0
 471 issueLat=1
 472 opClass=MemRead
 473 opLat=1
 474
 475 [system.cpu.fuPool.FUList7.opList1]
 476 type=OpDesc
 477 eventq_index=0
 478 issueLat=1
 479 opClass=MemWrite
 480 opLat=1
 481
 482 [system.cpu.fuPool.FUList8]
 483 type=FUDesc
 484 children=opList
 485 count=1
 486 eventq_index=0
 487 opList=system.cpu.fuPool.FUList8.opList
 488
 489 [system.cpu.fuPool.FUList8.opList]
 490 type=OpDesc
 491 eventq_index=0
 492 issueLat=3
 493 opClass=IprAccess
 494 opLat=3
 495
 496 [system.cpu.icache]
 497 type=BaseCache
 498 children=tags
 499 addr_ranges=0:18446744073709551615
 500 assoc=2
 501 clk_domain=system.cpu_clk_domain
 502 eventq_index=0
 503 forward_snoops=true
 504 hit_latency=2
 505 is_top_level=true
 506 max_miss_count=0
 507 mshrs=4
 508 prefetch_on_access=false
 509 prefetcher=Null
 510 response_latency=2
 511 sequential_access=false
 512 size=131072
 513 system=system
 514 tags=system.cpu.icache.tags
 515 tgts_per_mshr=20
 516 two_queue=false
 517 write_buffers=8
 518 cpu_side=system.cpu.icache_port
 519 mem_side=system.cpu.toL2Bus.slave[0]
 520
 521 [system.cpu.icache.tags]
 522 type=LRU
 523 assoc=2
 524 block_size=64
 525 clk_domain=system.cpu_clk_domain
 526 eventq_index=0
 527 hit_latency=2
 528 sequential_access=false
 529 size=131072
 530
 531 [system.cpu.interrupts]
 532 type=AlphaInterrupts
 533 eventq_index=0
 534
 535 [system.cpu.isa]
 536 type=AlphaISA
 537 eventq_index=0
 538 system=system
 539
 540 [system.cpu.itb]
 541 type=AlphaTLB
 542 eventq_index=0
 543 size=48
 544
 545 [system.cpu.l2cache]
 546 type=BaseCache
 547 children=tags
 548 addr_ranges=0:18446744073709551615
 549 assoc=8
 550 clk_domain=system.cpu_clk_domain
 551 eventq_index=0
 552 forward_snoops=true
 553 hit_latency=20
 554 is_top_level=false
 555 max_miss_count=0
 556 mshrs=20
 557 prefetch_on_access=false
 558 prefetcher=Null
 559 response_latency=20
 560 sequential_access=false
 561 size=2097152
 562 system=system
 563 tags=system.cpu.l2cache.tags
 564 tgts_per_mshr=12
 565 two_queue=false
 566 write_buffers=8
 567 cpu_side=system.cpu.toL2Bus.master[0]
 568 mem_side=system.membus.slave[1]
 569
 570 [system.cpu.l2cache.tags]
 571 type=LRU
 572 assoc=8
 573 block_size=64
 574 clk_domain=system.cpu_clk_domain
 575 eventq_index=0
 576 hit_latency=20
 577 sequential_access=false
 578 size=2097152
 579
 580 [system.cpu.toL2Bus]
 581 type=CoherentBus
 582 clk_domain=system.cpu_clk_domain
 583 eventq_index=0
 584 header_cycles=1
 585 system=system
 586 use_default_range=false
 587 width=32
 588 master=system.cpu.l2cache.cpu_side
 589 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 590
 591 [system.cpu.tracer]
 592 type=ExeTracer
 593 eventq_index=0
 594
 595 [system.cpu.workload]
 596 type=LiveProcess
 597 cmd=twolf smred
 598 cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing
 599 egid=100
 600 env=
 601 errout=cerr
 602 euid=100
 603 eventq_index=0
 604 executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/twolf
 605 gid=100
 606 input=cin
 607 max_stack_size=67108864
 608 output=cout
 609 pid=100
 610 ppid=99
 611 simpoint=0
 612 system=system
 613 uid=100
 614
 615 [system.cpu_clk_domain]
 616 type=SrcClockDomain
 617 clock=500
 618 eventq_index=0
 619 voltage_domain=system.voltage_domain
 620
 621 [system.membus]
 622 type=CoherentBus
 623 clk_domain=system.clk_domain
 624 eventq_index=0
 625 header_cycles=1
 626 system=system
 627 use_default_range=false
 628 width=8
 629 master=system.physmem.port
 630 slave=system.system_port system.cpu.l2cache.mem_side
 631
 632 [system.physmem]
 633 type=DRAMCtrl
 634 activation_limit=4
 635 addr_mapping=RoRaBaChCo
 636 banks_per_rank=8
 637 burst_length=8
 638 channels=1
 639 clk_domain=system.clk_domain
 640 conf_table_reported=true
 641 device_bus_width=8
 642 device_rowbuffer_size=1024
 643 devices_per_rank=8
 644 eventq_index=0
 645 in_addr_map=true
 646 max_accesses_per_row=16
 647 mem_sched_policy=frfcfs
 648 min_writes_per_switch=16
 649 null=false
 650 page_policy=open_adaptive
 651 range=0:134217727
 652 ranks_per_channel=2
 653 read_buffer_size=32
 654 static_backend_latency=10000
 655 static_frontend_latency=10000
 656 tBURST=5000
 657 tCK=1250
 658 tCL=13750
 659 tRAS=35000
 660 tRCD=13750
 661 tREFI=7800000
 662 tRFC=260000
 663 tRP=13750
 664 tRRD=6000
 665 tRTP=7500
 666 tRTW=2500
 667 tWR=15000
 668 tWTR=7500
 669 tXAW=30000
 670 write_buffer_size=64
 671 write_high_thresh_perc=85
 672 write_low_thresh_perc=50
 673 port=system.membus.master[0]
 674
 675 [system.voltage_domain]
 676 type=VoltageDomain
 677 eventq_index=0
 678 voltage=1.000000
 679