tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 full_system=false
   5 time_sync_enable=false
   6 time_sync_period=100000000000
   7 time_sync_spin_threshold=100000000
   8
   9 [system]
  10 type=System
  11 children=cpu membus physmem
  12 boot_osflags=a
  13 clock=1000
  14 init_param=0
  15 kernel=
  16 load_addr_mask=1099511627775
  17 mem_mode=timing
  18 mem_ranges=
  19 memories=system.physmem
  20 num_work_ids=16
  21 readfile=
  22 symbolfile=
  23 work_begin_ckpt_count=0
  24 work_begin_cpu_id_exit=-1
  25 work_begin_exit_count=0
  26 work_cpus_ckpt_count=0
  27 work_end_ckpt_count=0
  28 work_end_exit_count=0
  29 work_item_id=-1
  30 system_port=system.membus.slave[0]
  31
  32 [system.cpu]
  33 type=DerivO3CPU
  34 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
  35 LFSTSize=1024
  36 LQEntries=32
  37 LSQCheckLoads=true
  38 LSQDepCheckShift=4
  39 SQEntries=32
  40 SSITSize=1024
  41 activity=0
  42 backComSize=5
  43 branchPred=system.cpu.branchPred
  44 cachePorts=200
  45 checker=Null
  46 clock=500
  47 commitToDecodeDelay=1
  48 commitToFetchDelay=1
  49 commitToIEWDelay=1
  50 commitToRenameDelay=1
  51 commitWidth=8
  52 cpu_id=0
  53 decodeToFetchDelay=1
  54 decodeToRenameDelay=1
  55 decodeWidth=8
  56 dispatchWidth=8
  57 do_checkpoint_insts=true
  58 do_quiesce=true
  59 do_statistics_insts=true
  60 dtb=system.cpu.dtb
  61 fetchToDecodeDelay=1
  62 fetchTrapLatency=1
  63 fetchWidth=8
  64 forwardComSize=5
  65 fuPool=system.cpu.fuPool
  66 function_trace=false
  67 function_trace_start=0
  68 iewToCommitDelay=1
  69 iewToDecodeDelay=1
  70 iewToFetchDelay=1
  71 iewToRenameDelay=1
  72 interrupts=system.cpu.interrupts
  73 isa=system.cpu.isa
  74 issueToExecuteDelay=1
  75 issueWidth=8
  76 itb=system.cpu.itb
  77 max_insts_all_threads=0
  78 max_insts_any_thread=0
  79 max_loads_all_threads=0
  80 max_loads_any_thread=0
  81 needsTSO=false
  82 numIQEntries=64
  83 numPhysFloatRegs=256
  84 numPhysIntRegs=256
  85 numROBEntries=192
  86 numRobs=1
  87 numThreads=1
  88 profile=0
  89 progress_interval=0
  90 renameToDecodeDelay=1
  91 renameToFetchDelay=1
  92 renameToIEWDelay=2
  93 renameToROBDelay=1
  94 renameWidth=8
  95 smtCommitPolicy=RoundRobin
  96 smtFetchPolicy=SingleThread
  97 smtIQPolicy=Partitioned
  98 smtIQThreshold=100
  99 smtLSQPolicy=Partitioned
 100 smtLSQThreshold=100
 101 smtNumFetchingThreads=1
 102 smtROBPolicy=Partitioned
 103 smtROBThreshold=100
 104 squashWidth=8
 105 store_set_clear_period=250000
 106 switched_out=false
 107 system=system
 108 tracer=system.cpu.tracer
 109 trapLatency=13
 110 wbDepth=1
 111 wbWidth=8
 112 workload=system.cpu.workload
 113 dcache_port=system.cpu.dcache.cpu_side
 114 icache_port=system.cpu.icache.cpu_side
 115
 116 [system.cpu.branchPred]
 117 type=BranchPredictor
 118 BTBEntries=4096
 119 BTBTagSize=16
 120 RASSize=16
 121 choiceCtrBits=2
 122 choicePredictorSize=8192
 123 globalCtrBits=2
 124 globalHistoryBits=13
 125 globalPredictorSize=8192
 126 instShiftAmt=2
 127 localCtrBits=2
 128 localHistoryBits=11
 129 localHistoryTableSize=2048
 130 localPredictorSize=2048
 131 numThreads=1
 132 predType=tournament
 133
 134 [system.cpu.dcache]
 135 type=BaseCache
 136 addr_ranges=0:18446744073709551615
 137 assoc=2
 138 block_size=64
 139 clock=500
 140 forward_snoops=true
 141 hit_latency=2
 142 is_top_level=true
 143 max_miss_count=0
 144 mshrs=4
 145 prefetch_on_access=false
 146 prefetcher=Null
 147 response_latency=2
 148 size=262144
 149 system=system
 150 tgts_per_mshr=20
 151 two_queue=false
 152 write_buffers=8
 153 cpu_side=system.cpu.dcache_port
 154 mem_side=system.cpu.toL2Bus.slave[1]
 155
 156 [system.cpu.dtb]
 157 type=AlphaTLB
 158 size=64
 159
 160 [system.cpu.fuPool]
 161 type=FUPool
 162 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 163 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 164
 165 [system.cpu.fuPool.FUList0]
 166 type=FUDesc
 167 children=opList
 168 count=6
 169 opList=system.cpu.fuPool.FUList0.opList
 170
 171 [system.cpu.fuPool.FUList0.opList]
 172 type=OpDesc
 173 issueLat=1
 174 opClass=IntAlu
 175 opLat=1
 176
 177 [system.cpu.fuPool.FUList1]
 178 type=FUDesc
 179 children=opList0 opList1
 180 count=2
 181 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 182
 183 [system.cpu.fuPool.FUList1.opList0]
 184 type=OpDesc
 185 issueLat=1
 186 opClass=IntMult
 187 opLat=3
 188
 189 [system.cpu.fuPool.FUList1.opList1]
 190 type=OpDesc
 191 issueLat=19
 192 opClass=IntDiv
 193 opLat=20
 194
 195 [system.cpu.fuPool.FUList2]
 196 type=FUDesc
 197 children=opList0 opList1 opList2
 198 count=4
 199 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 200
 201 [system.cpu.fuPool.FUList2.opList0]
 202 type=OpDesc
 203 issueLat=1
 204 opClass=FloatAdd
 205 opLat=2
 206
 207 [system.cpu.fuPool.FUList2.opList1]
 208 type=OpDesc
 209 issueLat=1
 210 opClass=FloatCmp
 211 opLat=2
 212
 213 [system.cpu.fuPool.FUList2.opList2]
 214 type=OpDesc
 215 issueLat=1
 216 opClass=FloatCvt
 217 opLat=2
 218
 219 [system.cpu.fuPool.FUList3]
 220 type=FUDesc
 221 children=opList0 opList1 opList2
 222 count=2
 223 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 224
 225 [system.cpu.fuPool.FUList3.opList0]
 226 type=OpDesc
 227 issueLat=1
 228 opClass=FloatMult
 229 opLat=4
 230
 231 [system.cpu.fuPool.FUList3.opList1]
 232 type=OpDesc
 233 issueLat=12
 234 opClass=FloatDiv
 235 opLat=12
 236
 237 [system.cpu.fuPool.FUList3.opList2]
 238 type=OpDesc
 239 issueLat=24
 240 opClass=FloatSqrt
 241 opLat=24
 242
 243 [system.cpu.fuPool.FUList4]
 244 type=FUDesc
 245 children=opList
 246 count=0
 247 opList=system.cpu.fuPool.FUList4.opList
 248
 249 [system.cpu.fuPool.FUList4.opList]
 250 type=OpDesc
 251 issueLat=1
 252 opClass=MemRead
 253 opLat=1
 254
 255 [system.cpu.fuPool.FUList5]
 256 type=FUDesc
 257 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 258 count=4
 259 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 260
 261 [system.cpu.fuPool.FUList5.opList00]
 262 type=OpDesc
 263 issueLat=1
 264 opClass=SimdAdd
 265 opLat=1
 266
 267 [system.cpu.fuPool.FUList5.opList01]
 268 type=OpDesc
 269 issueLat=1
 270 opClass=SimdAddAcc
 271 opLat=1
 272
 273 [system.cpu.fuPool.FUList5.opList02]
 274 type=OpDesc
 275 issueLat=1
 276 opClass=SimdAlu
 277 opLat=1
 278
 279 [system.cpu.fuPool.FUList5.opList03]
 280 type=OpDesc
 281 issueLat=1
 282 opClass=SimdCmp
 283 opLat=1
 284
 285 [system.cpu.fuPool.FUList5.opList04]
 286 type=OpDesc
 287 issueLat=1
 288 opClass=SimdCvt
 289 opLat=1
 290
 291 [system.cpu.fuPool.FUList5.opList05]
 292 type=OpDesc
 293 issueLat=1
 294 opClass=SimdMisc
 295 opLat=1
 296
 297 [system.cpu.fuPool.FUList5.opList06]
 298 type=OpDesc
 299 issueLat=1
 300 opClass=SimdMult
 301 opLat=1
 302
 303 [system.cpu.fuPool.FUList5.opList07]
 304 type=OpDesc
 305 issueLat=1
 306 opClass=SimdMultAcc
 307 opLat=1
 308
 309 [system.cpu.fuPool.FUList5.opList08]
 310 type=OpDesc
 311 issueLat=1
 312 opClass=SimdShift
 313 opLat=1
 314
 315 [system.cpu.fuPool.FUList5.opList09]
 316 type=OpDesc
 317 issueLat=1
 318 opClass=SimdShiftAcc
 319 opLat=1
 320
 321 [system.cpu.fuPool.FUList5.opList10]
 322 type=OpDesc
 323 issueLat=1
 324 opClass=SimdSqrt
 325 opLat=1
 326
 327 [system.cpu.fuPool.FUList5.opList11]
 328 type=OpDesc
 329 issueLat=1
 330 opClass=SimdFloatAdd
 331 opLat=1
 332
 333 [system.cpu.fuPool.FUList5.opList12]
 334 type=OpDesc
 335 issueLat=1
 336 opClass=SimdFloatAlu
 337 opLat=1
 338
 339 [system.cpu.fuPool.FUList5.opList13]
 340 type=OpDesc
 341 issueLat=1
 342 opClass=SimdFloatCmp
 343 opLat=1
 344
 345 [system.cpu.fuPool.FUList5.opList14]
 346 type=OpDesc
 347 issueLat=1
 348 opClass=SimdFloatCvt
 349 opLat=1
 350
 351 [system.cpu.fuPool.FUList5.opList15]
 352 type=OpDesc
 353 issueLat=1
 354 opClass=SimdFloatDiv
 355 opLat=1
 356
 357 [system.cpu.fuPool.FUList5.opList16]
 358 type=OpDesc
 359 issueLat=1
 360 opClass=SimdFloatMisc
 361 opLat=1
 362
 363 [system.cpu.fuPool.FUList5.opList17]
 364 type=OpDesc
 365 issueLat=1
 366 opClass=SimdFloatMult
 367 opLat=1
 368
 369 [system.cpu.fuPool.FUList5.opList18]
 370 type=OpDesc
 371 issueLat=1
 372 opClass=SimdFloatMultAcc
 373 opLat=1
 374
 375 [system.cpu.fuPool.FUList5.opList19]
 376 type=OpDesc
 377 issueLat=1
 378 opClass=SimdFloatSqrt
 379 opLat=1
 380
 381 [system.cpu.fuPool.FUList6]
 382 type=FUDesc
 383 children=opList
 384 count=0
 385 opList=system.cpu.fuPool.FUList6.opList
 386
 387 [system.cpu.fuPool.FUList6.opList]
 388 type=OpDesc
 389 issueLat=1
 390 opClass=MemWrite
 391 opLat=1
 392
 393 [system.cpu.fuPool.FUList7]
 394 type=FUDesc
 395 children=opList0 opList1
 396 count=4
 397 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 398
 399 [system.cpu.fuPool.FUList7.opList0]
 400 type=OpDesc
 401 issueLat=1
 402 opClass=MemRead
 403 opLat=1
 404
 405 [system.cpu.fuPool.FUList7.opList1]
 406 type=OpDesc
 407 issueLat=1
 408 opClass=MemWrite
 409 opLat=1
 410
 411 [system.cpu.fuPool.FUList8]
 412 type=FUDesc
 413 children=opList
 414 count=1
 415 opList=system.cpu.fuPool.FUList8.opList
 416
 417 [system.cpu.fuPool.FUList8.opList]
 418 type=OpDesc
 419 issueLat=3
 420 opClass=IprAccess
 421 opLat=3
 422
 423 [system.cpu.icache]
 424 type=BaseCache
 425 addr_ranges=0:18446744073709551615
 426 assoc=2
 427 block_size=64
 428 clock=500
 429 forward_snoops=true
 430 hit_latency=2
 431 is_top_level=true
 432 max_miss_count=0
 433 mshrs=4
 434 prefetch_on_access=false
 435 prefetcher=Null
 436 response_latency=2
 437 size=131072
 438 system=system
 439 tgts_per_mshr=20
 440 two_queue=false
 441 write_buffers=8
 442 cpu_side=system.cpu.icache_port
 443 mem_side=system.cpu.toL2Bus.slave[0]
 444
 445 [system.cpu.interrupts]
 446 type=AlphaInterrupts
 447
 448 [system.cpu.isa]
 449 type=AlphaISA
 450
 451 [system.cpu.itb]
 452 type=AlphaTLB
 453 size=48
 454
 455 [system.cpu.l2cache]
 456 type=BaseCache
 457 addr_ranges=0:18446744073709551615
 458 assoc=8
 459 block_size=64
 460 clock=500
 461 forward_snoops=true
 462 hit_latency=20
 463 is_top_level=false
 464 max_miss_count=0
 465 mshrs=20
 466 prefetch_on_access=false
 467 prefetcher=Null
 468 response_latency=20
 469 size=2097152
 470 system=system
 471 tgts_per_mshr=12
 472 two_queue=false
 473 write_buffers=8
 474 cpu_side=system.cpu.toL2Bus.master[0]
 475 mem_side=system.membus.slave[1]
 476
 477 [system.cpu.toL2Bus]
 478 type=CoherentBus
 479 block_size=64
 480 clock=500
 481 header_cycles=1
 482 use_default_range=false
 483 width=32
 484 master=system.cpu.l2cache.cpu_side
 485 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 486
 487 [system.cpu.tracer]
 488 type=ExeTracer
 489
 490 [system.cpu.workload]
 491 type=LiveProcess
 492 cmd=twolf smred
 493 cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing
 494 egid=100
 495 env=
 496 errout=cerr
 497 euid=100
 498 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
 499 gid=100
 500 input=cin
 501 max_stack_size=67108864
 502 output=cout
 503 pid=100
 504 ppid=99
 505 simpoint=0
 506 system=system
 507 uid=100
 508
 509 [system.membus]
 510 type=CoherentBus
 511 block_size=64
 512 clock=1000
 513 header_cycles=1
 514 use_default_range=false
 515 width=8
 516 master=system.physmem.port
 517 slave=system.system_port system.cpu.l2cache.mem_side
 518
 519 [system.physmem]
 520 type=SimpleDRAM
 521 addr_mapping=openmap
 522 banks_per_rank=8
 523 clock=1000
 524 conf_table_reported=false
 525 in_addr_map=true
 526 lines_per_rowbuffer=64
 527 mem_sched_policy=fcfs
 528 null=false
 529 page_policy=open
 530 range=0:134217727
 531 ranks_per_channel=2
 532 read_buffer_size=32
 533 tBURST=4000
 534 tCL=14000
 535 tRCD=14000
 536 tREFI=7800000
 537 tRFC=300000
 538 tRP=14000
 539 tWTR=1000
 540 write_buffer_size=32
 541 write_thresh_perc=70
 542 zero=false
 543 port=system.membus.master[0]
 544