2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.029167 # Number of seconds simulated
4 sim_ticks 29167093500 # Number of ticks simulated
5 final_tick 29167093500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 155660 # Simulator instruction rate (inst/s)
8 host_tick_rate 53933893 # Simulator tick rate (ticks/s)
9 host_mem_usage 212576 # Number of bytes of host memory used
10 host_seconds 540.79 # Real time elapsed on the host
11 sim_insts 84179709 # Number of instructions simulated
12 system.physmem.bytes_read 332416 # Number of bytes read from this memory
13 system.physmem.bytes_inst_read 193856 # Number of instructions bytes read from this memory
14 system.physmem.bytes_written 0 # Number of bytes written to this memory
15 system.physmem.num_reads 5194 # Number of read requests responded to by this memory
16 system.physmem.num_writes 0 # Number of write requests responded to by this memory
17 system.physmem.num_other 0 # Number of other requests responded to by this memory
18 system.physmem.bw_read 11396953 # Total read bandwidth from this memory (bytes/s)
19 system.physmem.bw_inst_read 6646394 # Instruction read bandwidth from this memory (bytes/s)
20 system.physmem.bw_total 11396953 # Total bandwidth to/from this memory (bytes/s)
21 system.cpu.dtb.fetch_hits 0 # ITB hits
22 system.cpu.dtb.fetch_misses 0 # ITB misses
23 system.cpu.dtb.fetch_acv 0 # ITB acv
24 system.cpu.dtb.fetch_accesses 0 # ITB accesses
25 system.cpu.dtb.read_hits 25236325 # DTB read hits
26 system.cpu.dtb.read_misses 540509 # DTB read misses
27 system.cpu.dtb.read_acv 0 # DTB read access violations
28 system.cpu.dtb.read_accesses 25776834 # DTB read accesses
29 system.cpu.dtb.write_hits 7362909 # DTB write hits
30 system.cpu.dtb.write_misses 1032 # DTB write misses
31 system.cpu.dtb.write_acv 0 # DTB write access violations
32 system.cpu.dtb.write_accesses 7363941 # DTB write accesses
33 system.cpu.dtb.data_hits 32599234 # DTB hits
34 system.cpu.dtb.data_misses 541541 # DTB misses
35 system.cpu.dtb.data_acv 0 # DTB access violations
36 system.cpu.dtb.data_accesses 33140775 # DTB accesses
37 system.cpu.itb.fetch_hits 18604047 # ITB hits
38 system.cpu.itb.fetch_misses 85 # ITB misses
39 system.cpu.itb.fetch_acv 0 # ITB acv
40 system.cpu.itb.fetch_accesses 18604132 # ITB accesses
41 system.cpu.itb.read_hits 0 # DTB read hits
42 system.cpu.itb.read_misses 0 # DTB read misses
43 system.cpu.itb.read_acv 0 # DTB read access violations
44 system.cpu.itb.read_accesses 0 # DTB read accesses
45 system.cpu.itb.write_hits 0 # DTB write hits
46 system.cpu.itb.write_misses 0 # DTB write misses
47 system.cpu.itb.write_acv 0 # DTB write access violations
48 system.cpu.itb.write_accesses 0 # DTB write accesses
49 system.cpu.itb.data_hits 0 # DTB hits
50 system.cpu.itb.data_misses 0 # DTB misses
51 system.cpu.itb.data_acv 0 # DTB access violations
52 system.cpu.itb.data_accesses 0 # DTB accesses
53 system.cpu.workload.num_syscalls 389 # Number of system calls
54 system.cpu.numCycles 58334188 # number of cpu cycles simulated
55 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
56 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
57 system.cpu.BPredUnit.lookups 18443606 # Number of BP lookups
58 system.cpu.BPredUnit.condPredicted 13550904 # Number of conditional branches predicted
59 system.cpu.BPredUnit.condIncorrect 1909309 # Number of conditional branches incorrect
60 system.cpu.BPredUnit.BTBLookups 15151906 # Number of BTB lookups
61 system.cpu.BPredUnit.BTBHits 11744171 # Number of BTB hits
62 system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
63 system.cpu.BPredUnit.usedRAS 1797123 # Number of times the RAS was used to get a target.
64 system.cpu.BPredUnit.RASInCorrect 2508 # Number of incorrect RAS predictions.
65 system.cpu.fetch.icacheStallCycles 19753130 # Number of cycles fetch is stalled on an Icache miss
66 system.cpu.fetch.Insts 155901269 # Number of instructions fetch has processed
67 system.cpu.fetch.Branches 18443606 # Number of branches that fetch encountered
68 system.cpu.fetch.predictedBranches 13541294 # Number of branches that fetch has predicted taken
69 system.cpu.fetch.Cycles 28873870 # Number of cycles fetch has run and was not squashing or blocked
70 system.cpu.fetch.SquashCycles 8029527 # Number of cycles fetch has spent squashing
71 system.cpu.fetch.BlockedCycles 3519156 # Number of cycles fetch has spent blocked
72 system.cpu.fetch.MiscStallCycles 49 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
73 system.cpu.fetch.PendingTrapStallCycles 1819 # Number of stall cycles due to pending traps
74 system.cpu.fetch.CacheLines 18604047 # Number of cache lines fetched
75 system.cpu.fetch.IcacheSquashes 633220 # Number of outstanding Icache misses that were squashed
76 system.cpu.fetch.rateDist::samples 58241050 # Number of instructions fetched each cycle (Total)
77 system.cpu.fetch.rateDist::mean 2.676828 # Number of instructions fetched each cycle (Total)
78 system.cpu.fetch.rateDist::stdev 3.252315 # Number of instructions fetched each cycle (Total)
79 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
80 system.cpu.fetch.rateDist::0 29367180 50.42% 50.42% # Number of instructions fetched each cycle (Total)
81 system.cpu.fetch.rateDist::1 2937608 5.04% 55.47% # Number of instructions fetched each cycle (Total)
82 system.cpu.fetch.rateDist::2 2015194 3.46% 58.93% # Number of instructions fetched each cycle (Total)
83 system.cpu.fetch.rateDist::3 3338566 5.73% 64.66% # Number of instructions fetched each cycle (Total)
84 system.cpu.fetch.rateDist::4 4094138 7.03% 71.69% # Number of instructions fetched each cycle (Total)
85 system.cpu.fetch.rateDist::5 1423310 2.44% 74.13% # Number of instructions fetched each cycle (Total)
86 system.cpu.fetch.rateDist::6 1755062 3.01% 77.15% # Number of instructions fetched each cycle (Total)
87 system.cpu.fetch.rateDist::7 1585835 2.72% 79.87% # Number of instructions fetched each cycle (Total)
88 system.cpu.fetch.rateDist::8 11724157 20.13% 100.00% # Number of instructions fetched each cycle (Total)
89 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
90 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
91 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
92 system.cpu.fetch.rateDist::total 58241050 # Number of instructions fetched each cycle (Total)
93 system.cpu.fetch.branchRate 0.316171 # Number of branch fetches per cycle
94 system.cpu.fetch.rate 2.672554 # Number of inst fetches per cycle
95 system.cpu.decode.IdleCycles 21649179 # Number of cycles decode is idle
96 system.cpu.decode.BlockedCycles 2708949 # Number of cycles decode is blocked
97 system.cpu.decode.RunCycles 27144653 # Number of cycles decode is running
98 system.cpu.decode.UnblockCycles 658698 # Number of cycles decode is unblocking
99 system.cpu.decode.SquashCycles 6079571 # Number of cycles decode is squashing
100 system.cpu.decode.BranchResolved 2969190 # Number of times decode resolved a branch
101 system.cpu.decode.BranchMispred 13806 # Number of times decode detected a branch misprediction
102 system.cpu.decode.DecodedInsts 150046107 # Number of instructions handled by decode
103 system.cpu.decode.SquashedInsts 43597 # Number of squashed instructions handled by decode
104 system.cpu.rename.SquashCycles 6079571 # Number of cycles rename is squashing
105 system.cpu.rename.IdleCycles 23241789 # Number of cycles rename is idle
106 system.cpu.rename.BlockCycles 566661 # Number of cycles rename is blocking
107 system.cpu.rename.serializeStallCycles 6095 # count of cycles rename stalled for serializing inst
108 system.cpu.rename.RunCycles 26202396 # Number of cycles rename is running
109 system.cpu.rename.UnblockCycles 2144538 # Number of cycles rename is unblocking
110 system.cpu.rename.RenamedInsts 144061667 # Number of instructions processed by rename
111 system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full
112 system.cpu.rename.IQFullEvents 244284 # Number of times rename has blocked due to IQ full
113 system.cpu.rename.LSQFullEvents 1605069 # Number of times rename has blocked due to LSQ full
114 system.cpu.rename.RenamedOperands 105522995 # Number of destination operands rename has renamed
115 system.cpu.rename.RenameLookups 186327738 # Number of register rename lookups that rename has made
116 system.cpu.rename.int_rename_lookups 175726328 # Number of integer rename lookups
117 system.cpu.rename.fp_rename_lookups 10601410 # Number of floating rename lookups
118 system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed
119 system.cpu.rename.UndoneMaps 37095634 # Number of HB maps that are undone due to squashing
120 system.cpu.rename.serializingInsts 535 # count of serializing insts renamed
121 system.cpu.rename.tempSerializingInsts 531 # count of temporary serializing insts renamed
122 system.cpu.rename.skidInsts 6071657 # count of insts added to the skid buffer
123 system.cpu.memDep0.insertedLoads 29750182 # Number of loads inserted to the mem dependence unit.
124 system.cpu.memDep0.insertedStores 9383371 # Number of stores inserted to the mem dependence unit.
125 system.cpu.memDep0.conflictingLoads 2457988 # Number of conflicting loads.
126 system.cpu.memDep0.conflictingStores 836885 # Number of conflicting stores.
127 system.cpu.iq.iqInstsAdded 120824169 # Number of instructions added to the IQ (excludes non-spec)
128 system.cpu.iq.iqNonSpecInstsAdded 510 # Number of non-speculative instructions added to the IQ
129 system.cpu.iq.iqInstsIssued 104934850 # Number of instructions issued
130 system.cpu.iq.iqSquashedInstsIssued 288533 # Number of squashed instructions issued
131 system.cpu.iq.iqSquashedInstsExamined 35688110 # Number of squashed instructions iterated over during squash; mainly for profiling
132 system.cpu.iq.iqSquashedOperandsExamined 27652526 # Number of squashed operands that are examined and possibly removed from graph
133 system.cpu.iq.iqSquashedNonSpecRemoved 121 # Number of squashed non-spec instructions that were removed
134 system.cpu.iq.issued_per_cycle::samples 58241050 # Number of insts issued each cycle
135 system.cpu.iq.issued_per_cycle::mean 1.801733 # Number of insts issued each cycle
136 system.cpu.iq.issued_per_cycle::stdev 1.850509 # Number of insts issued each cycle
137 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
138 system.cpu.iq.issued_per_cycle::0 19806248 34.01% 34.01% # Number of insts issued each cycle
139 system.cpu.iq.issued_per_cycle::1 11039636 18.96% 52.96% # Number of insts issued each cycle
140 system.cpu.iq.issued_per_cycle::2 9348946 16.05% 69.01% # Number of insts issued each cycle
141 system.cpu.iq.issued_per_cycle::3 6752104 11.59% 80.61% # Number of insts issued each cycle
142 system.cpu.iq.issued_per_cycle::4 5521673 9.48% 90.09% # Number of insts issued each cycle
143 system.cpu.iq.issued_per_cycle::5 2974014 5.11% 95.20% # Number of insts issued each cycle
144 system.cpu.iq.issued_per_cycle::6 1775531 3.05% 98.24% # Number of insts issued each cycle
145 system.cpu.iq.issued_per_cycle::7 852122 1.46% 99.71% # Number of insts issued each cycle
146 system.cpu.iq.issued_per_cycle::8 170776 0.29% 100.00% # Number of insts issued each cycle
147 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
148 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
149 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
150 system.cpu.iq.issued_per_cycle::total 58241050 # Number of insts issued each cycle
151 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
152 system.cpu.iq.fu_full::IntAlu 161609 9.97% 9.97% # attempts to use FU when none available
153 system.cpu.iq.fu_full::IntMult 0 0.00% 9.97% # attempts to use FU when none available
154 system.cpu.iq.fu_full::IntDiv 0 0.00% 9.97% # attempts to use FU when none available
155 system.cpu.iq.fu_full::FloatAdd 218 0.01% 9.98% # attempts to use FU when none available
156 system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.98% # attempts to use FU when none available
157 system.cpu.iq.fu_full::FloatCvt 6469 0.40% 10.38% # attempts to use FU when none available
158 system.cpu.iq.fu_full::FloatMult 2295 0.14% 10.52% # attempts to use FU when none available
159 system.cpu.iq.fu_full::FloatDiv 845619 52.17% 62.69% # attempts to use FU when none available
160 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 62.69% # attempts to use FU when none available
161 system.cpu.iq.fu_full::SimdAdd 0 0.00% 62.69% # attempts to use FU when none available
162 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 62.69% # attempts to use FU when none available
163 system.cpu.iq.fu_full::SimdAlu 0 0.00% 62.69% # attempts to use FU when none available
164 system.cpu.iq.fu_full::SimdCmp 0 0.00% 62.69% # attempts to use FU when none available
165 system.cpu.iq.fu_full::SimdCvt 0 0.00% 62.69% # attempts to use FU when none available
166 system.cpu.iq.fu_full::SimdMisc 0 0.00% 62.69% # attempts to use FU when none available
167 system.cpu.iq.fu_full::SimdMult 0 0.00% 62.69% # attempts to use FU when none available
168 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 62.69% # attempts to use FU when none available
169 system.cpu.iq.fu_full::SimdShift 0 0.00% 62.69% # attempts to use FU when none available
170 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 62.69% # attempts to use FU when none available
171 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 62.69% # attempts to use FU when none available
172 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 62.69% # attempts to use FU when none available
173 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 62.69% # attempts to use FU when none available
174 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 62.69% # attempts to use FU when none available
175 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 62.69% # attempts to use FU when none available
176 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 62.69% # attempts to use FU when none available
177 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 62.69% # attempts to use FU when none available
178 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 62.69% # attempts to use FU when none available
179 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 62.69% # attempts to use FU when none available
180 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 62.69% # attempts to use FU when none available
181 system.cpu.iq.fu_full::MemRead 527151 32.52% 95.21% # attempts to use FU when none available
182 system.cpu.iq.fu_full::MemWrite 77634 4.79% 100.00% # attempts to use FU when none available
183 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
184 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
185 system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued
186 system.cpu.iq.FU_type_0::IntAlu 63561145 60.57% 60.57% # Type of FU issued
187 system.cpu.iq.FU_type_0::IntMult 485535 0.46% 61.03% # Type of FU issued
188 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.03% # Type of FU issued
189 system.cpu.iq.FU_type_0::FloatAdd 2794061 2.66% 63.70% # Type of FU issued
190 system.cpu.iq.FU_type_0::FloatCmp 115045 0.11% 63.81% # Type of FU issued
191 system.cpu.iq.FU_type_0::FloatCvt 2411045 2.30% 66.10% # Type of FU issued
192 system.cpu.iq.FU_type_0::FloatMult 308682 0.29% 66.40% # Type of FU issued
193 system.cpu.iq.FU_type_0::FloatDiv 763571 0.73% 67.13% # Type of FU issued
194 system.cpu.iq.FU_type_0::FloatSqrt 318 0.00% 67.13% # Type of FU issued
195 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.13% # Type of FU issued
196 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.13% # Type of FU issued
197 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.13% # Type of FU issued
198 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.13% # Type of FU issued
199 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.13% # Type of FU issued
200 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.13% # Type of FU issued
201 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.13% # Type of FU issued
202 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.13% # Type of FU issued
203 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.13% # Type of FU issued
204 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.13% # Type of FU issued
205 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.13% # Type of FU issued
206 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.13% # Type of FU issued
207 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.13% # Type of FU issued
208 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.13% # Type of FU issued
209 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.13% # Type of FU issued
210 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.13% # Type of FU issued
211 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.13% # Type of FU issued
212 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.13% # Type of FU issued
213 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.13% # Type of FU issued
214 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.13% # Type of FU issued
215 system.cpu.iq.FU_type_0::MemRead 27006510 25.74% 92.86% # Type of FU issued
216 system.cpu.iq.FU_type_0::MemWrite 7488931 7.14% 100.00% # Type of FU issued
217 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
218 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
219 system.cpu.iq.FU_type_0::total 104934850 # Type of FU issued
220 system.cpu.iq.rate 1.798857 # Inst issue rate
221 system.cpu.iq.fu_busy_cnt 1620995 # FU busy when requested
222 system.cpu.iq.fu_busy_rate 0.015448 # FU busy rate (busy events/executed inst)
223 system.cpu.iq.int_inst_queue_reads 254843963 # Number of integer instruction queue reads
224 system.cpu.iq.int_inst_queue_writes 146750024 # Number of integer instruction queue writes
225 system.cpu.iq.int_inst_queue_wakeup_accesses 92740043 # Number of integer instruction queue wakeup accesses
226 system.cpu.iq.fp_inst_queue_reads 15176315 # Number of floating instruction queue reads
227 system.cpu.iq.fp_inst_queue_writes 9791044 # Number of floating instruction queue writes
228 system.cpu.iq.fp_inst_queue_wakeup_accesses 7062550 # Number of floating instruction queue wakeup accesses
229 system.cpu.iq.int_alu_accesses 98540004 # Number of integer alu accesses
230 system.cpu.iq.fp_alu_accesses 8015834 # Number of floating point alu accesses
231 system.cpu.iew.lsq.thread0.forwLoads 1319105 # Number of loads that had data forwarded from stores
232 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
233 system.cpu.iew.lsq.thread0.squashedLoads 9753984 # Number of loads squashed
234 system.cpu.iew.lsq.thread0.ignoredResponses 15279 # Number of memory responses ignored because the instruction is squashed
235 system.cpu.iew.lsq.thread0.memOrderViolation 28494 # Number of memory ordering violations
236 system.cpu.iew.lsq.thread0.squashedStores 2882268 # Number of stores squashed
237 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
238 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
239 system.cpu.iew.lsq.thread0.rescheduledLoads 10177 # Number of loads that were rescheduled
240 system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked
241 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
242 system.cpu.iew.iewSquashCycles 6079571 # Number of cycles IEW is squashing
243 system.cpu.iew.iewBlockCycles 81043 # Number of cycles IEW is blocking
244 system.cpu.iew.iewUnblockCycles 15363 # Number of cycles IEW is unblocking
245 system.cpu.iew.iewDispatchedInsts 132624218 # Number of instructions dispatched to IQ
246 system.cpu.iew.iewDispSquashedInsts 876009 # Number of squashed instructions skipped by dispatch
247 system.cpu.iew.iewDispLoadInsts 29750182 # Number of dispatched load instructions
248 system.cpu.iew.iewDispStoreInsts 9383371 # Number of dispatched store instructions
249 system.cpu.iew.iewDispNonSpecInsts 510 # Number of dispatched non-speculative instructions
250 system.cpu.iew.iewIQFullEvents 184 # Number of times the IQ has become full, causing a stall
251 system.cpu.iew.iewLSQFullEvents 33 # Number of times the LSQ has become full, causing a stall
252 system.cpu.iew.memOrderViolationEvents 28494 # Number of memory order violations
253 system.cpu.iew.predictedTakenIncorrect 1787084 # Number of branches that were predicted taken incorrectly
254 system.cpu.iew.predictedNotTakenIncorrect 342134 # Number of branches that were predicted not taken incorrectly
255 system.cpu.iew.branchMispredicts 2129218 # Number of branch mispredicts detected at execute
256 system.cpu.iew.iewExecutedInsts 102333218 # Number of executed instructions
257 system.cpu.iew.iewExecLoadInsts 25777384 # Number of load instructions executed
258 system.cpu.iew.iewExecSquashedInsts 2601632 # Number of squashed instructions skipped in execute
259 system.cpu.iew.exec_swp 0 # number of swp insts executed
260 system.cpu.iew.exec_nop 11799539 # number of nop insts executed
261 system.cpu.iew.exec_refs 33141424 # number of memory reference insts executed
262 system.cpu.iew.exec_branches 12916232 # Number of branches executed
263 system.cpu.iew.exec_stores 7364040 # Number of stores executed
264 system.cpu.iew.exec_rate 1.754258 # Inst execution rate
265 system.cpu.iew.wb_sent 101006568 # cumulative count of insts sent to commit
266 system.cpu.iew.wb_count 99802593 # cumulative count of insts written-back
267 system.cpu.iew.wb_producers 67789343 # num instructions producing a value
268 system.cpu.iew.wb_consumers 93484829 # num instructions consuming a value
269 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
270 system.cpu.iew.wb_rate 1.710877 # insts written-back per cycle
271 system.cpu.iew.wb_fanout 0.725137 # average fanout of values written-back
272 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
273 system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions
274 system.cpu.commit.commitSquashedInsts 40723267 # The number of squashed insts skipped by commit
275 system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
276 system.cpu.commit.branchMispredicts 1895854 # The number of times a branch was mispredicted
277 system.cpu.commit.committed_per_cycle::samples 52161479 # Number of insts commited each cycle
278 system.cpu.commit.committed_per_cycle::mean 1.761895 # Number of insts commited each cycle
279 system.cpu.commit.committed_per_cycle::stdev 2.510937 # Number of insts commited each cycle
280 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
281 system.cpu.commit.committed_per_cycle::0 23655247 45.35% 45.35% # Number of insts commited each cycle
282 system.cpu.commit.committed_per_cycle::1 11195713 21.46% 66.81% # Number of insts commited each cycle
283 system.cpu.commit.committed_per_cycle::2 5070133 9.72% 76.53% # Number of insts commited each cycle
284 system.cpu.commit.committed_per_cycle::3 2810925 5.39% 81.92% # Number of insts commited each cycle
285 system.cpu.commit.committed_per_cycle::4 1675607 3.21% 85.13% # Number of insts commited each cycle
286 system.cpu.commit.committed_per_cycle::5 1392452 2.67% 87.80% # Number of insts commited each cycle
287 system.cpu.commit.committed_per_cycle::6 795157 1.52% 89.33% # Number of insts commited each cycle
288 system.cpu.commit.committed_per_cycle::7 831289 1.59% 90.92% # Number of insts commited each cycle
289 system.cpu.commit.committed_per_cycle::8 4734956 9.08% 100.00% # Number of insts commited each cycle
290 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
291 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
292 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
293 system.cpu.commit.committed_per_cycle::total 52161479 # Number of insts commited each cycle
294 system.cpu.commit.count 91903055 # Number of instructions committed
295 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
296 system.cpu.commit.refs 26497301 # Number of memory references committed
297 system.cpu.commit.loads 19996198 # Number of loads committed
298 system.cpu.commit.membars 0 # Number of memory barriers committed
299 system.cpu.commit.branches 10240685 # Number of branches committed
300 system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions.
301 system.cpu.commit.int_insts 79581076 # Number of committed integer instructions.
302 system.cpu.commit.function_calls 1029620 # Number of function calls committed.
303 system.cpu.commit.bw_lim_events 4734956 # number cycles where commit BW limit reached
304 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
305 system.cpu.rob.rob_reads 180051805 # The number of ROB reads
306 system.cpu.rob.rob_writes 271380444 # The number of ROB writes
307 system.cpu.timesIdled 2277 # Number of times that the entire CPU went into an idle state and unscheduled itself
308 system.cpu.idleCycles 93138 # Total number of cycles that the CPU has spent unscheduled due to idling
309 system.cpu.committedInsts 84179709 # Number of Instructions Simulated
310 system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated
311 system.cpu.cpi 0.692972 # CPI: Cycles Per Instruction
312 system.cpu.cpi_total 0.692972 # CPI: Total CPI of All Threads
313 system.cpu.ipc 1.443060 # IPC: Instructions Per Cycle
314 system.cpu.ipc_total 1.443060 # IPC: Total IPC of All Threads
315 system.cpu.int_regfile_reads 138495671 # number of integer regfile reads
316 system.cpu.int_regfile_writes 75435014 # number of integer regfile writes
317 system.cpu.fp_regfile_reads 6177236 # number of floating regfile reads
318 system.cpu.fp_regfile_writes 6044349 # number of floating regfile writes
319 system.cpu.misc_regfile_reads 715554 # number of misc regfile reads
320 system.cpu.misc_regfile_writes 1 # number of misc regfile writes
321 system.cpu.icache.replacements 8695 # number of replacements
322 system.cpu.icache.tagsinuse 1593.002324 # Cycle average of tags in use
323 system.cpu.icache.total_refs 18592194 # Total number of references to valid blocks.
324 system.cpu.icache.sampled_refs 10628 # Sample count of references to valid blocks.
325 system.cpu.icache.avg_refs 1749.359616 # Average number of references to valid blocks.
326 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
327 system.cpu.icache.occ_blocks::0 1593.002324 # Average occupied blocks per context
328 system.cpu.icache.occ_percent::0 0.777833 # Average percentage of cache occupancy
329 system.cpu.icache.ReadReq_hits 18592194 # number of ReadReq hits
330 system.cpu.icache.demand_hits 18592194 # number of demand (read+write) hits
331 system.cpu.icache.overall_hits 18592194 # number of overall hits
332 system.cpu.icache.ReadReq_misses 11853 # number of ReadReq misses
333 system.cpu.icache.demand_misses 11853 # number of demand (read+write) misses
334 system.cpu.icache.overall_misses 11853 # number of overall misses
335 system.cpu.icache.ReadReq_miss_latency 188036500 # number of ReadReq miss cycles
336 system.cpu.icache.demand_miss_latency 188036500 # number of demand (read+write) miss cycles
337 system.cpu.icache.overall_miss_latency 188036500 # number of overall miss cycles
338 system.cpu.icache.ReadReq_accesses 18604047 # number of ReadReq accesses(hits+misses)
339 system.cpu.icache.demand_accesses 18604047 # number of demand (read+write) accesses
340 system.cpu.icache.overall_accesses 18604047 # number of overall (read+write) accesses
341 system.cpu.icache.ReadReq_miss_rate 0.000637 # miss rate for ReadReq accesses
342 system.cpu.icache.demand_miss_rate 0.000637 # miss rate for demand accesses
343 system.cpu.icache.overall_miss_rate 0.000637 # miss rate for overall accesses
344 system.cpu.icache.ReadReq_avg_miss_latency 15864.042858 # average ReadReq miss latency
345 system.cpu.icache.demand_avg_miss_latency 15864.042858 # average overall miss latency
346 system.cpu.icache.overall_avg_miss_latency 15864.042858 # average overall miss latency
347 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
348 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
349 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
350 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
351 system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
352 system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
353 system.cpu.icache.fast_writes 0 # number of fast writes performed
354 system.cpu.icache.cache_copies 0 # number of cache copies performed
355 system.cpu.icache.writebacks 0 # number of writebacks
356 system.cpu.icache.ReadReq_mshr_hits 1225 # number of ReadReq MSHR hits
357 system.cpu.icache.demand_mshr_hits 1225 # number of demand (read+write) MSHR hits
358 system.cpu.icache.overall_mshr_hits 1225 # number of overall MSHR hits
359 system.cpu.icache.ReadReq_mshr_misses 10628 # number of ReadReq MSHR misses
360 system.cpu.icache.demand_mshr_misses 10628 # number of demand (read+write) MSHR misses
361 system.cpu.icache.overall_mshr_misses 10628 # number of overall MSHR misses
362 system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
363 system.cpu.icache.ReadReq_mshr_miss_latency 124769000 # number of ReadReq MSHR miss cycles
364 system.cpu.icache.demand_mshr_miss_latency 124769000 # number of demand (read+write) MSHR miss cycles
365 system.cpu.icache.overall_mshr_miss_latency 124769000 # number of overall MSHR miss cycles
366 system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
367 system.cpu.icache.ReadReq_mshr_miss_rate 0.000571 # mshr miss rate for ReadReq accesses
368 system.cpu.icache.demand_mshr_miss_rate 0.000571 # mshr miss rate for demand accesses
369 system.cpu.icache.overall_mshr_miss_rate 0.000571 # mshr miss rate for overall accesses
370 system.cpu.icache.ReadReq_avg_mshr_miss_latency 11739.649981 # average ReadReq mshr miss latency
371 system.cpu.icache.demand_avg_mshr_miss_latency 11739.649981 # average overall mshr miss latency
372 system.cpu.icache.overall_avg_mshr_miss_latency 11739.649981 # average overall mshr miss latency
373 system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
374 system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
375 system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
376 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
377 system.cpu.dcache.replacements 159 # number of replacements
378 system.cpu.dcache.tagsinuse 1462.507461 # Cycle average of tags in use
379 system.cpu.dcache.total_refs 30399158 # Total number of references to valid blocks.
380 system.cpu.dcache.sampled_refs 2246 # Sample count of references to valid blocks.
381 system.cpu.dcache.avg_refs 13534.798753 # Average number of references to valid blocks.
382 system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
383 system.cpu.dcache.occ_blocks::0 1462.507461 # Average occupied blocks per context
384 system.cpu.dcache.occ_percent::0 0.357057 # Average percentage of cache occupancy
385 system.cpu.dcache.ReadReq_hits 23906051 # number of ReadReq hits
386 system.cpu.dcache.WriteReq_hits 6493055 # number of WriteReq hits
387 system.cpu.dcache.LoadLockedReq_hits 52 # number of LoadLockedReq hits
388 system.cpu.dcache.demand_hits 30399106 # number of demand (read+write) hits
389 system.cpu.dcache.overall_hits 30399106 # number of overall hits
390 system.cpu.dcache.ReadReq_misses 938 # number of ReadReq misses
391 system.cpu.dcache.WriteReq_misses 8048 # number of WriteReq misses
392 system.cpu.dcache.LoadLockedReq_misses 1 # number of LoadLockedReq misses
393 system.cpu.dcache.demand_misses 8986 # number of demand (read+write) misses
394 system.cpu.dcache.overall_misses 8986 # number of overall misses
395 system.cpu.dcache.ReadReq_miss_latency 28163500 # number of ReadReq miss cycles
396 system.cpu.dcache.WriteReq_miss_latency 289889000 # number of WriteReq miss cycles
397 system.cpu.dcache.LoadLockedReq_miss_latency 38000 # number of LoadLockedReq miss cycles
398 system.cpu.dcache.demand_miss_latency 318052500 # number of demand (read+write) miss cycles
399 system.cpu.dcache.overall_miss_latency 318052500 # number of overall miss cycles
400 system.cpu.dcache.ReadReq_accesses 23906989 # number of ReadReq accesses(hits+misses)
401 system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
402 system.cpu.dcache.LoadLockedReq_accesses 53 # number of LoadLockedReq accesses(hits+misses)
403 system.cpu.dcache.demand_accesses 30408092 # number of demand (read+write) accesses
404 system.cpu.dcache.overall_accesses 30408092 # number of overall (read+write) accesses
405 system.cpu.dcache.ReadReq_miss_rate 0.000039 # miss rate for ReadReq accesses
406 system.cpu.dcache.WriteReq_miss_rate 0.001238 # miss rate for WriteReq accesses
407 system.cpu.dcache.LoadLockedReq_miss_rate 0.018868 # miss rate for LoadLockedReq accesses
408 system.cpu.dcache.demand_miss_rate 0.000296 # miss rate for demand accesses
409 system.cpu.dcache.overall_miss_rate 0.000296 # miss rate for overall accesses
410 system.cpu.dcache.ReadReq_avg_miss_latency 30025.053305 # average ReadReq miss latency
411 system.cpu.dcache.WriteReq_avg_miss_latency 36020.004970 # average WriteReq miss latency
412 system.cpu.dcache.LoadLockedReq_avg_miss_latency 38000 # average LoadLockedReq miss latency
413 system.cpu.dcache.demand_avg_miss_latency 35394.224349 # average overall miss latency
414 system.cpu.dcache.overall_avg_miss_latency 35394.224349 # average overall miss latency
415 system.cpu.dcache.blocked_cycles::no_mshrs 2500 # number of cycles access was blocked
416 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
417 system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
418 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
419 system.cpu.dcache.avg_blocked_cycles::no_mshrs 2500 # average number of cycles each access was blocked
420 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
421 system.cpu.dcache.fast_writes 0 # number of fast writes performed
422 system.cpu.dcache.cache_copies 0 # number of cache copies performed
423 system.cpu.dcache.writebacks 108 # number of writebacks
424 system.cpu.dcache.ReadReq_mshr_hits 424 # number of ReadReq MSHR hits
425 system.cpu.dcache.WriteReq_mshr_hits 6317 # number of WriteReq MSHR hits
426 system.cpu.dcache.demand_mshr_hits 6741 # number of demand (read+write) MSHR hits
427 system.cpu.dcache.overall_mshr_hits 6741 # number of overall MSHR hits
428 system.cpu.dcache.ReadReq_mshr_misses 514 # number of ReadReq MSHR misses
429 system.cpu.dcache.WriteReq_mshr_misses 1731 # number of WriteReq MSHR misses
430 system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses
431 system.cpu.dcache.demand_mshr_misses 2245 # number of demand (read+write) MSHR misses
432 system.cpu.dcache.overall_mshr_misses 2245 # number of overall MSHR misses
433 system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
434 system.cpu.dcache.ReadReq_mshr_miss_latency 16469500 # number of ReadReq MSHR miss cycles
435 system.cpu.dcache.WriteReq_mshr_miss_latency 61655000 # number of WriteReq MSHR miss cycles
436 system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35000 # number of LoadLockedReq MSHR miss cycles
437 system.cpu.dcache.demand_mshr_miss_latency 78124500 # number of demand (read+write) MSHR miss cycles
438 system.cpu.dcache.overall_mshr_miss_latency 78124500 # number of overall MSHR miss cycles
439 system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
440 system.cpu.dcache.ReadReq_mshr_miss_rate 0.000021 # mshr miss rate for ReadReq accesses
441 system.cpu.dcache.WriteReq_mshr_miss_rate 0.000266 # mshr miss rate for WriteReq accesses
442 system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.018868 # mshr miss rate for LoadLockedReq accesses
443 system.cpu.dcache.demand_mshr_miss_rate 0.000074 # mshr miss rate for demand accesses
444 system.cpu.dcache.overall_mshr_miss_rate 0.000074 # mshr miss rate for overall accesses
445 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32041.828794 # average ReadReq mshr miss latency
446 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35618.139804 # average WriteReq mshr miss latency
447 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35000 # average LoadLockedReq mshr miss latency
448 system.cpu.dcache.demand_avg_mshr_miss_latency 34799.331849 # average overall mshr miss latency
449 system.cpu.dcache.overall_avg_mshr_miss_latency 34799.331849 # average overall mshr miss latency
450 system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
451 system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
452 system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
453 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
454 system.cpu.l2cache.replacements 0 # number of replacements
455 system.cpu.l2cache.tagsinuse 2400.275766 # Cycle average of tags in use
456 system.cpu.l2cache.total_refs 7666 # Total number of references to valid blocks.
457 system.cpu.l2cache.sampled_refs 3556 # Sample count of references to valid blocks.
458 system.cpu.l2cache.avg_refs 2.155793 # Average number of references to valid blocks.
459 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
460 system.cpu.l2cache.occ_blocks::0 2382.642182 # Average occupied blocks per context
461 system.cpu.l2cache.occ_blocks::1 17.633584 # Average occupied blocks per context
462 system.cpu.l2cache.occ_percent::0 0.072712 # Average percentage of cache occupancy
463 system.cpu.l2cache.occ_percent::1 0.000538 # Average percentage of cache occupancy
464 system.cpu.l2cache.ReadReq_hits 7655 # number of ReadReq hits
465 system.cpu.l2cache.Writeback_hits 108 # number of Writeback hits
466 system.cpu.l2cache.ReadExReq_hits 25 # number of ReadExReq hits
467 system.cpu.l2cache.demand_hits 7680 # number of demand (read+write) hits
468 system.cpu.l2cache.overall_hits 7680 # number of overall hits
469 system.cpu.l2cache.ReadReq_misses 3488 # number of ReadReq misses
470 system.cpu.l2cache.ReadExReq_misses 1706 # number of ReadExReq misses
471 system.cpu.l2cache.demand_misses 5194 # number of demand (read+write) misses
472 system.cpu.l2cache.overall_misses 5194 # number of overall misses
473 system.cpu.l2cache.ReadReq_miss_latency 119792500 # number of ReadReq miss cycles
474 system.cpu.l2cache.ReadExReq_miss_latency 59244000 # number of ReadExReq miss cycles
475 system.cpu.l2cache.demand_miss_latency 179036500 # number of demand (read+write) miss cycles
476 system.cpu.l2cache.overall_miss_latency 179036500 # number of overall miss cycles
477 system.cpu.l2cache.ReadReq_accesses 11143 # number of ReadReq accesses(hits+misses)
478 system.cpu.l2cache.Writeback_accesses 108 # number of Writeback accesses(hits+misses)
479 system.cpu.l2cache.ReadExReq_accesses 1731 # number of ReadExReq accesses(hits+misses)
480 system.cpu.l2cache.demand_accesses 12874 # number of demand (read+write) accesses
481 system.cpu.l2cache.overall_accesses 12874 # number of overall (read+write) accesses
482 system.cpu.l2cache.ReadReq_miss_rate 0.313022 # miss rate for ReadReq accesses
483 system.cpu.l2cache.ReadExReq_miss_rate 0.985557 # miss rate for ReadExReq accesses
484 system.cpu.l2cache.demand_miss_rate 0.403449 # miss rate for demand accesses
485 system.cpu.l2cache.overall_miss_rate 0.403449 # miss rate for overall accesses
486 system.cpu.l2cache.ReadReq_avg_miss_latency 34344.180046 # average ReadReq miss latency
487 system.cpu.l2cache.ReadExReq_avg_miss_latency 34726.846424 # average ReadExReq miss latency
488 system.cpu.l2cache.demand_avg_miss_latency 34469.869080 # average overall miss latency
489 system.cpu.l2cache.overall_avg_miss_latency 34469.869080 # average overall miss latency
490 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
491 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
492 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
493 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
494 system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
495 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
496 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
497 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
498 system.cpu.l2cache.writebacks 0 # number of writebacks
499 system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
500 system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
501 system.cpu.l2cache.ReadReq_mshr_misses 3488 # number of ReadReq MSHR misses
502 system.cpu.l2cache.ReadExReq_mshr_misses 1706 # number of ReadExReq MSHR misses
503 system.cpu.l2cache.demand_mshr_misses 5194 # number of demand (read+write) MSHR misses
504 system.cpu.l2cache.overall_mshr_misses 5194 # number of overall MSHR misses
505 system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
506 system.cpu.l2cache.ReadReq_mshr_miss_latency 108490000 # number of ReadReq MSHR miss cycles
507 system.cpu.l2cache.ReadExReq_mshr_miss_latency 53828000 # number of ReadExReq MSHR miss cycles
508 system.cpu.l2cache.demand_mshr_miss_latency 162318000 # number of demand (read+write) MSHR miss cycles
509 system.cpu.l2cache.overall_mshr_miss_latency 162318000 # number of overall MSHR miss cycles
510 system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
511 system.cpu.l2cache.ReadReq_mshr_miss_rate 0.313022 # mshr miss rate for ReadReq accesses
512 system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985557 # mshr miss rate for ReadExReq accesses
513 system.cpu.l2cache.demand_mshr_miss_rate 0.403449 # mshr miss rate for demand accesses
514 system.cpu.l2cache.overall_mshr_miss_rate 0.403449 # mshr miss rate for overall accesses
515 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31103.784404 # average ReadReq mshr miss latency
516 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31552.168816 # average ReadExReq mshr miss latency
517 system.cpu.l2cache.demand_avg_mshr_miss_latency 31251.058914 # average overall mshr miss latency
518 system.cpu.l2cache.overall_avg_mshr_miss_latency 31251.058914 # average overall mshr miss latency
519 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
520 system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
521 system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
522 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
524 ---------- End Simulation Statistics ----------
projects / gem5.git / blob