2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.118729 # Number of seconds simulated
4 sim_ticks 118729316000 # Number of ticks simulated
5 final_tick 118729316000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 852211 # Simulator instruction rate (inst/s)
8 host_op_rate 852211 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 1100968725 # Simulator tick rate (ticks/s)
10 host_mem_usage 228676 # Number of bytes of host memory used
11 host_seconds 107.84 # Real time elapsed on the host
12 sim_insts 91903056 # Number of instructions simulated
13 sim_ops 91903056 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 167744 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 137216 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 304960 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 167744 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 167744 # Number of instructions bytes read from this memory
19 system.physmem.num_reads::cpu.inst 2621 # Number of read requests responded to by this memory
20 system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory
21 system.physmem.num_reads::total 4765 # Number of read requests responded to by this memory
22 system.physmem.bw_read::cpu.inst 1412827 # Total read bandwidth from this memory (bytes/s)
23 system.physmem.bw_read::cpu.data 1155704 # Total read bandwidth from this memory (bytes/s)
24 system.physmem.bw_read::total 2568532 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_inst_read::cpu.inst 1412827 # Instruction read bandwidth from this memory (bytes/s)
26 system.physmem.bw_inst_read::total 1412827 # Instruction read bandwidth from this memory (bytes/s)
27 system.physmem.bw_total::cpu.inst 1412827 # Total bandwidth to/from this memory (bytes/s)
28 system.physmem.bw_total::cpu.data 1155704 # Total bandwidth to/from this memory (bytes/s)
29 system.physmem.bw_total::total 2568532 # Total bandwidth to/from this memory (bytes/s)
30 system.membus.throughput 2568532 # Throughput (bytes/s)
31 system.membus.trans_dist::ReadReq 3043 # Transaction distribution
32 system.membus.trans_dist::ReadResp 3043 # Transaction distribution
33 system.membus.trans_dist::ReadExReq 1722 # Transaction distribution
34 system.membus.trans_dist::ReadExResp 1722 # Transaction distribution
35 system.membus.pkt_count_system.cpu.l2cache.mem_side 9530 # Packet count per connected master and slave (bytes)
36 system.membus.pkt_count 9530 # Packet count per connected master and slave (bytes)
37 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 304960 # Cumulative packet size per connected master and slave (bytes)
38 system.membus.tot_pkt_size 304960 # Cumulative packet size per connected master and slave (bytes)
39 system.membus.data_through_bus 304960 # Total data (bytes)
40 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
41 system.membus.reqLayer0.occupancy 4765000 # Layer occupancy (ticks)
42 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
43 system.membus.respLayer1.occupancy 42885000 # Layer occupancy (ticks)
44 system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
45 system.cpu.dtb.fetch_hits 0 # ITB hits
46 system.cpu.dtb.fetch_misses 0 # ITB misses
47 system.cpu.dtb.fetch_acv 0 # ITB acv
48 system.cpu.dtb.fetch_accesses 0 # ITB accesses
49 system.cpu.dtb.read_hits 19996198 # DTB read hits
50 system.cpu.dtb.read_misses 10 # DTB read misses
51 system.cpu.dtb.read_acv 0 # DTB read access violations
52 system.cpu.dtb.read_accesses 19996208 # DTB read accesses
53 system.cpu.dtb.write_hits 6501103 # DTB write hits
54 system.cpu.dtb.write_misses 23 # DTB write misses
55 system.cpu.dtb.write_acv 0 # DTB write access violations
56 system.cpu.dtb.write_accesses 6501126 # DTB write accesses
57 system.cpu.dtb.data_hits 26497301 # DTB hits
58 system.cpu.dtb.data_misses 33 # DTB misses
59 system.cpu.dtb.data_acv 0 # DTB access violations
60 system.cpu.dtb.data_accesses 26497334 # DTB accesses
61 system.cpu.itb.fetch_hits 91903090 # ITB hits
62 system.cpu.itb.fetch_misses 47 # ITB misses
63 system.cpu.itb.fetch_acv 0 # ITB acv
64 system.cpu.itb.fetch_accesses 91903137 # ITB accesses
65 system.cpu.itb.read_hits 0 # DTB read hits
66 system.cpu.itb.read_misses 0 # DTB read misses
67 system.cpu.itb.read_acv 0 # DTB read access violations
68 system.cpu.itb.read_accesses 0 # DTB read accesses
69 system.cpu.itb.write_hits 0 # DTB write hits
70 system.cpu.itb.write_misses 0 # DTB write misses
71 system.cpu.itb.write_acv 0 # DTB write access violations
72 system.cpu.itb.write_accesses 0 # DTB write accesses
73 system.cpu.itb.data_hits 0 # DTB hits
74 system.cpu.itb.data_misses 0 # DTB misses
75 system.cpu.itb.data_acv 0 # DTB access violations
76 system.cpu.itb.data_accesses 0 # DTB accesses
77 system.cpu.workload.num_syscalls 389 # Number of system calls
78 system.cpu.numCycles 237458632 # number of cpu cycles simulated
79 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
80 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
81 system.cpu.committedInsts 91903056 # Number of instructions committed
82 system.cpu.committedOps 91903056 # Number of ops (including micro ops) committed
83 system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses
84 system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses
85 system.cpu.num_func_calls 2059216 # number of times a function call or return occured
86 system.cpu.num_conditional_control_insts 7465012 # number of instructions that are conditional controls
87 system.cpu.num_int_insts 79581109 # number of integer instructions
88 system.cpu.num_fp_insts 6862064 # number of float instructions
89 system.cpu.num_int_register_reads 115028592 # number of times the integer registers were read
90 system.cpu.num_int_register_writes 62575473 # number of times the integer registers were written
91 system.cpu.num_fp_register_reads 6071661 # number of times the floating registers were read
92 system.cpu.num_fp_register_writes 5851888 # number of times the floating registers were written
93 system.cpu.num_mem_refs 26497334 # number of memory refs
94 system.cpu.num_load_insts 19996208 # Number of load instructions
95 system.cpu.num_store_insts 6501126 # Number of store instructions
96 system.cpu.num_idle_cycles 0 # Number of idle cycles
97 system.cpu.num_busy_cycles 237458632 # Number of busy cycles
98 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
99 system.cpu.idle_fraction 0 # Percentage of idle cycles
100 system.cpu.icache.replacements 6681 # number of replacements
101 system.cpu.icache.tagsinuse 1418.052773 # Cycle average of tags in use
102 system.cpu.icache.total_refs 91894580 # Total number of references to valid blocks.
103 system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks.
104 system.cpu.icache.avg_refs 10798.423032 # Average number of references to valid blocks.
105 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
106 system.cpu.icache.occ_blocks::cpu.inst 1418.052773 # Average occupied blocks per requestor
107 system.cpu.icache.occ_percent::cpu.inst 0.692409 # Average percentage of cache occupancy
108 system.cpu.icache.occ_percent::total 0.692409 # Average percentage of cache occupancy
109 system.cpu.icache.ReadReq_hits::cpu.inst 91894580 # number of ReadReq hits
110 system.cpu.icache.ReadReq_hits::total 91894580 # number of ReadReq hits
111 system.cpu.icache.demand_hits::cpu.inst 91894580 # number of demand (read+write) hits
112 system.cpu.icache.demand_hits::total 91894580 # number of demand (read+write) hits
113 system.cpu.icache.overall_hits::cpu.inst 91894580 # number of overall hits
114 system.cpu.icache.overall_hits::total 91894580 # number of overall hits
115 system.cpu.icache.ReadReq_misses::cpu.inst 8510 # number of ReadReq misses
116 system.cpu.icache.ReadReq_misses::total 8510 # number of ReadReq misses
117 system.cpu.icache.demand_misses::cpu.inst 8510 # number of demand (read+write) misses
118 system.cpu.icache.demand_misses::total 8510 # number of demand (read+write) misses
119 system.cpu.icache.overall_misses::cpu.inst 8510 # number of overall misses
120 system.cpu.icache.overall_misses::total 8510 # number of overall misses
121 system.cpu.icache.ReadReq_miss_latency::cpu.inst 220712000 # number of ReadReq miss cycles
122 system.cpu.icache.ReadReq_miss_latency::total 220712000 # number of ReadReq miss cycles
123 system.cpu.icache.demand_miss_latency::cpu.inst 220712000 # number of demand (read+write) miss cycles
124 system.cpu.icache.demand_miss_latency::total 220712000 # number of demand (read+write) miss cycles
125 system.cpu.icache.overall_miss_latency::cpu.inst 220712000 # number of overall miss cycles
126 system.cpu.icache.overall_miss_latency::total 220712000 # number of overall miss cycles
127 system.cpu.icache.ReadReq_accesses::cpu.inst 91903090 # number of ReadReq accesses(hits+misses)
128 system.cpu.icache.ReadReq_accesses::total 91903090 # number of ReadReq accesses(hits+misses)
129 system.cpu.icache.demand_accesses::cpu.inst 91903090 # number of demand (read+write) accesses
130 system.cpu.icache.demand_accesses::total 91903090 # number of demand (read+write) accesses
131 system.cpu.icache.overall_accesses::cpu.inst 91903090 # number of overall (read+write) accesses
132 system.cpu.icache.overall_accesses::total 91903090 # number of overall (read+write) accesses
133 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses
134 system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses
135 system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses
136 system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses
137 system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses
138 system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses
139 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25935.605170 # average ReadReq miss latency
140 system.cpu.icache.ReadReq_avg_miss_latency::total 25935.605170 # average ReadReq miss latency
141 system.cpu.icache.demand_avg_miss_latency::cpu.inst 25935.605170 # average overall miss latency
142 system.cpu.icache.demand_avg_miss_latency::total 25935.605170 # average overall miss latency
143 system.cpu.icache.overall_avg_miss_latency::cpu.inst 25935.605170 # average overall miss latency
144 system.cpu.icache.overall_avg_miss_latency::total 25935.605170 # average overall miss latency
145 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
146 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
147 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
148 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
149 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
150 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
151 system.cpu.icache.fast_writes 0 # number of fast writes performed
152 system.cpu.icache.cache_copies 0 # number of cache copies performed
153 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8510 # number of ReadReq MSHR misses
154 system.cpu.icache.ReadReq_mshr_misses::total 8510 # number of ReadReq MSHR misses
155 system.cpu.icache.demand_mshr_misses::cpu.inst 8510 # number of demand (read+write) MSHR misses
156 system.cpu.icache.demand_mshr_misses::total 8510 # number of demand (read+write) MSHR misses
157 system.cpu.icache.overall_mshr_misses::cpu.inst 8510 # number of overall MSHR misses
158 system.cpu.icache.overall_mshr_misses::total 8510 # number of overall MSHR misses
159 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 203692000 # number of ReadReq MSHR miss cycles
160 system.cpu.icache.ReadReq_mshr_miss_latency::total 203692000 # number of ReadReq MSHR miss cycles
161 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 203692000 # number of demand (read+write) MSHR miss cycles
162 system.cpu.icache.demand_mshr_miss_latency::total 203692000 # number of demand (read+write) MSHR miss cycles
163 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 203692000 # number of overall MSHR miss cycles
164 system.cpu.icache.overall_mshr_miss_latency::total 203692000 # number of overall MSHR miss cycles
165 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for ReadReq accesses
166 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000093 # mshr miss rate for ReadReq accesses
167 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for demand accesses
168 system.cpu.icache.demand_mshr_miss_rate::total 0.000093 # mshr miss rate for demand accesses
169 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for overall accesses
170 system.cpu.icache.overall_mshr_miss_rate::total 0.000093 # mshr miss rate for overall accesses
171 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23935.605170 # average ReadReq mshr miss latency
172 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23935.605170 # average ReadReq mshr miss latency
173 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency
174 system.cpu.icache.demand_avg_mshr_miss_latency::total 23935.605170 # average overall mshr miss latency
175 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency
176 system.cpu.icache.overall_avg_mshr_miss_latency::total 23935.605170 # average overall mshr miss latency
177 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
178 system.cpu.l2cache.replacements 0 # number of replacements
179 system.cpu.l2cache.tagsinuse 2074.070560 # Cycle average of tags in use
180 system.cpu.l2cache.total_refs 5956 # Total number of references to valid blocks.
181 system.cpu.l2cache.sampled_refs 3109 # Sample count of references to valid blocks.
182 system.cpu.l2cache.avg_refs 1.915729 # Average number of references to valid blocks.
183 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
184 system.cpu.l2cache.occ_blocks::writebacks 17.795178 # Average occupied blocks per requestor
185 system.cpu.l2cache.occ_blocks::cpu.inst 1705.018003 # Average occupied blocks per requestor
186 system.cpu.l2cache.occ_blocks::cpu.data 351.257379 # Average occupied blocks per requestor
187 system.cpu.l2cache.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy
188 system.cpu.l2cache.occ_percent::cpu.inst 0.052033 # Average percentage of cache occupancy
189 system.cpu.l2cache.occ_percent::cpu.data 0.010720 # Average percentage of cache occupancy
190 system.cpu.l2cache.occ_percent::total 0.063296 # Average percentage of cache occupancy
191 system.cpu.l2cache.ReadReq_hits::cpu.inst 5889 # number of ReadReq hits
192 system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits
193 system.cpu.l2cache.ReadReq_hits::total 5942 # number of ReadReq hits
194 system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits
195 system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits
196 system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits
197 system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits
198 system.cpu.l2cache.demand_hits::cpu.inst 5889 # number of demand (read+write) hits
199 system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits
200 system.cpu.l2cache.demand_hits::total 5968 # number of demand (read+write) hits
201 system.cpu.l2cache.overall_hits::cpu.inst 5889 # number of overall hits
202 system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits
203 system.cpu.l2cache.overall_hits::total 5968 # number of overall hits
204 system.cpu.l2cache.ReadReq_misses::cpu.inst 2621 # number of ReadReq misses
205 system.cpu.l2cache.ReadReq_misses::cpu.data 422 # number of ReadReq misses
206 system.cpu.l2cache.ReadReq_misses::total 3043 # number of ReadReq misses
207 system.cpu.l2cache.ReadExReq_misses::cpu.data 1722 # number of ReadExReq misses
208 system.cpu.l2cache.ReadExReq_misses::total 1722 # number of ReadExReq misses
209 system.cpu.l2cache.demand_misses::cpu.inst 2621 # number of demand (read+write) misses
210 system.cpu.l2cache.demand_misses::cpu.data 2144 # number of demand (read+write) misses
211 system.cpu.l2cache.demand_misses::total 4765 # number of demand (read+write) misses
212 system.cpu.l2cache.overall_misses::cpu.inst 2621 # number of overall misses
213 system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses
214 system.cpu.l2cache.overall_misses::total 4765 # number of overall misses
215 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 136292000 # number of ReadReq miss cycles
216 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21944000 # number of ReadReq miss cycles
217 system.cpu.l2cache.ReadReq_miss_latency::total 158236000 # number of ReadReq miss cycles
218 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 89544000 # number of ReadExReq miss cycles
219 system.cpu.l2cache.ReadExReq_miss_latency::total 89544000 # number of ReadExReq miss cycles
220 system.cpu.l2cache.demand_miss_latency::cpu.inst 136292000 # number of demand (read+write) miss cycles
221 system.cpu.l2cache.demand_miss_latency::cpu.data 111488000 # number of demand (read+write) miss cycles
222 system.cpu.l2cache.demand_miss_latency::total 247780000 # number of demand (read+write) miss cycles
223 system.cpu.l2cache.overall_miss_latency::cpu.inst 136292000 # number of overall miss cycles
224 system.cpu.l2cache.overall_miss_latency::cpu.data 111488000 # number of overall miss cycles
225 system.cpu.l2cache.overall_miss_latency::total 247780000 # number of overall miss cycles
226 system.cpu.l2cache.ReadReq_accesses::cpu.inst 8510 # number of ReadReq accesses(hits+misses)
227 system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses)
228 system.cpu.l2cache.ReadReq_accesses::total 8985 # number of ReadReq accesses(hits+misses)
229 system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses)
230 system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses)
231 system.cpu.l2cache.ReadExReq_accesses::cpu.data 1748 # number of ReadExReq accesses(hits+misses)
232 system.cpu.l2cache.ReadExReq_accesses::total 1748 # number of ReadExReq accesses(hits+misses)
233 system.cpu.l2cache.demand_accesses::cpu.inst 8510 # number of demand (read+write) accesses
234 system.cpu.l2cache.demand_accesses::cpu.data 2223 # number of demand (read+write) accesses
235 system.cpu.l2cache.demand_accesses::total 10733 # number of demand (read+write) accesses
236 system.cpu.l2cache.overall_accesses::cpu.inst 8510 # number of overall (read+write) accesses
237 system.cpu.l2cache.overall_accesses::cpu.data 2223 # number of overall (read+write) accesses
238 system.cpu.l2cache.overall_accesses::total 10733 # number of overall (read+write) accesses
239 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.307991 # miss rate for ReadReq accesses
240 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.888421 # miss rate for ReadReq accesses
241 system.cpu.l2cache.ReadReq_miss_rate::total 0.338676 # miss rate for ReadReq accesses
242 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses
243 system.cpu.l2cache.ReadExReq_miss_rate::total 0.985126 # miss rate for ReadExReq accesses
244 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.307991 # miss rate for demand accesses
245 system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses
246 system.cpu.l2cache.demand_miss_rate::total 0.443958 # miss rate for demand accesses
247 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.307991 # miss rate for overall accesses
248 system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses
249 system.cpu.l2cache.overall_miss_rate::total 0.443958 # miss rate for overall accesses
250 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
251 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
252 system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
253 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
254 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
255 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
256 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
257 system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
258 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
259 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
260 system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
261 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
262 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
263 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
264 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
265 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
266 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
267 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
268 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
269 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2621 # number of ReadReq MSHR misses
270 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 422 # number of ReadReq MSHR misses
271 system.cpu.l2cache.ReadReq_mshr_misses::total 3043 # number of ReadReq MSHR misses
272 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1722 # number of ReadExReq MSHR misses
273 system.cpu.l2cache.ReadExReq_mshr_misses::total 1722 # number of ReadExReq MSHR misses
274 system.cpu.l2cache.demand_mshr_misses::cpu.inst 2621 # number of demand (read+write) MSHR misses
275 system.cpu.l2cache.demand_mshr_misses::cpu.data 2144 # number of demand (read+write) MSHR misses
276 system.cpu.l2cache.demand_mshr_misses::total 4765 # number of demand (read+write) MSHR misses
277 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2621 # number of overall MSHR misses
278 system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses
279 system.cpu.l2cache.overall_mshr_misses::total 4765 # number of overall MSHR misses
280 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104840000 # number of ReadReq MSHR miss cycles
281 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16880000 # number of ReadReq MSHR miss cycles
282 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 121720000 # number of ReadReq MSHR miss cycles
283 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 68880000 # number of ReadExReq MSHR miss cycles
284 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 68880000 # number of ReadExReq MSHR miss cycles
285 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104840000 # number of demand (read+write) MSHR miss cycles
286 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 85760000 # number of demand (read+write) MSHR miss cycles
287 system.cpu.l2cache.demand_mshr_miss_latency::total 190600000 # number of demand (read+write) MSHR miss cycles
288 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104840000 # number of overall MSHR miss cycles
289 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 85760000 # number of overall MSHR miss cycles
290 system.cpu.l2cache.overall_mshr_miss_latency::total 190600000 # number of overall MSHR miss cycles
291 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for ReadReq accesses
292 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses
293 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.338676 # mshr miss rate for ReadReq accesses
294 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses
295 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985126 # mshr miss rate for ReadExReq accesses
296 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for demand accesses
297 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses
298 system.cpu.l2cache.demand_mshr_miss_rate::total 0.443958 # mshr miss rate for demand accesses
299 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for overall accesses
300 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses
301 system.cpu.l2cache.overall_mshr_miss_rate::total 0.443958 # mshr miss rate for overall accesses
302 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
303 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
304 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
305 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
306 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
307 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
308 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
309 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
310 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
311 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
312 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
313 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
314 system.cpu.dcache.replacements 157 # number of replacements
315 system.cpu.dcache.tagsinuse 1442.043392 # Cycle average of tags in use
316 system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks.
317 system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks.
318 system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks.
319 system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
320 system.cpu.dcache.occ_blocks::cpu.data 1442.043392 # Average occupied blocks per requestor
321 system.cpu.dcache.occ_percent::cpu.data 0.352061 # Average percentage of cache occupancy
322 system.cpu.dcache.occ_percent::total 0.352061 # Average percentage of cache occupancy
323 system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits
324 system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits
325 system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits
326 system.cpu.dcache.WriteReq_hits::total 6499355 # number of WriteReq hits
327 system.cpu.dcache.demand_hits::cpu.data 26495078 # number of demand (read+write) hits
328 system.cpu.dcache.demand_hits::total 26495078 # number of demand (read+write) hits
329 system.cpu.dcache.overall_hits::cpu.data 26495078 # number of overall hits
330 system.cpu.dcache.overall_hits::total 26495078 # number of overall hits
331 system.cpu.dcache.ReadReq_misses::cpu.data 475 # number of ReadReq misses
332 system.cpu.dcache.ReadReq_misses::total 475 # number of ReadReq misses
333 system.cpu.dcache.WriteReq_misses::cpu.data 1748 # number of WriteReq misses
334 system.cpu.dcache.WriteReq_misses::total 1748 # number of WriteReq misses
335 system.cpu.dcache.demand_misses::cpu.data 2223 # number of demand (read+write) misses
336 system.cpu.dcache.demand_misses::total 2223 # number of demand (read+write) misses
337 system.cpu.dcache.overall_misses::cpu.data 2223 # number of overall misses
338 system.cpu.dcache.overall_misses::total 2223 # number of overall misses
339 system.cpu.dcache.ReadReq_miss_latency::cpu.data 23899000 # number of ReadReq miss cycles
340 system.cpu.dcache.ReadReq_miss_latency::total 23899000 # number of ReadReq miss cycles
341 system.cpu.dcache.WriteReq_miss_latency::cpu.data 95048000 # number of WriteReq miss cycles
342 system.cpu.dcache.WriteReq_miss_latency::total 95048000 # number of WriteReq miss cycles
343 system.cpu.dcache.demand_miss_latency::cpu.data 118947000 # number of demand (read+write) miss cycles
344 system.cpu.dcache.demand_miss_latency::total 118947000 # number of demand (read+write) miss cycles
345 system.cpu.dcache.overall_miss_latency::cpu.data 118947000 # number of overall miss cycles
346 system.cpu.dcache.overall_miss_latency::total 118947000 # number of overall miss cycles
347 system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses)
348 system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses)
349 system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
350 system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses)
351 system.cpu.dcache.demand_accesses::cpu.data 26497301 # number of demand (read+write) accesses
352 system.cpu.dcache.demand_accesses::total 26497301 # number of demand (read+write) accesses
353 system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses
354 system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses
355 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses
356 system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses
357 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000269 # miss rate for WriteReq accesses
358 system.cpu.dcache.WriteReq_miss_rate::total 0.000269 # miss rate for WriteReq accesses
359 system.cpu.dcache.demand_miss_rate::cpu.data 0.000084 # miss rate for demand accesses
360 system.cpu.dcache.demand_miss_rate::total 0.000084 # miss rate for demand accesses
361 system.cpu.dcache.overall_miss_rate::cpu.data 0.000084 # miss rate for overall accesses
362 system.cpu.dcache.overall_miss_rate::total 0.000084 # miss rate for overall accesses
363 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50313.684211 # average ReadReq miss latency
364 system.cpu.dcache.ReadReq_avg_miss_latency::total 50313.684211 # average ReadReq miss latency
365 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54375.286041 # average WriteReq miss latency
366 system.cpu.dcache.WriteReq_avg_miss_latency::total 54375.286041 # average WriteReq miss latency
367 system.cpu.dcache.demand_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency
368 system.cpu.dcache.demand_avg_miss_latency::total 53507.422402 # average overall miss latency
369 system.cpu.dcache.overall_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency
370 system.cpu.dcache.overall_avg_miss_latency::total 53507.422402 # average overall miss latency
371 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
372 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
373 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
374 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
375 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
376 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
377 system.cpu.dcache.fast_writes 0 # number of fast writes performed
378 system.cpu.dcache.cache_copies 0 # number of cache copies performed
379 system.cpu.dcache.writebacks::writebacks 107 # number of writebacks
380 system.cpu.dcache.writebacks::total 107 # number of writebacks
381 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses
382 system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses
383 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses
384 system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses
385 system.cpu.dcache.demand_mshr_misses::cpu.data 2223 # number of demand (read+write) MSHR misses
386 system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses
387 system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses
388 system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses
389 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22949000 # number of ReadReq MSHR miss cycles
390 system.cpu.dcache.ReadReq_mshr_miss_latency::total 22949000 # number of ReadReq MSHR miss cycles
391 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 91552000 # number of WriteReq MSHR miss cycles
392 system.cpu.dcache.WriteReq_mshr_miss_latency::total 91552000 # number of WriteReq MSHR miss cycles
393 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 114501000 # number of demand (read+write) MSHR miss cycles
394 system.cpu.dcache.demand_mshr_miss_latency::total 114501000 # number of demand (read+write) MSHR miss cycles
395 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 114501000 # number of overall MSHR miss cycles
396 system.cpu.dcache.overall_mshr_miss_latency::total 114501000 # number of overall MSHR miss cycles
397 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
398 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
399 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses
400 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000269 # mshr miss rate for WriteReq accesses
401 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses
402 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
403 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
404 system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
405 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48313.684211 # average ReadReq mshr miss latency
406 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48313.684211 # average ReadReq mshr miss latency
407 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52375.286041 # average WriteReq mshr miss latency
408 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52375.286041 # average WriteReq mshr miss latency
409 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency
410 system.cpu.dcache.demand_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency
411 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency
412 system.cpu.dcache.overall_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency
413 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
414 system.cpu.toL2Bus.throughput 5843207 # Throughput (bytes/s)
415 system.cpu.toL2Bus.trans_dist::ReadReq 8985 # Transaction distribution
416 system.cpu.toL2Bus.trans_dist::ReadResp 8985 # Transaction distribution
417 system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution
418 system.cpu.toL2Bus.trans_dist::ReadExReq 1748 # Transaction distribution
419 system.cpu.toL2Bus.trans_dist::ReadExResp 1748 # Transaction distribution
420 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 17020 # Packet count per connected master and slave (bytes)
421 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 4553 # Packet count per connected master and slave (bytes)
422 system.cpu.toL2Bus.pkt_count 21573 # Packet count per connected master and slave (bytes)
423 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 544640 # Cumulative packet size per connected master and slave (bytes)
424 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 149120 # Cumulative packet size per connected master and slave (bytes)
425 system.cpu.toL2Bus.tot_pkt_size 693760 # Cumulative packet size per connected master and slave (bytes)
426 system.cpu.toL2Bus.data_through_bus 693760 # Total data (bytes)
427 system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
428 system.cpu.toL2Bus.reqLayer0.occupancy 5527000 # Layer occupancy (ticks)
429 system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
430 system.cpu.toL2Bus.respLayer0.occupancy 12765000 # Layer occupancy (ticks)
431 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
432 system.cpu.toL2Bus.respLayer1.occupancy 3334500 # Layer occupancy (ticks)
433 system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
435 ---------- End Simulation Statistics ----------
projects / gem5.git / blob