tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 eventq_index=0
  18 init_param=0
  19 kernel=
  20 kernel_addr_check=true
  21 load_addr_mask=1099511627775
  22 load_offset=0
  23 mem_mode=timing
  24 mem_ranges=
  25 memories=system.physmem
  26 mmap_using_noreserve=false
  27 num_work_ids=16
  28 readfile=
  29 symbolfile=
  30 work_begin_ckpt_count=0
  31 work_begin_cpu_id_exit=-1
  32 work_begin_exit_count=0
  33 work_cpus_ckpt_count=0
  34 work_end_ckpt_count=0
  35 work_end_exit_count=0
  36 work_item_id=-1
  37 system_port=system.membus.slave[0]
  38
  39 [system.clk_domain]
  40 type=SrcClockDomain
  41 clock=1000
  42 domain_id=-1
  43 eventq_index=0
  44 init_perf_level=0
  45 voltage_domain=system.voltage_domain
  46
  47 [system.cpu]
  48 type=MinorCPU
  49 children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
  50 branchPred=system.cpu.branchPred
  51 checker=Null
  52 clk_domain=system.cpu_clk_domain
  53 cpu_id=0
  54 decodeCycleInput=true
  55 decodeInputBufferSize=3
  56 decodeInputWidth=2
  57 decodeToExecuteForwardDelay=1
  58 do_checkpoint_insts=true
  59 do_quiesce=true
  60 do_statistics_insts=true
  61 dstage2_mmu=system.cpu.dstage2_mmu
  62 dtb=system.cpu.dtb
  63 enableIdling=true
  64 eventq_index=0
  65 executeAllowEarlyMemoryIssue=true
  66 executeBranchDelay=1
  67 executeCommitLimit=2
  68 executeCycleInput=true
  69 executeFuncUnits=system.cpu.executeFuncUnits
  70 executeInputBufferSize=7
  71 executeInputWidth=2
  72 executeIssueLimit=2
  73 executeLSQMaxStoreBufferStoresPerCycle=2
  74 executeLSQRequestsQueueSize=1
  75 executeLSQStoreBufferSize=5
  76 executeLSQTransfersQueueSize=2
  77 executeMaxAccessesInMemory=2
  78 executeMemoryCommitLimit=1
  79 executeMemoryIssueLimit=1
  80 executeMemoryWidth=0
  81 executeSetTraceTimeOnCommit=true
  82 executeSetTraceTimeOnIssue=false
  83 fetch1FetchLimit=1
  84 fetch1LineSnapWidth=0
  85 fetch1LineWidth=0
  86 fetch1ToFetch2BackwardDelay=1
  87 fetch1ToFetch2ForwardDelay=1
  88 fetch2CycleInput=true
  89 fetch2InputBufferSize=2
  90 fetch2ToDecodeForwardDelay=1
  91 function_trace=false
  92 function_trace_start=0
  93 interrupts=system.cpu.interrupts
  94 isa=system.cpu.isa
  95 istage2_mmu=system.cpu.istage2_mmu
  96 itb=system.cpu.itb
  97 max_insts_all_threads=0
  98 max_insts_any_thread=0
  99 max_loads_all_threads=0
 100 max_loads_any_thread=0
 101 numThreads=1
 102 profile=0
 103 progress_interval=0
 104 simpoint_start_insts=
 105 socket_id=0
 106 switched_out=false
 107 system=system
 108 tracer=system.cpu.tracer
 109 workload=system.cpu.workload
 110 dcache_port=system.cpu.dcache.cpu_side
 111 icache_port=system.cpu.icache.cpu_side
 112
 113 [system.cpu.branchPred]
 114 type=TournamentBP
 115 BTBEntries=4096
 116 BTBTagSize=16
 117 RASSize=16
 118 choiceCtrBits=2
 119 choicePredictorSize=8192
 120 eventq_index=0
 121 globalCtrBits=2
 122 globalPredictorSize=8192
 123 instShiftAmt=2
 124 localCtrBits=2
 125 localHistoryTableSize=2048
 126 localPredictorSize=2048
 127 numThreads=1
 128
 129 [system.cpu.dcache]
 130 type=BaseCache
 131 children=tags
 132 addr_ranges=0:18446744073709551615
 133 assoc=2
 134 clk_domain=system.cpu_clk_domain
 135 demand_mshr_reserve=1
 136 eventq_index=0
 137 forward_snoops=true
 138 hit_latency=2
 139 is_read_only=false
 140 max_miss_count=0
 141 mshrs=4
 142 prefetch_on_access=false
 143 prefetcher=Null
 144 response_latency=2
 145 sequential_access=false
 146 size=262144
 147 system=system
 148 tags=system.cpu.dcache.tags
 149 tgts_per_mshr=20
 150 write_buffers=8
 151 cpu_side=system.cpu.dcache_port
 152 mem_side=system.cpu.toL2Bus.slave[1]
 153
 154 [system.cpu.dcache.tags]
 155 type=LRU
 156 assoc=2
 157 block_size=64
 158 clk_domain=system.cpu_clk_domain
 159 eventq_index=0
 160 hit_latency=2
 161 sequential_access=false
 162 size=262144
 163
 164 [system.cpu.dstage2_mmu]
 165 type=ArmStage2MMU
 166 children=stage2_tlb
 167 eventq_index=0
 168 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
 169 sys=system
 170 tlb=system.cpu.dtb
 171
 172 [system.cpu.dstage2_mmu.stage2_tlb]
 173 type=ArmTLB
 174 children=walker
 175 eventq_index=0
 176 is_stage2=true
 177 size=32
 178 walker=system.cpu.dstage2_mmu.stage2_tlb.walker
 179
 180 [system.cpu.dstage2_mmu.stage2_tlb.walker]
 181 type=ArmTableWalker
 182 clk_domain=system.cpu_clk_domain
 183 eventq_index=0
 184 is_stage2=true
 185 num_squash_per_cycle=2
 186 sys=system
 187
 188 [system.cpu.dtb]
 189 type=ArmTLB
 190 children=walker
 191 eventq_index=0
 192 is_stage2=false
 193 size=64
 194 walker=system.cpu.dtb.walker
 195
 196 [system.cpu.dtb.walker]
 197 type=ArmTableWalker
 198 clk_domain=system.cpu_clk_domain
 199 eventq_index=0
 200 is_stage2=false
 201 num_squash_per_cycle=2
 202 sys=system
 203 port=system.cpu.toL2Bus.slave[3]
 204
 205 [system.cpu.executeFuncUnits]
 206 type=MinorFUPool
 207 children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
 208 eventq_index=0
 209 funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6
 210
 211 [system.cpu.executeFuncUnits.funcUnits0]
 212 type=MinorFU
 213 children=opClasses timings
 214 cantForwardFromFUIndices=
 215 eventq_index=0
 216 issueLat=1
 217 opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses
 218 opLat=3
 219 timings=system.cpu.executeFuncUnits.funcUnits0.timings
 220
 221 [system.cpu.executeFuncUnits.funcUnits0.opClasses]
 222 type=MinorOpClassSet
 223 children=opClasses
 224 eventq_index=0
 225 opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses
 226
 227 [system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses]
 228 type=MinorOpClass
 229 eventq_index=0
 230 opClass=IntAlu
 231
 232 [system.cpu.executeFuncUnits.funcUnits0.timings]
 233 type=MinorFUTiming
 234 children=opClasses
 235 description=Int
 236 eventq_index=0
 237 extraAssumedLat=0
 238 extraCommitLat=0
 239 extraCommitLatExpr=Null
 240 mask=0
 241 match=0
 242 opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses
 243 srcRegsRelativeLats=2
 244 suppress=false
 245
 246 [system.cpu.executeFuncUnits.funcUnits0.timings.opClasses]
 247 type=MinorOpClassSet
 248 eventq_index=0
 249 opClasses=
 250
 251 [system.cpu.executeFuncUnits.funcUnits1]
 252 type=MinorFU
 253 children=opClasses timings
 254 cantForwardFromFUIndices=
 255 eventq_index=0
 256 issueLat=1
 257 opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses
 258 opLat=3
 259 timings=system.cpu.executeFuncUnits.funcUnits1.timings
 260
 261 [system.cpu.executeFuncUnits.funcUnits1.opClasses]
 262 type=MinorOpClassSet
 263 children=opClasses
 264 eventq_index=0
 265 opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses
 266
 267 [system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses]
 268 type=MinorOpClass
 269 eventq_index=0
 270 opClass=IntAlu
 271
 272 [system.cpu.executeFuncUnits.funcUnits1.timings]
 273 type=MinorFUTiming
 274 children=opClasses
 275 description=Int
 276 eventq_index=0
 277 extraAssumedLat=0
 278 extraCommitLat=0
 279 extraCommitLatExpr=Null
 280 mask=0
 281 match=0
 282 opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses
 283 srcRegsRelativeLats=2
 284 suppress=false
 285
 286 [system.cpu.executeFuncUnits.funcUnits1.timings.opClasses]
 287 type=MinorOpClassSet
 288 eventq_index=0
 289 opClasses=
 290
 291 [system.cpu.executeFuncUnits.funcUnits2]
 292 type=MinorFU
 293 children=opClasses timings
 294 cantForwardFromFUIndices=
 295 eventq_index=0
 296 issueLat=1
 297 opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses
 298 opLat=3
 299 timings=system.cpu.executeFuncUnits.funcUnits2.timings
 300
 301 [system.cpu.executeFuncUnits.funcUnits2.opClasses]
 302 type=MinorOpClassSet
 303 children=opClasses
 304 eventq_index=0
 305 opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses
 306
 307 [system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses]
 308 type=MinorOpClass
 309 eventq_index=0
 310 opClass=IntMult
 311
 312 [system.cpu.executeFuncUnits.funcUnits2.timings]
 313 type=MinorFUTiming
 314 children=opClasses
 315 description=Mul
 316 eventq_index=0
 317 extraAssumedLat=0
 318 extraCommitLat=0
 319 extraCommitLatExpr=Null
 320 mask=0
 321 match=0
 322 opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses
 323 srcRegsRelativeLats=0
 324 suppress=false
 325
 326 [system.cpu.executeFuncUnits.funcUnits2.timings.opClasses]
 327 type=MinorOpClassSet
 328 eventq_index=0
 329 opClasses=
 330
 331 [system.cpu.executeFuncUnits.funcUnits3]
 332 type=MinorFU
 333 children=opClasses
 334 cantForwardFromFUIndices=
 335 eventq_index=0
 336 issueLat=9
 337 opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses
 338 opLat=9
 339 timings=
 340
 341 [system.cpu.executeFuncUnits.funcUnits3.opClasses]
 342 type=MinorOpClassSet
 343 children=opClasses
 344 eventq_index=0
 345 opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses
 346
 347 [system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses]
 348 type=MinorOpClass
 349 eventq_index=0
 350 opClass=IntDiv
 351
 352 [system.cpu.executeFuncUnits.funcUnits4]
 353 type=MinorFU
 354 children=opClasses timings
 355 cantForwardFromFUIndices=
 356 eventq_index=0
 357 issueLat=1
 358 opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses
 359 opLat=6
 360 timings=system.cpu.executeFuncUnits.funcUnits4.timings
 361
 362 [system.cpu.executeFuncUnits.funcUnits4.opClasses]
 363 type=MinorOpClassSet
 364 children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
 365 eventq_index=0
 366 opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25
 367
 368 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
 369 type=MinorOpClass
 370 eventq_index=0
 371 opClass=FloatAdd
 372
 373 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01]
 374 type=MinorOpClass
 375 eventq_index=0
 376 opClass=FloatCmp
 377
 378 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02]
 379 type=MinorOpClass
 380 eventq_index=0
 381 opClass=FloatCvt
 382
 383 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03]
 384 type=MinorOpClass
 385 eventq_index=0
 386 opClass=FloatMult
 387
 388 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
 389 type=MinorOpClass
 390 eventq_index=0
 391 opClass=FloatDiv
 392
 393 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
 394 type=MinorOpClass
 395 eventq_index=0
 396 opClass=FloatSqrt
 397
 398 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
 399 type=MinorOpClass
 400 eventq_index=0
 401 opClass=SimdAdd
 402
 403 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
 404 type=MinorOpClass
 405 eventq_index=0
 406 opClass=SimdAddAcc
 407
 408 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
 409 type=MinorOpClass
 410 eventq_index=0
 411 opClass=SimdAlu
 412
 413 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
 414 type=MinorOpClass
 415 eventq_index=0
 416 opClass=SimdCmp
 417
 418 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
 419 type=MinorOpClass
 420 eventq_index=0
 421 opClass=SimdCvt
 422
 423 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11]
 424 type=MinorOpClass
 425 eventq_index=0
 426 opClass=SimdMisc
 427
 428 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12]
 429 type=MinorOpClass
 430 eventq_index=0
 431 opClass=SimdMult
 432
 433 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
 434 type=MinorOpClass
 435 eventq_index=0
 436 opClass=SimdMultAcc
 437
 438 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
 439 type=MinorOpClass
 440 eventq_index=0
 441 opClass=SimdShift
 442
 443 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
 444 type=MinorOpClass
 445 eventq_index=0
 446 opClass=SimdShiftAcc
 447
 448 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
 449 type=MinorOpClass
 450 eventq_index=0
 451 opClass=SimdSqrt
 452
 453 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17]
 454 type=MinorOpClass
 455 eventq_index=0
 456 opClass=SimdFloatAdd
 457
 458 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
 459 type=MinorOpClass
 460 eventq_index=0
 461 opClass=SimdFloatAlu
 462
 463 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
 464 type=MinorOpClass
 465 eventq_index=0
 466 opClass=SimdFloatCmp
 467
 468 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
 469 type=MinorOpClass
 470 eventq_index=0
 471 opClass=SimdFloatCvt
 472
 473 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
 474 type=MinorOpClass
 475 eventq_index=0
 476 opClass=SimdFloatDiv
 477
 478 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
 479 type=MinorOpClass
 480 eventq_index=0
 481 opClass=SimdFloatMisc
 482
 483 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
 484 type=MinorOpClass
 485 eventq_index=0
 486 opClass=SimdFloatMult
 487
 488 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
 489 type=MinorOpClass
 490 eventq_index=0
 491 opClass=SimdFloatMultAcc
 492
 493 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
 494 type=MinorOpClass
 495 eventq_index=0
 496 opClass=SimdFloatSqrt
 497
 498 [system.cpu.executeFuncUnits.funcUnits4.timings]
 499 type=MinorFUTiming
 500 children=opClasses
 501 description=FloatSimd
 502 eventq_index=0
 503 extraAssumedLat=0
 504 extraCommitLat=0
 505 extraCommitLatExpr=Null
 506 mask=0
 507 match=0
 508 opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses
 509 srcRegsRelativeLats=2
 510 suppress=false
 511
 512 [system.cpu.executeFuncUnits.funcUnits4.timings.opClasses]
 513 type=MinorOpClassSet
 514 eventq_index=0
 515 opClasses=
 516
 517 [system.cpu.executeFuncUnits.funcUnits5]
 518 type=MinorFU
 519 children=opClasses timings
 520 cantForwardFromFUIndices=
 521 eventq_index=0
 522 issueLat=1
 523 opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses
 524 opLat=1
 525 timings=system.cpu.executeFuncUnits.funcUnits5.timings
 526
 527 [system.cpu.executeFuncUnits.funcUnits5.opClasses]
 528 type=MinorOpClassSet
 529 children=opClasses0 opClasses1
 530 eventq_index=0
 531 opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1
 532
 533 [system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
 534 type=MinorOpClass
 535 eventq_index=0
 536 opClass=MemRead
 537
 538 [system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1]
 539 type=MinorOpClass
 540 eventq_index=0
 541 opClass=MemWrite
 542
 543 [system.cpu.executeFuncUnits.funcUnits5.timings]
 544 type=MinorFUTiming
 545 children=opClasses
 546 description=Mem
 547 eventq_index=0
 548 extraAssumedLat=2
 549 extraCommitLat=0
 550 extraCommitLatExpr=Null
 551 mask=0
 552 match=0
 553 opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses
 554 srcRegsRelativeLats=1
 555 suppress=false
 556
 557 [system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
 558 type=MinorOpClassSet
 559 eventq_index=0
 560 opClasses=
 561
 562 [system.cpu.executeFuncUnits.funcUnits6]
 563 type=MinorFU
 564 children=opClasses
 565 cantForwardFromFUIndices=
 566 eventq_index=0
 567 issueLat=1
 568 opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses
 569 opLat=1
 570 timings=
 571
 572 [system.cpu.executeFuncUnits.funcUnits6.opClasses]
 573 type=MinorOpClassSet
 574 children=opClasses0 opClasses1
 575 eventq_index=0
 576 opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1
 577
 578 [system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
 579 type=MinorOpClass
 580 eventq_index=0
 581 opClass=IprAccess
 582
 583 [system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
 584 type=MinorOpClass
 585 eventq_index=0
 586 opClass=InstPrefetch
 587
 588 [system.cpu.icache]
 589 type=BaseCache
 590 children=tags
 591 addr_ranges=0:18446744073709551615
 592 assoc=2
 593 clk_domain=system.cpu_clk_domain
 594 demand_mshr_reserve=1
 595 eventq_index=0
 596 forward_snoops=true
 597 hit_latency=2
 598 is_read_only=true
 599 max_miss_count=0
 600 mshrs=4
 601 prefetch_on_access=false
 602 prefetcher=Null
 603 response_latency=2
 604 sequential_access=false
 605 size=131072
 606 system=system
 607 tags=system.cpu.icache.tags
 608 tgts_per_mshr=20
 609 write_buffers=8
 610 cpu_side=system.cpu.icache_port
 611 mem_side=system.cpu.toL2Bus.slave[0]
 612
 613 [system.cpu.icache.tags]
 614 type=LRU
 615 assoc=2
 616 block_size=64
 617 clk_domain=system.cpu_clk_domain
 618 eventq_index=0
 619 hit_latency=2
 620 sequential_access=false
 621 size=131072
 622
 623 [system.cpu.interrupts]
 624 type=ArmInterrupts
 625 eventq_index=0
 626
 627 [system.cpu.isa]
 628 type=ArmISA
 629 eventq_index=0
 630 fpsid=1090793632
 631 id_aa64afr0_el1=0
 632 id_aa64afr1_el1=0
 633 id_aa64dfr0_el1=1052678
 634 id_aa64dfr1_el1=0
 635 id_aa64isar0_el1=0
 636 id_aa64isar1_el1=0
 637 id_aa64mmfr0_el1=15728642
 638 id_aa64mmfr1_el1=0
 639 id_aa64pfr0_el1=17
 640 id_aa64pfr1_el1=0
 641 id_isar0=34607377
 642 id_isar1=34677009
 643 id_isar2=555950401
 644 id_isar3=17899825
 645 id_isar4=268501314
 646 id_isar5=0
 647 id_mmfr0=270536963
 648 id_mmfr1=0
 649 id_mmfr2=19070976
 650 id_mmfr3=34611729
 651 id_pfr0=49
 652 id_pfr1=4113
 653 midr=1091551472
 654 pmu=Null
 655 system=system
 656
 657 [system.cpu.istage2_mmu]
 658 type=ArmStage2MMU
 659 children=stage2_tlb
 660 eventq_index=0
 661 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
 662 sys=system
 663 tlb=system.cpu.itb
 664
 665 [system.cpu.istage2_mmu.stage2_tlb]
 666 type=ArmTLB
 667 children=walker
 668 eventq_index=0
 669 is_stage2=true
 670 size=32
 671 walker=system.cpu.istage2_mmu.stage2_tlb.walker
 672
 673 [system.cpu.istage2_mmu.stage2_tlb.walker]
 674 type=ArmTableWalker
 675 clk_domain=system.cpu_clk_domain
 676 eventq_index=0
 677 is_stage2=true
 678 num_squash_per_cycle=2
 679 sys=system
 680
 681 [system.cpu.itb]
 682 type=ArmTLB
 683 children=walker
 684 eventq_index=0
 685 is_stage2=false
 686 size=64
 687 walker=system.cpu.itb.walker
 688
 689 [system.cpu.itb.walker]
 690 type=ArmTableWalker
 691 clk_domain=system.cpu_clk_domain
 692 eventq_index=0
 693 is_stage2=false
 694 num_squash_per_cycle=2
 695 sys=system
 696 port=system.cpu.toL2Bus.slave[2]
 697
 698 [system.cpu.l2cache]
 699 type=BaseCache
 700 children=tags
 701 addr_ranges=0:18446744073709551615
 702 assoc=8
 703 clk_domain=system.cpu_clk_domain
 704 demand_mshr_reserve=1
 705 eventq_index=0
 706 forward_snoops=true
 707 hit_latency=20
 708 is_read_only=false
 709 max_miss_count=0
 710 mshrs=20
 711 prefetch_on_access=false
 712 prefetcher=Null
 713 response_latency=20
 714 sequential_access=false
 715 size=2097152
 716 system=system
 717 tags=system.cpu.l2cache.tags
 718 tgts_per_mshr=12
 719 write_buffers=8
 720 cpu_side=system.cpu.toL2Bus.master[0]
 721 mem_side=system.membus.slave[1]
 722
 723 [system.cpu.l2cache.tags]
 724 type=LRU
 725 assoc=8
 726 block_size=64
 727 clk_domain=system.cpu_clk_domain
 728 eventq_index=0
 729 hit_latency=20
 730 sequential_access=false
 731 size=2097152
 732
 733 [system.cpu.toL2Bus]
 734 type=CoherentXBar
 735 clk_domain=system.cpu_clk_domain
 736 eventq_index=0
 737 forward_latency=0
 738 frontend_latency=1
 739 response_latency=1
 740 snoop_filter=Null
 741 snoop_response_latency=1
 742 system=system
 743 use_default_range=false
 744 width=32
 745 master=system.cpu.l2cache.cpu_side
 746 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 747
 748 [system.cpu.tracer]
 749 type=ExeTracer
 750 eventq_index=0
 751
 752 [system.cpu.workload]
 753 type=LiveProcess
 754 cmd=twolf smred
 755 cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing
 756 drivers=
 757 egid=100
 758 env=
 759 errout=cerr
 760 euid=100
 761 eventq_index=0
 762 executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
 763 gid=100
 764 input=cin
 765 kvmInSE=false
 766 max_stack_size=67108864
 767 output=cout
 768 pid=100
 769 ppid=99
 770 simpoint=0
 771 system=system
 772 uid=100
 773 useArchPT=false
 774
 775 [system.cpu_clk_domain]
 776 type=SrcClockDomain
 777 clock=500
 778 domain_id=-1
 779 eventq_index=0
 780 init_perf_level=0
 781 voltage_domain=system.voltage_domain
 782
 783 [system.dvfs_handler]
 784 type=DVFSHandler
 785 domains=
 786 enable=false
 787 eventq_index=0
 788 sys_clk_domain=system.clk_domain
 789 transition_latency=100000000
 790
 791 [system.membus]
 792 type=CoherentXBar
 793 clk_domain=system.clk_domain
 794 eventq_index=0
 795 forward_latency=4
 796 frontend_latency=3
 797 response_latency=2
 798 snoop_filter=Null
 799 snoop_response_latency=4
 800 system=system
 801 use_default_range=false
 802 width=16
 803 master=system.physmem.port
 804 slave=system.system_port system.cpu.l2cache.mem_side
 805
 806 [system.physmem]
 807 type=DRAMCtrl
 808 IDD0=0.075000
 809 IDD02=0.000000
 810 IDD2N=0.050000
 811 IDD2N2=0.000000
 812 IDD2P0=0.000000
 813 IDD2P02=0.000000
 814 IDD2P1=0.000000
 815 IDD2P12=0.000000
 816 IDD3N=0.057000
 817 IDD3N2=0.000000
 818 IDD3P0=0.000000
 819 IDD3P02=0.000000
 820 IDD3P1=0.000000
 821 IDD3P12=0.000000
 822 IDD4R=0.187000
 823 IDD4R2=0.000000
 824 IDD4W=0.165000
 825 IDD4W2=0.000000
 826 IDD5=0.220000
 827 IDD52=0.000000
 828 IDD6=0.000000
 829 IDD62=0.000000
 830 VDD=1.500000
 831 VDD2=0.000000
 832 activation_limit=4
 833 addr_mapping=RoRaBaCoCh
 834 bank_groups_per_rank=0
 835 banks_per_rank=8
 836 burst_length=8
 837 channels=1
 838 clk_domain=system.clk_domain
 839 conf_table_reported=true
 840 device_bus_width=8
 841 device_rowbuffer_size=1024
 842 device_size=536870912
 843 devices_per_rank=8
 844 dll=true
 845 eventq_index=0
 846 in_addr_map=true
 847 max_accesses_per_row=16
 848 mem_sched_policy=frfcfs
 849 min_writes_per_switch=16
 850 null=false
 851 page_policy=open_adaptive
 852 range=0:134217727
 853 ranks_per_channel=2
 854 read_buffer_size=32
 855 static_backend_latency=10000
 856 static_frontend_latency=10000
 857 tBURST=5000
 858 tCCD_L=0
 859 tCK=1250
 860 tCL=13750
 861 tCS=2500
 862 tRAS=35000
 863 tRCD=13750
 864 tREFI=7800000
 865 tRFC=260000
 866 tRP=13750
 867 tRRD=6000
 868 tRRD_L=0
 869 tRTP=7500
 870 tRTW=2500
 871 tWR=15000
 872 tWTR=7500
 873 tXAW=30000
 874 tXP=0
 875 tXPDLL=0
 876 tXS=0
 877 tXSDLL=0
 878 write_buffer_size=64
 879 write_high_thresh_perc=85
 880 write_low_thresh_perc=50
 881 port=system.membus.master[0]
 882
 883 [system.voltage_domain]
 884 type=VoltageDomain
 885 eventq_index=0
 886 voltage=1.000000
 887