2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.132570 # Number of seconds simulated
4 sim_ticks 132570000500 # Number of ticks simulated
5 final_tick 132570000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 373440 # Simulator instruction rate (inst/s)
8 host_op_rate 393666 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 287300012 # Simulator tick rate (ticks/s)
10 host_mem_usage 274936 # Number of bytes of host memory used
11 host_seconds 461.43 # Real time elapsed on the host
12 sim_insts 172317810 # Number of instructions simulated
13 sim_ops 181650743 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
17 system.physmem.bytes_read::cpu.inst 138240 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory
19 system.physmem.bytes_read::total 247552 # Number of bytes read from this memory
20 system.physmem.bytes_inst_read::cpu.inst 138240 # Number of instructions bytes read from this memory
21 system.physmem.bytes_inst_read::total 138240 # Number of instructions bytes read from this memory
22 system.physmem.num_reads::cpu.inst 2160 # Number of read requests responded to by this memory
23 system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory
24 system.physmem.num_reads::total 3868 # Number of read requests responded to by this memory
25 system.physmem.bw_read::cpu.inst 1042770 # Total read bandwidth from this memory (bytes/s)
26 system.physmem.bw_read::cpu.data 824561 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_read::total 1867330 # Total read bandwidth from this memory (bytes/s)
28 system.physmem.bw_inst_read::cpu.inst 1042770 # Instruction read bandwidth from this memory (bytes/s)
29 system.physmem.bw_inst_read::total 1042770 # Instruction read bandwidth from this memory (bytes/s)
30 system.physmem.bw_total::cpu.inst 1042770 # Total bandwidth to/from this memory (bytes/s)
31 system.physmem.bw_total::cpu.data 824561 # Total bandwidth to/from this memory (bytes/s)
32 system.physmem.bw_total::total 1867330 # Total bandwidth to/from this memory (bytes/s)
33 system.physmem.readReqs 3868 # Number of read requests accepted
34 system.physmem.writeReqs 0 # Number of write requests accepted
35 system.physmem.readBursts 3868 # Number of DRAM read bursts, including those serviced by the write queue
36 system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
37 system.physmem.bytesReadDRAM 247552 # Total number of bytes read from DRAM
38 system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
39 system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
40 system.physmem.bytesReadSys 247552 # Total read bytes from the system interface side
41 system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
42 system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
43 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
44 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
45 system.physmem.perBankRdBursts::0 305 # Per bank write bursts
46 system.physmem.perBankRdBursts::1 217 # Per bank write bursts
47 system.physmem.perBankRdBursts::2 135 # Per bank write bursts
48 system.physmem.perBankRdBursts::3 313 # Per bank write bursts
49 system.physmem.perBankRdBursts::4 306 # Per bank write bursts
50 system.physmem.perBankRdBursts::5 305 # Per bank write bursts
51 system.physmem.perBankRdBursts::6 273 # Per bank write bursts
52 system.physmem.perBankRdBursts::7 222 # Per bank write bursts
53 system.physmem.perBankRdBursts::8 248 # Per bank write bursts
54 system.physmem.perBankRdBursts::9 218 # Per bank write bursts
55 system.physmem.perBankRdBursts::10 296 # Per bank write bursts
56 system.physmem.perBankRdBursts::11 200 # Per bank write bursts
57 system.physmem.perBankRdBursts::12 183 # Per bank write bursts
58 system.physmem.perBankRdBursts::13 218 # Per bank write bursts
59 system.physmem.perBankRdBursts::14 224 # Per bank write bursts
60 system.physmem.perBankRdBursts::15 205 # Per bank write bursts
61 system.physmem.perBankWrBursts::0 0 # Per bank write bursts
62 system.physmem.perBankWrBursts::1 0 # Per bank write bursts
63 system.physmem.perBankWrBursts::2 0 # Per bank write bursts
64 system.physmem.perBankWrBursts::3 0 # Per bank write bursts
65 system.physmem.perBankWrBursts::4 0 # Per bank write bursts
66 system.physmem.perBankWrBursts::5 0 # Per bank write bursts
67 system.physmem.perBankWrBursts::6 0 # Per bank write bursts
68 system.physmem.perBankWrBursts::7 0 # Per bank write bursts
69 system.physmem.perBankWrBursts::8 0 # Per bank write bursts
70 system.physmem.perBankWrBursts::9 0 # Per bank write bursts
71 system.physmem.perBankWrBursts::10 0 # Per bank write bursts
72 system.physmem.perBankWrBursts::11 0 # Per bank write bursts
73 system.physmem.perBankWrBursts::12 0 # Per bank write bursts
74 system.physmem.perBankWrBursts::13 0 # Per bank write bursts
75 system.physmem.perBankWrBursts::14 0 # Per bank write bursts
76 system.physmem.perBankWrBursts::15 0 # Per bank write bursts
77 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
78 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
79 system.physmem.totGap 132569899500 # Total gap between requests
80 system.physmem.readPktSize::0 0 # Read request sizes (log2)
81 system.physmem.readPktSize::1 0 # Read request sizes (log2)
82 system.physmem.readPktSize::2 0 # Read request sizes (log2)
83 system.physmem.readPktSize::3 0 # Read request sizes (log2)
84 system.physmem.readPktSize::4 0 # Read request sizes (log2)
85 system.physmem.readPktSize::5 0 # Read request sizes (log2)
86 system.physmem.readPktSize::6 3868 # Read request sizes (log2)
87 system.physmem.writePktSize::0 0 # Write request sizes (log2)
88 system.physmem.writePktSize::1 0 # Write request sizes (log2)
89 system.physmem.writePktSize::2 0 # Write request sizes (log2)
90 system.physmem.writePktSize::3 0 # Write request sizes (log2)
91 system.physmem.writePktSize::4 0 # Write request sizes (log2)
92 system.physmem.writePktSize::5 0 # Write request sizes (log2)
93 system.physmem.writePktSize::6 0 # Write request sizes (log2)
94 system.physmem.rdQLenPdf::0 3619 # What read queue length does an incoming req see
95 system.physmem.rdQLenPdf::1 239 # What read queue length does an incoming req see
96 system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see
97 system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
98 system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
99 system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
100 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
126 system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
127 system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
128 system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
129 system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
130 system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
131 system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
132 system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
190 system.physmem.bytesPerActivate::samples 928 # Bytes accessed per row activation
191 system.physmem.bytesPerActivate::mean 265.103448 # Bytes accessed per row activation
192 system.physmem.bytesPerActivate::gmean 174.513478 # Bytes accessed per row activation
193 system.physmem.bytesPerActivate::stdev 277.064139 # Bytes accessed per row activation
194 system.physmem.bytesPerActivate::0-127 273 29.42% 29.42% # Bytes accessed per row activation
195 system.physmem.bytesPerActivate::128-255 364 39.22% 68.64% # Bytes accessed per row activation
196 system.physmem.bytesPerActivate::256-383 95 10.24% 78.88% # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::384-511 53 5.71% 84.59% # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::512-639 24 2.59% 87.18% # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::640-767 21 2.26% 89.44% # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::768-895 18 1.94% 91.38% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::896-1023 18 1.94% 93.32% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::1024-1151 62 6.68% 100.00% # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::total 928 # Bytes accessed per row activation
204 system.physmem.totQLat 82551750 # Total ticks spent queuing
205 system.physmem.totMemAccLat 155076750 # Total ticks spent from burst creation until serviced by the DRAM
206 system.physmem.totBusLat 19340000 # Total ticks spent in databus transfers
207 system.physmem.avgQLat 21342.23 # Average queueing delay per DRAM burst
208 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
209 system.physmem.avgMemAccLat 40092.23 # Average memory access latency per DRAM burst
210 system.physmem.avgRdBW 1.87 # Average DRAM read bandwidth in MiByte/s
211 system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
212 system.physmem.avgRdBWSys 1.87 # Average system read bandwidth in MiByte/s
213 system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
214 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
215 system.physmem.busUtil 0.01 # Data bus utilization in percentage
216 system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
217 system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
218 system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
219 system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
220 system.physmem.readRowHits 2935 # Number of row buffer hits during reads
221 system.physmem.writeRowHits 0 # Number of row buffer hits during writes
222 system.physmem.readRowHitRate 75.88 # Row buffer hit rate for reads
223 system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
224 system.physmem.avgGap 34273500.39 # Average gap between requests
225 system.physmem.pageHitRate 75.88 # Row buffer hit rate, read and write combined
226 system.physmem_0.actEnergy 2963100 # Energy for activate commands per rank (pJ)
227 system.physmem_0.preEnergy 1574925 # Energy for precharge commands per rank (pJ)
228 system.physmem_0.readEnergy 14822640 # Energy for read commands per rank (pJ)
229 system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
230 system.physmem_0.refreshEnergy 157347840.000000 # Energy for refresh commands per rank (pJ)
231 system.physmem_0.actBackEnergy 56147850 # Energy for active background per rank (pJ)
232 system.physmem_0.preBackEnergy 6612480 # Energy for precharge background per rank (pJ)
233 system.physmem_0.actPowerDownEnergy 497768460 # Energy for active power-down per rank (pJ)
234 system.physmem_0.prePowerDownEnergy 192585120 # Energy for precharge power-down per rank (pJ)
235 system.physmem_0.selfRefreshEnergy 31420705950 # Energy for self refresh per rank (pJ)
236 system.physmem_0.totalEnergy 32350562865 # Total energy per rank (pJ)
237 system.physmem_0.averagePower 244.026270 # Core power per rank (mW)
238 system.physmem_0.totalIdleTime 132428576750 # Total Idle time Per DRAM Rank
239 system.physmem_0.memoryStateTime::IDLE 10716000 # Time in different power states
240 system.physmem_0.memoryStateTime::REF 66782000 # Time in different power states
241 system.physmem_0.memoryStateTime::SREF 130836450000 # Time in different power states
242 system.physmem_0.memoryStateTime::PRE_PDN 501553500 # Time in different power states
243 system.physmem_0.memoryStateTime::ACT 62926000 # Time in different power states
244 system.physmem_0.memoryStateTime::ACT_PDN 1091573000 # Time in different power states
245 system.physmem_1.actEnergy 3698520 # Energy for activate commands per rank (pJ)
246 system.physmem_1.preEnergy 1946835 # Energy for precharge commands per rank (pJ)
247 system.physmem_1.readEnergy 12794880 # Energy for read commands per rank (pJ)
248 system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
249 system.physmem_1.refreshEnergy 143211120.000000 # Energy for refresh commands per rank (pJ)
250 system.physmem_1.actBackEnergy 50027190 # Energy for active background per rank (pJ)
251 system.physmem_1.preBackEnergy 5428800 # Energy for precharge background per rank (pJ)
252 system.physmem_1.actPowerDownEnergy 512852940 # Energy for active power-down per rank (pJ)
253 system.physmem_1.prePowerDownEnergy 149734560 # Energy for precharge power-down per rank (pJ)
254 system.physmem_1.selfRefreshEnergy 31437405705 # Energy for self refresh per rank (pJ)
255 system.physmem_1.totalEnergy 32317131480 # Total energy per rank (pJ)
256 system.physmem_1.averagePower 243.774090 # Core power per rank (mW)
257 system.physmem_1.totalIdleTime 132446049750 # Total Idle time Per DRAM Rank
258 system.physmem_1.memoryStateTime::IDLE 8198000 # Time in different power states
259 system.physmem_1.memoryStateTime::REF 60730000 # Time in different power states
260 system.physmem_1.memoryStateTime::SREF 130931475750 # Time in different power states
261 system.physmem_1.memoryStateTime::PRE_PDN 389968500 # Time in different power states
262 system.physmem_1.memoryStateTime::ACT 54962000 # Time in different power states
263 system.physmem_1.memoryStateTime::ACT_PDN 1124666250 # Time in different power states
264 system.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
265 system.cpu.branchPred.lookups 49693872 # Number of BP lookups
266 system.cpu.branchPred.condPredicted 39498414 # Number of conditional branches predicted
267 system.cpu.branchPred.condIncorrect 5520434 # Number of conditional branches incorrect
268 system.cpu.branchPred.BTBLookups 24194736 # Number of BTB lookups
269 system.cpu.branchPred.BTBHits 22923274 # Number of BTB hits
270 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
271 system.cpu.branchPred.BTBHitPct 94.744882 # BTB Hit Percentage
272 system.cpu.branchPred.usedRAS 1894785 # Number of times the RAS was used to get a target.
273 system.cpu.branchPred.RASInCorrect 142 # Number of incorrect RAS predictions.
274 system.cpu.branchPred.indirectLookups 213909 # Number of indirect predictor lookups.
275 system.cpu.branchPred.indirectHits 208025 # Number of indirect target hits.
276 system.cpu.branchPred.indirectMisses 5884 # Number of indirect misses.
277 system.cpu.branchPredindirectMispredicted 40447 # Number of mispredicted indirect branches.
278 system.cpu_clk_domain.clock 500 # Clock period in ticks
279 system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
280 system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
281 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
282 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
283 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
284 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
285 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
286 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
287 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
288 system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
289 system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
290 system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
291 system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
292 system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
293 system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
294 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
295 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
296 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
297 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
298 system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
299 system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
300 system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
301 system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
302 system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
303 system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
304 system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
305 system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
306 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
307 system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
308 system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
309 system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
310 system.cpu.dtb.walker.walks 0 # Table walker walks requested
311 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
312 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
313 system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
314 system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
315 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
316 system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
317 system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
318 system.cpu.dtb.inst_hits 0 # ITB inst hits
319 system.cpu.dtb.inst_misses 0 # ITB inst misses
320 system.cpu.dtb.read_hits 0 # DTB read hits
321 system.cpu.dtb.read_misses 0 # DTB read misses
322 system.cpu.dtb.write_hits 0 # DTB write hits
323 system.cpu.dtb.write_misses 0 # DTB write misses
324 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
325 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
326 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
327 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
328 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
329 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
330 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
331 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
332 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
333 system.cpu.dtb.read_accesses 0 # DTB read accesses
334 system.cpu.dtb.write_accesses 0 # DTB write accesses
335 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
336 system.cpu.dtb.hits 0 # DTB hits
337 system.cpu.dtb.misses 0 # DTB misses
338 system.cpu.dtb.accesses 0 # DTB accesses
339 system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
340 system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
341 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
342 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
343 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
344 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
345 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
346 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
347 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
348 system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
349 system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
350 system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
351 system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
352 system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
353 system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
354 system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
355 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
356 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
357 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
358 system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
359 system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
360 system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
361 system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
362 system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
363 system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
364 system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
365 system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
366 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
367 system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
368 system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
369 system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
370 system.cpu.itb.walker.walks 0 # Table walker walks requested
371 system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
372 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
373 system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
374 system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
375 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
376 system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
377 system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
378 system.cpu.itb.inst_hits 0 # ITB inst hits
379 system.cpu.itb.inst_misses 0 # ITB inst misses
380 system.cpu.itb.read_hits 0 # DTB read hits
381 system.cpu.itb.read_misses 0 # DTB read misses
382 system.cpu.itb.write_hits 0 # DTB write hits
383 system.cpu.itb.write_misses 0 # DTB write misses
384 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
385 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
386 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
387 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
388 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
389 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
390 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
391 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
392 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
393 system.cpu.itb.read_accesses 0 # DTB read accesses
394 system.cpu.itb.write_accesses 0 # DTB write accesses
395 system.cpu.itb.inst_accesses 0 # ITB inst accesses
396 system.cpu.itb.hits 0 # DTB hits
397 system.cpu.itb.misses 0 # DTB misses
398 system.cpu.itb.accesses 0 # DTB accesses
399 system.cpu.workload.numSyscalls 400 # Number of system calls
400 system.cpu.pwrStateResidencyTicks::ON 132570000500 # Cumulative time (in ticks) in various power states
401 system.cpu.numCycles 265140001 # number of cpu cycles simulated
402 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
403 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
404 system.cpu.committedInsts 172317810 # Number of instructions committed
405 system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed
406 system.cpu.discardedOps 11517797 # Number of ops (including micro ops) which were discarded before commit
407 system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
408 system.cpu.cpi 1.538669 # CPI: cycles per instruction
409 system.cpu.ipc 0.649913 # IPC: instructions per cycle
410 system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
411 system.cpu.op_class_0::IntAlu 138988213 76.51% 76.51% # Class of committed instruction
412 system.cpu.op_class_0::IntMult 908940 0.50% 77.01% # Class of committed instruction
413 system.cpu.op_class_0::IntDiv 0 0.00% 77.01% # Class of committed instruction
414 system.cpu.op_class_0::FloatAdd 0 0.00% 77.01% # Class of committed instruction
415 system.cpu.op_class_0::FloatCmp 0 0.00% 77.01% # Class of committed instruction
416 system.cpu.op_class_0::FloatCvt 0 0.00% 77.01% # Class of committed instruction
417 system.cpu.op_class_0::FloatMult 0 0.00% 77.01% # Class of committed instruction
418 system.cpu.op_class_0::FloatMultAcc 0 0.00% 77.01% # Class of committed instruction
419 system.cpu.op_class_0::FloatDiv 0 0.00% 77.01% # Class of committed instruction
420 system.cpu.op_class_0::FloatMisc 0 0.00% 77.01% # Class of committed instruction
421 system.cpu.op_class_0::FloatSqrt 0 0.00% 77.01% # Class of committed instruction
422 system.cpu.op_class_0::SimdAdd 0 0.00% 77.01% # Class of committed instruction
423 system.cpu.op_class_0::SimdAddAcc 0 0.00% 77.01% # Class of committed instruction
424 system.cpu.op_class_0::SimdAlu 0 0.00% 77.01% # Class of committed instruction
425 system.cpu.op_class_0::SimdCmp 0 0.00% 77.01% # Class of committed instruction
426 system.cpu.op_class_0::SimdCvt 0 0.00% 77.01% # Class of committed instruction
427 system.cpu.op_class_0::SimdMisc 0 0.00% 77.01% # Class of committed instruction
428 system.cpu.op_class_0::SimdMult 0 0.00% 77.01% # Class of committed instruction
429 system.cpu.op_class_0::SimdMultAcc 0 0.00% 77.01% # Class of committed instruction
430 system.cpu.op_class_0::SimdShift 0 0.00% 77.01% # Class of committed instruction
431 system.cpu.op_class_0::SimdShiftAcc 0 0.00% 77.01% # Class of committed instruction
432 system.cpu.op_class_0::SimdSqrt 0 0.00% 77.01% # Class of committed instruction
433 system.cpu.op_class_0::SimdFloatAdd 32754 0.02% 77.03% # Class of committed instruction
434 system.cpu.op_class_0::SimdFloatAlu 0 0.00% 77.03% # Class of committed instruction
435 system.cpu.op_class_0::SimdFloatCmp 154829 0.09% 77.12% # Class of committed instruction
436 system.cpu.op_class_0::SimdFloatCvt 238880 0.13% 77.25% # Class of committed instruction
437 system.cpu.op_class_0::SimdFloatDiv 76016 0.04% 77.29% # Class of committed instruction
438 system.cpu.op_class_0::SimdFloatMisc 437591 0.24% 77.53% # Class of committed instruction
439 system.cpu.op_class_0::SimdFloatMult 200806 0.11% 77.64% # Class of committed instruction
440 system.cpu.op_class_0::SimdFloatMultAcc 71617 0.04% 77.68% # Class of committed instruction
441 system.cpu.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction
442 system.cpu.op_class_0::MemRead 27348059 15.06% 92.74% # Class of committed instruction
443 system.cpu.op_class_0::MemWrite 12498389 6.88% 99.62% # Class of committed instruction
444 system.cpu.op_class_0::FloatMemRead 548085 0.30% 99.92% # Class of committed instruction
445 system.cpu.op_class_0::FloatMemWrite 146246 0.08% 100.00% # Class of committed instruction
446 system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
447 system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
448 system.cpu.op_class_0::total 181650743 # Class of committed instruction
449 system.cpu.tickCycles 256807085 # Number of cycles that the object actually ticked
450 system.cpu.idleCycles 8332916 # Total number of cycles that the object has spent stopped
451 system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
452 system.cpu.dcache.tags.replacements 42 # number of replacements
453 system.cpu.dcache.tags.tagsinuse 1378.592517 # Cycle average of tags in use
454 system.cpu.dcache.tags.total_refs 40754461 # Total number of references to valid blocks.
455 system.cpu.dcache.tags.sampled_refs 1811 # Sample count of references to valid blocks.
456 system.cpu.dcache.tags.avg_refs 22503.843733 # Average number of references to valid blocks.
457 system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
458 system.cpu.dcache.tags.occ_blocks::cpu.data 1378.592517 # Average occupied blocks per requestor
459 system.cpu.dcache.tags.occ_percent::cpu.data 0.336570 # Average percentage of cache occupancy
460 system.cpu.dcache.tags.occ_percent::total 0.336570 # Average percentage of cache occupancy
461 system.cpu.dcache.tags.occ_task_id_blocks::1024 1769 # Occupied blocks per task id
462 system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
463 system.cpu.dcache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id
464 system.cpu.dcache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id
465 system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id
466 system.cpu.dcache.tags.age_task_id_blocks_1024::4 1359 # Occupied blocks per task id
467 system.cpu.dcache.tags.occ_task_id_percent::1024 0.431885 # Percentage of cache occupancy per task id
468 system.cpu.dcache.tags.tag_accesses 81515543 # Number of tag accesses
469 system.cpu.dcache.tags.data_accesses 81515543 # Number of data accesses
470 system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
471 system.cpu.dcache.ReadReq_hits::cpu.data 28346550 # number of ReadReq hits
472 system.cpu.dcache.ReadReq_hits::total 28346550 # number of ReadReq hits
473 system.cpu.dcache.WriteReq_hits::cpu.data 12362634 # number of WriteReq hits
474 system.cpu.dcache.WriteReq_hits::total 12362634 # number of WriteReq hits
475 system.cpu.dcache.SoftPFReq_hits::cpu.data 463 # number of SoftPFReq hits
476 system.cpu.dcache.SoftPFReq_hits::total 463 # number of SoftPFReq hits
477 system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits
478 system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits
479 system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits
480 system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits
481 system.cpu.dcache.demand_hits::cpu.data 40709184 # number of demand (read+write) hits
482 system.cpu.dcache.demand_hits::total 40709184 # number of demand (read+write) hits
483 system.cpu.dcache.overall_hits::cpu.data 40709647 # number of overall hits
484 system.cpu.dcache.overall_hits::total 40709647 # number of overall hits
485 system.cpu.dcache.ReadReq_misses::cpu.data 751 # number of ReadReq misses
486 system.cpu.dcache.ReadReq_misses::total 751 # number of ReadReq misses
487 system.cpu.dcache.WriteReq_misses::cpu.data 1653 # number of WriteReq misses
488 system.cpu.dcache.WriteReq_misses::total 1653 # number of WriteReq misses
489 system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses
490 system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses
491 system.cpu.dcache.demand_misses::cpu.data 2404 # number of demand (read+write) misses
492 system.cpu.dcache.demand_misses::total 2404 # number of demand (read+write) misses
493 system.cpu.dcache.overall_misses::cpu.data 2405 # number of overall misses
494 system.cpu.dcache.overall_misses::total 2405 # number of overall misses
495 system.cpu.dcache.ReadReq_miss_latency::cpu.data 64086500 # number of ReadReq miss cycles
496 system.cpu.dcache.ReadReq_miss_latency::total 64086500 # number of ReadReq miss cycles
497 system.cpu.dcache.WriteReq_miss_latency::cpu.data 146233500 # number of WriteReq miss cycles
498 system.cpu.dcache.WriteReq_miss_latency::total 146233500 # number of WriteReq miss cycles
499 system.cpu.dcache.demand_miss_latency::cpu.data 210320000 # number of demand (read+write) miss cycles
500 system.cpu.dcache.demand_miss_latency::total 210320000 # number of demand (read+write) miss cycles
501 system.cpu.dcache.overall_miss_latency::cpu.data 210320000 # number of overall miss cycles
502 system.cpu.dcache.overall_miss_latency::total 210320000 # number of overall miss cycles
503 system.cpu.dcache.ReadReq_accesses::cpu.data 28347301 # number of ReadReq accesses(hits+misses)
504 system.cpu.dcache.ReadReq_accesses::total 28347301 # number of ReadReq accesses(hits+misses)
505 system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
506 system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
507 system.cpu.dcache.SoftPFReq_accesses::cpu.data 464 # number of SoftPFReq accesses(hits+misses)
508 system.cpu.dcache.SoftPFReq_accesses::total 464 # number of SoftPFReq accesses(hits+misses)
509 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses)
510 system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses)
511 system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses)
512 system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses)
513 system.cpu.dcache.demand_accesses::cpu.data 40711588 # number of demand (read+write) accesses
514 system.cpu.dcache.demand_accesses::total 40711588 # number of demand (read+write) accesses
515 system.cpu.dcache.overall_accesses::cpu.data 40712052 # number of overall (read+write) accesses
516 system.cpu.dcache.overall_accesses::total 40712052 # number of overall (read+write) accesses
517 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000026 # miss rate for ReadReq accesses
518 system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses
519 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000134 # miss rate for WriteReq accesses
520 system.cpu.dcache.WriteReq_miss_rate::total 0.000134 # miss rate for WriteReq accesses
521 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002155 # miss rate for SoftPFReq accesses
522 system.cpu.dcache.SoftPFReq_miss_rate::total 0.002155 # miss rate for SoftPFReq accesses
523 system.cpu.dcache.demand_miss_rate::cpu.data 0.000059 # miss rate for demand accesses
524 system.cpu.dcache.demand_miss_rate::total 0.000059 # miss rate for demand accesses
525 system.cpu.dcache.overall_miss_rate::cpu.data 0.000059 # miss rate for overall accesses
526 system.cpu.dcache.overall_miss_rate::total 0.000059 # miss rate for overall accesses
527 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 85334.886818 # average ReadReq miss latency
528 system.cpu.dcache.ReadReq_avg_miss_latency::total 85334.886818 # average ReadReq miss latency
529 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 88465.517241 # average WriteReq miss latency
530 system.cpu.dcache.WriteReq_avg_miss_latency::total 88465.517241 # average WriteReq miss latency
531 system.cpu.dcache.demand_avg_miss_latency::cpu.data 87487.520799 # average overall miss latency
532 system.cpu.dcache.demand_avg_miss_latency::total 87487.520799 # average overall miss latency
533 system.cpu.dcache.overall_avg_miss_latency::cpu.data 87451.143451 # average overall miss latency
534 system.cpu.dcache.overall_avg_miss_latency::total 87451.143451 # average overall miss latency
535 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
536 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
537 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
538 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
539 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
540 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
541 system.cpu.dcache.writebacks::writebacks 16 # number of writebacks
542 system.cpu.dcache.writebacks::total 16 # number of writebacks
543 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits
544 system.cpu.dcache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits
545 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 554 # number of WriteReq MSHR hits
546 system.cpu.dcache.WriteReq_mshr_hits::total 554 # number of WriteReq MSHR hits
547 system.cpu.dcache.demand_mshr_hits::cpu.data 594 # number of demand (read+write) MSHR hits
548 system.cpu.dcache.demand_mshr_hits::total 594 # number of demand (read+write) MSHR hits
549 system.cpu.dcache.overall_mshr_hits::cpu.data 594 # number of overall MSHR hits
550 system.cpu.dcache.overall_mshr_hits::total 594 # number of overall MSHR hits
551 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711 # number of ReadReq MSHR misses
552 system.cpu.dcache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses
553 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1099 # number of WriteReq MSHR misses
554 system.cpu.dcache.WriteReq_mshr_misses::total 1099 # number of WriteReq MSHR misses
555 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
556 system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
557 system.cpu.dcache.demand_mshr_misses::cpu.data 1810 # number of demand (read+write) MSHR misses
558 system.cpu.dcache.demand_mshr_misses::total 1810 # number of demand (read+write) MSHR misses
559 system.cpu.dcache.overall_mshr_misses::cpu.data 1811 # number of overall MSHR misses
560 system.cpu.dcache.overall_mshr_misses::total 1811 # number of overall MSHR misses
561 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 60392000 # number of ReadReq MSHR miss cycles
562 system.cpu.dcache.ReadReq_mshr_miss_latency::total 60392000 # number of ReadReq MSHR miss cycles
563 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 99618500 # number of WriteReq MSHR miss cycles
564 system.cpu.dcache.WriteReq_mshr_miss_latency::total 99618500 # number of WriteReq MSHR miss cycles
565 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 77000 # number of SoftPFReq MSHR miss cycles
566 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 77000 # number of SoftPFReq MSHR miss cycles
567 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 160010500 # number of demand (read+write) MSHR miss cycles
568 system.cpu.dcache.demand_mshr_miss_latency::total 160010500 # number of demand (read+write) MSHR miss cycles
569 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 160087500 # number of overall MSHR miss cycles
570 system.cpu.dcache.overall_mshr_miss_latency::total 160087500 # number of overall MSHR miss cycles
571 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses
572 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses
573 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses
574 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses
575 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002155 # mshr miss rate for SoftPFReq accesses
576 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002155 # mshr miss rate for SoftPFReq accesses
577 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for demand accesses
578 system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses
579 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses
580 system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses
581 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84939.521800 # average ReadReq mshr miss latency
582 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84939.521800 # average ReadReq mshr miss latency
583 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 90644.676979 # average WriteReq mshr miss latency
584 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 90644.676979 # average WriteReq mshr miss latency
585 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 77000 # average SoftPFReq mshr miss latency
586 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 77000 # average SoftPFReq mshr miss latency
587 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 88403.591160 # average overall mshr miss latency
588 system.cpu.dcache.demand_avg_mshr_miss_latency::total 88403.591160 # average overall mshr miss latency
589 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 88397.294313 # average overall mshr miss latency
590 system.cpu.dcache.overall_avg_mshr_miss_latency::total 88397.294313 # average overall mshr miss latency
591 system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
592 system.cpu.icache.tags.replacements 2861 # number of replacements
593 system.cpu.icache.tags.tagsinuse 1424.892665 # Cycle average of tags in use
594 system.cpu.icache.tags.total_refs 70991309 # Total number of references to valid blocks.
595 system.cpu.icache.tags.sampled_refs 4660 # Sample count of references to valid blocks.
596 system.cpu.icache.tags.avg_refs 15234.186481 # Average number of references to valid blocks.
597 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
598 system.cpu.icache.tags.occ_blocks::cpu.inst 1424.892665 # Average occupied blocks per requestor
599 system.cpu.icache.tags.occ_percent::cpu.inst 0.695748 # Average percentage of cache occupancy
600 system.cpu.icache.tags.occ_percent::total 0.695748 # Average percentage of cache occupancy
601 system.cpu.icache.tags.occ_task_id_blocks::1024 1799 # Occupied blocks per task id
602 system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
603 system.cpu.icache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id
604 system.cpu.icache.tags.age_task_id_blocks_1024::2 490 # Occupied blocks per task id
605 system.cpu.icache.tags.age_task_id_blocks_1024::3 131 # Occupied blocks per task id
606 system.cpu.icache.tags.age_task_id_blocks_1024::4 1069 # Occupied blocks per task id
607 system.cpu.icache.tags.occ_task_id_percent::1024 0.878418 # Percentage of cache occupancy per task id
608 system.cpu.icache.tags.tag_accesses 141996600 # Number of tag accesses
609 system.cpu.icache.tags.data_accesses 141996600 # Number of data accesses
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611 system.cpu.icache.ReadReq_hits::cpu.inst 70991309 # number of ReadReq hits
612 system.cpu.icache.ReadReq_hits::total 70991309 # number of ReadReq hits
613 system.cpu.icache.demand_hits::cpu.inst 70991309 # number of demand (read+write) hits
614 system.cpu.icache.demand_hits::total 70991309 # number of demand (read+write) hits
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616 system.cpu.icache.overall_hits::total 70991309 # number of overall hits
617 system.cpu.icache.ReadReq_misses::cpu.inst 4661 # number of ReadReq misses
618 system.cpu.icache.ReadReq_misses::total 4661 # number of ReadReq misses
619 system.cpu.icache.demand_misses::cpu.inst 4661 # number of demand (read+write) misses
620 system.cpu.icache.demand_misses::total 4661 # number of demand (read+write) misses
621 system.cpu.icache.overall_misses::cpu.inst 4661 # number of overall misses
622 system.cpu.icache.overall_misses::total 4661 # number of overall misses
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624 system.cpu.icache.ReadReq_miss_latency::total 236001500 # number of ReadReq miss cycles
625 system.cpu.icache.demand_miss_latency::cpu.inst 236001500 # number of demand (read+write) miss cycles
626 system.cpu.icache.demand_miss_latency::total 236001500 # number of demand (read+write) miss cycles
627 system.cpu.icache.overall_miss_latency::cpu.inst 236001500 # number of overall miss cycles
628 system.cpu.icache.overall_miss_latency::total 236001500 # number of overall miss cycles
629 system.cpu.icache.ReadReq_accesses::cpu.inst 70995970 # number of ReadReq accesses(hits+misses)
630 system.cpu.icache.ReadReq_accesses::total 70995970 # number of ReadReq accesses(hits+misses)
631 system.cpu.icache.demand_accesses::cpu.inst 70995970 # number of demand (read+write) accesses
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634 system.cpu.icache.overall_accesses::total 70995970 # number of overall (read+write) accesses
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636 system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses
637 system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses
638 system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses
639 system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses
640 system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses
641 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50633.233212 # average ReadReq miss latency
642 system.cpu.icache.ReadReq_avg_miss_latency::total 50633.233212 # average ReadReq miss latency
643 system.cpu.icache.demand_avg_miss_latency::cpu.inst 50633.233212 # average overall miss latency
644 system.cpu.icache.demand_avg_miss_latency::total 50633.233212 # average overall miss latency
645 system.cpu.icache.overall_avg_miss_latency::cpu.inst 50633.233212 # average overall miss latency
646 system.cpu.icache.overall_avg_miss_latency::total 50633.233212 # average overall miss latency
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648 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
649 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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651 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
652 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
653 system.cpu.icache.writebacks::writebacks 2861 # number of writebacks
654 system.cpu.icache.writebacks::total 2861 # number of writebacks
655 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4661 # number of ReadReq MSHR misses
656 system.cpu.icache.ReadReq_mshr_misses::total 4661 # number of ReadReq MSHR misses
657 system.cpu.icache.demand_mshr_misses::cpu.inst 4661 # number of demand (read+write) MSHR misses
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659 system.cpu.icache.overall_mshr_misses::cpu.inst 4661 # number of overall MSHR misses
660 system.cpu.icache.overall_mshr_misses::total 4661 # number of overall MSHR misses
661 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 231341500 # number of ReadReq MSHR miss cycles
662 system.cpu.icache.ReadReq_mshr_miss_latency::total 231341500 # number of ReadReq MSHR miss cycles
663 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 231341500 # number of demand (read+write) MSHR miss cycles
664 system.cpu.icache.demand_mshr_miss_latency::total 231341500 # number of demand (read+write) MSHR miss cycles
665 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 231341500 # number of overall MSHR miss cycles
666 system.cpu.icache.overall_mshr_miss_latency::total 231341500 # number of overall MSHR miss cycles
667 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses
668 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses
669 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses
670 system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses
671 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses
672 system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses
673 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49633.447758 # average ReadReq mshr miss latency
674 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49633.447758 # average ReadReq mshr miss latency
675 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49633.447758 # average overall mshr miss latency
676 system.cpu.icache.demand_avg_mshr_miss_latency::total 49633.447758 # average overall mshr miss latency
677 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49633.447758 # average overall mshr miss latency
678 system.cpu.icache.overall_avg_mshr_miss_latency::total 49633.447758 # average overall mshr miss latency
679 system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
680 system.cpu.l2cache.tags.replacements 0 # number of replacements
681 system.cpu.l2cache.tags.tagsinuse 2835.344855 # Cycle average of tags in use
682 system.cpu.l2cache.tags.total_refs 5154 # Total number of references to valid blocks.
683 system.cpu.l2cache.tags.sampled_refs 3868 # Sample count of references to valid blocks.
684 system.cpu.l2cache.tags.avg_refs 1.332472 # Average number of references to valid blocks.
685 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
686 system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.641960 # Average occupied blocks per requestor
687 system.cpu.l2cache.tags.occ_blocks::cpu.data 1327.702895 # Average occupied blocks per requestor
688 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046010 # Average percentage of cache occupancy
689 system.cpu.l2cache.tags.occ_percent::cpu.data 0.040518 # Average percentage of cache occupancy
690 system.cpu.l2cache.tags.occ_percent::total 0.086528 # Average percentage of cache occupancy
691 system.cpu.l2cache.tags.occ_task_id_blocks::1024 3868 # Occupied blocks per task id
692 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id
693 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id
694 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 534 # Occupied blocks per task id
695 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 367 # Occupied blocks per task id
696 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2841 # Occupied blocks per task id
697 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.118042 # Percentage of cache occupancy per task id
698 system.cpu.l2cache.tags.tag_accesses 76180 # Number of tag accesses
699 system.cpu.l2cache.tags.data_accesses 76180 # Number of data accesses
700 system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
701 system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits
702 system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits
703 system.cpu.l2cache.WritebackClean_hits::writebacks 2531 # number of WritebackClean hits
704 system.cpu.l2cache.WritebackClean_hits::total 2531 # number of WritebackClean hits
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706 system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits
707 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2499 # number of ReadCleanReq hits
708 system.cpu.l2cache.ReadCleanReq_hits::total 2499 # number of ReadCleanReq hits
709 system.cpu.l2cache.ReadSharedReq_hits::cpu.data 80 # number of ReadSharedReq hits
710 system.cpu.l2cache.ReadSharedReq_hits::total 80 # number of ReadSharedReq hits
711 system.cpu.l2cache.demand_hits::cpu.inst 2499 # number of demand (read+write) hits
712 system.cpu.l2cache.demand_hits::cpu.data 88 # number of demand (read+write) hits
713 system.cpu.l2cache.demand_hits::total 2587 # number of demand (read+write) hits
714 system.cpu.l2cache.overall_hits::cpu.inst 2499 # number of overall hits
715 system.cpu.l2cache.overall_hits::cpu.data 88 # number of overall hits
716 system.cpu.l2cache.overall_hits::total 2587 # number of overall hits
717 system.cpu.l2cache.ReadExReq_misses::cpu.data 1091 # number of ReadExReq misses
718 system.cpu.l2cache.ReadExReq_misses::total 1091 # number of ReadExReq misses
719 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2162 # number of ReadCleanReq misses
720 system.cpu.l2cache.ReadCleanReq_misses::total 2162 # number of ReadCleanReq misses
721 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 632 # number of ReadSharedReq misses
722 system.cpu.l2cache.ReadSharedReq_misses::total 632 # number of ReadSharedReq misses
723 system.cpu.l2cache.demand_misses::cpu.inst 2162 # number of demand (read+write) misses
724 system.cpu.l2cache.demand_misses::cpu.data 1723 # number of demand (read+write) misses
725 system.cpu.l2cache.demand_misses::total 3885 # number of demand (read+write) misses
726 system.cpu.l2cache.overall_misses::cpu.inst 2162 # number of overall misses
727 system.cpu.l2cache.overall_misses::cpu.data 1723 # number of overall misses
728 system.cpu.l2cache.overall_misses::total 3885 # number of overall misses
729 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 97884500 # number of ReadExReq miss cycles
730 system.cpu.l2cache.ReadExReq_miss_latency::total 97884500 # number of ReadExReq miss cycles
731 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 197728500 # number of ReadCleanReq miss cycles
732 system.cpu.l2cache.ReadCleanReq_miss_latency::total 197728500 # number of ReadCleanReq miss cycles
733 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 58476500 # number of ReadSharedReq miss cycles
734 system.cpu.l2cache.ReadSharedReq_miss_latency::total 58476500 # number of ReadSharedReq miss cycles
735 system.cpu.l2cache.demand_miss_latency::cpu.inst 197728500 # number of demand (read+write) miss cycles
736 system.cpu.l2cache.demand_miss_latency::cpu.data 156361000 # number of demand (read+write) miss cycles
737 system.cpu.l2cache.demand_miss_latency::total 354089500 # number of demand (read+write) miss cycles
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739 system.cpu.l2cache.overall_miss_latency::cpu.data 156361000 # number of overall miss cycles
740 system.cpu.l2cache.overall_miss_latency::total 354089500 # number of overall miss cycles
741 system.cpu.l2cache.WritebackDirty_accesses::writebacks 16 # number of WritebackDirty accesses(hits+misses)
742 system.cpu.l2cache.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses)
743 system.cpu.l2cache.WritebackClean_accesses::writebacks 2531 # number of WritebackClean accesses(hits+misses)
744 system.cpu.l2cache.WritebackClean_accesses::total 2531 # number of WritebackClean accesses(hits+misses)
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746 system.cpu.l2cache.ReadExReq_accesses::total 1099 # number of ReadExReq accesses(hits+misses)
747 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4661 # number of ReadCleanReq accesses(hits+misses)
748 system.cpu.l2cache.ReadCleanReq_accesses::total 4661 # number of ReadCleanReq accesses(hits+misses)
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758 system.cpu.l2cache.ReadExReq_miss_rate::total 0.992721 # miss rate for ReadExReq accesses
759 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.463849 # miss rate for ReadCleanReq accesses
760 system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.463849 # miss rate for ReadCleanReq accesses
761 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.887640 # miss rate for ReadSharedReq accesses
762 system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.887640 # miss rate for ReadSharedReq accesses
763 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.463849 # miss rate for demand accesses
764 system.cpu.l2cache.demand_miss_rate::cpu.data 0.951408 # miss rate for demand accesses
765 system.cpu.l2cache.demand_miss_rate::total 0.600278 # miss rate for demand accesses
766 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.463849 # miss rate for overall accesses
767 system.cpu.l2cache.overall_miss_rate::cpu.data 0.951408 # miss rate for overall accesses
768 system.cpu.l2cache.overall_miss_rate::total 0.600278 # miss rate for overall accesses
769 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89719.981668 # average ReadExReq miss latency
770 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89719.981668 # average ReadExReq miss latency
771 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 91456.290472 # average ReadCleanReq miss latency
772 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 91456.290472 # average ReadCleanReq miss latency
773 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 92526.107595 # average ReadSharedReq miss latency
774 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 92526.107595 # average ReadSharedReq miss latency
775 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 91456.290472 # average overall miss latency
776 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 90749.274521 # average overall miss latency
777 system.cpu.l2cache.demand_avg_miss_latency::total 91142.728443 # average overall miss latency
778 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 91456.290472 # average overall miss latency
779 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 90749.274521 # average overall miss latency
780 system.cpu.l2cache.overall_avg_miss_latency::total 91142.728443 # average overall miss latency
781 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
782 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
783 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
784 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
785 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
786 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
787 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
788 system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
789 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 15 # number of ReadSharedReq MSHR hits
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791 system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
792 system.cpu.l2cache.demand_mshr_hits::cpu.data 15 # number of demand (read+write) MSHR hits
793 system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits
794 system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
795 system.cpu.l2cache.overall_mshr_hits::cpu.data 15 # number of overall MSHR hits
796 system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits
797 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1091 # number of ReadExReq MSHR misses
798 system.cpu.l2cache.ReadExReq_mshr_misses::total 1091 # number of ReadExReq MSHR misses
799 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2161 # number of ReadCleanReq MSHR misses
800 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2161 # number of ReadCleanReq MSHR misses
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822 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992721 # mshr miss rate for ReadExReq accesses
823 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.463634 # mshr miss rate for ReadCleanReq accesses
824 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.463634 # mshr miss rate for ReadCleanReq accesses
825 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.866573 # mshr miss rate for ReadSharedReq accesses
826 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.866573 # mshr miss rate for ReadSharedReq accesses
827 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.463634 # mshr miss rate for demand accesses
828 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for demand accesses
829 system.cpu.l2cache.demand_mshr_miss_rate::total 0.597806 # mshr miss rate for demand accesses
830 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463634 # mshr miss rate for overall accesses
831 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for overall accesses
832 system.cpu.l2cache.overall_mshr_miss_rate::total 0.597806 # mshr miss rate for overall accesses
833 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79719.981668 # average ReadExReq mshr miss latency
834 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79719.981668 # average ReadExReq mshr miss latency
835 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 81469.227210 # average ReadCleanReq mshr miss latency
836 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 81469.227210 # average ReadCleanReq mshr miss latency
837 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82073.743922 # average ReadSharedReq mshr miss latency
838 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 82073.743922 # average ReadSharedReq mshr miss latency
839 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 81469.227210 # average overall mshr miss latency
840 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80570.257611 # average overall mshr miss latency
841 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81072.370121 # average overall mshr miss latency
842 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 81469.227210 # average overall mshr miss latency
843 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80570.257611 # average overall mshr miss latency
844 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81072.370121 # average overall mshr miss latency
845 system.cpu.toL2Bus.snoop_filter.tot_requests 9375 # Total number of requests made to the snoop filter.
846 system.cpu.toL2Bus.snoop_filter.hit_single_requests 3038 # Number of requests hitting in the snoop filter with a single holder of the requested data.
847 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 336 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
848 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
849 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
850 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
851 system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
852 system.cpu.toL2Bus.trans_dist::ReadResp 5372 # Transaction distribution
853 system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution
854 system.cpu.toL2Bus.trans_dist::WritebackClean 2861 # Transaction distribution
855 system.cpu.toL2Bus.trans_dist::CleanEvict 26 # Transaction distribution
856 system.cpu.toL2Bus.trans_dist::ReadExReq 1099 # Transaction distribution
857 system.cpu.toL2Bus.trans_dist::ReadExResp 1099 # Transaction distribution
858 system.cpu.toL2Bus.trans_dist::ReadCleanReq 4661 # Transaction distribution
859 system.cpu.toL2Bus.trans_dist::ReadSharedReq 712 # Transaction distribution
860 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12182 # Packet count per connected master and slave (bytes)
861 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3664 # Packet count per connected master and slave (bytes)
862 system.cpu.toL2Bus.pkt_count::total 15846 # Packet count per connected master and slave (bytes)
863 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 481344 # Cumulative packet size per connected master and slave (bytes)
864 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116928 # Cumulative packet size per connected master and slave (bytes)
865 system.cpu.toL2Bus.pkt_size::total 598272 # Cumulative packet size per connected master and slave (bytes)
866 system.cpu.toL2Bus.snoops 0 # Total snoops (count)
867 system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
868 system.cpu.toL2Bus.snoop_fanout::samples 6472 # Request fanout histogram
869 system.cpu.toL2Bus.snoop_fanout::mean 0.072775 # Request fanout histogram
870 system.cpu.toL2Bus.snoop_fanout::stdev 0.259787 # Request fanout histogram
871 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
872 system.cpu.toL2Bus.snoop_fanout::0 6001 92.72% 92.72% # Request fanout histogram
873 system.cpu.toL2Bus.snoop_fanout::1 471 7.28% 100.00% # Request fanout histogram
874 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
875 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
876 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
877 system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
878 system.cpu.toL2Bus.snoop_fanout::total 6472 # Request fanout histogram
879 system.cpu.toL2Bus.reqLayer0.occupancy 7564500 # Layer occupancy (ticks)
880 system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
881 system.cpu.toL2Bus.respLayer0.occupancy 6990499 # Layer occupancy (ticks)
882 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
883 system.cpu.toL2Bus.respLayer1.occupancy 2723985 # Layer occupancy (ticks)
884 system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
885 system.membus.snoop_filter.tot_requests 3868 # Total number of requests made to the snoop filter.
886 system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
887 system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
888 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
889 system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
890 system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
891 system.membus.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
892 system.membus.trans_dist::ReadResp 2777 # Transaction distribution
893 system.membus.trans_dist::ReadExReq 1091 # Transaction distribution
894 system.membus.trans_dist::ReadExResp 1091 # Transaction distribution
895 system.membus.trans_dist::ReadSharedReq 2777 # Transaction distribution
896 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7736 # Packet count per connected master and slave (bytes)
897 system.membus.pkt_count::total 7736 # Packet count per connected master and slave (bytes)
898 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247552 # Cumulative packet size per connected master and slave (bytes)
899 system.membus.pkt_size::total 247552 # Cumulative packet size per connected master and slave (bytes)
900 system.membus.snoops 0 # Total snoops (count)
901 system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
902 system.membus.snoop_fanout::samples 3868 # Request fanout histogram
903 system.membus.snoop_fanout::mean 0 # Request fanout histogram
904 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
905 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
906 system.membus.snoop_fanout::0 3868 100.00% 100.00% # Request fanout histogram
907 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
908 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
909 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
910 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
911 system.membus.snoop_fanout::total 3868 # Request fanout histogram
912 system.membus.reqLayer0.occupancy 4525000 # Layer occupancy (ticks)
913 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
914 system.membus.respLayer1.occupancy 20564500 # Layer occupancy (ticks)
915 system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
917 ---------- End Simulation Statistics ----------
projects / gem5.git / blob