2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.130773 # Number of seconds simulated
4 sim_ticks 130772642500 # Number of ticks simulated
5 final_tick 130772642500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 239563 # Simulator instruction rate (inst/s)
8 host_op_rate 252538 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 181805529 # Simulator tick rate (ticks/s)
10 host_mem_usage 322304 # Number of bytes of host memory used
11 host_seconds 719.30 # Real time elapsed on the host
12 sim_insts 172317810 # Number of instructions simulated
13 sim_ops 181650743 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 138112 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory
18 system.physmem.bytes_read::total 247424 # Number of bytes read from this memory
19 system.physmem.bytes_inst_read::cpu.inst 138112 # Number of instructions bytes read from this memory
20 system.physmem.bytes_inst_read::total 138112 # Number of instructions bytes read from this memory
21 system.physmem.num_reads::cpu.inst 2158 # Number of read requests responded to by this memory
22 system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory
23 system.physmem.num_reads::total 3866 # Number of read requests responded to by this memory
24 system.physmem.bw_read::cpu.inst 1056123 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_read::cpu.data 835893 # Total read bandwidth from this memory (bytes/s)
26 system.physmem.bw_read::total 1892017 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_inst_read::cpu.inst 1056123 # Instruction read bandwidth from this memory (bytes/s)
28 system.physmem.bw_inst_read::total 1056123 # Instruction read bandwidth from this memory (bytes/s)
29 system.physmem.bw_total::cpu.inst 1056123 # Total bandwidth to/from this memory (bytes/s)
30 system.physmem.bw_total::cpu.data 835893 # Total bandwidth to/from this memory (bytes/s)
31 system.physmem.bw_total::total 1892017 # Total bandwidth to/from this memory (bytes/s)
32 system.physmem.readReqs 3866 # Number of read requests accepted
33 system.physmem.writeReqs 0 # Number of write requests accepted
34 system.physmem.readBursts 3866 # Number of DRAM read bursts, including those serviced by the write queue
35 system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
36 system.physmem.bytesReadDRAM 247424 # Total number of bytes read from DRAM
37 system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
38 system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
39 system.physmem.bytesReadSys 247424 # Total read bytes from the system interface side
40 system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
41 system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
42 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
43 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
44 system.physmem.perBankRdBursts::0 305 # Per bank write bursts
45 system.physmem.perBankRdBursts::1 217 # Per bank write bursts
46 system.physmem.perBankRdBursts::2 135 # Per bank write bursts
47 system.physmem.perBankRdBursts::3 313 # Per bank write bursts
48 system.physmem.perBankRdBursts::4 306 # Per bank write bursts
49 system.physmem.perBankRdBursts::5 305 # Per bank write bursts
50 system.physmem.perBankRdBursts::6 273 # Per bank write bursts
51 system.physmem.perBankRdBursts::7 222 # Per bank write bursts
52 system.physmem.perBankRdBursts::8 248 # Per bank write bursts
53 system.physmem.perBankRdBursts::9 218 # Per bank write bursts
54 system.physmem.perBankRdBursts::10 295 # Per bank write bursts
55 system.physmem.perBankRdBursts::11 200 # Per bank write bursts
56 system.physmem.perBankRdBursts::12 183 # Per bank write bursts
57 system.physmem.perBankRdBursts::13 218 # Per bank write bursts
58 system.physmem.perBankRdBursts::14 224 # Per bank write bursts
59 system.physmem.perBankRdBursts::15 204 # Per bank write bursts
60 system.physmem.perBankWrBursts::0 0 # Per bank write bursts
61 system.physmem.perBankWrBursts::1 0 # Per bank write bursts
62 system.physmem.perBankWrBursts::2 0 # Per bank write bursts
63 system.physmem.perBankWrBursts::3 0 # Per bank write bursts
64 system.physmem.perBankWrBursts::4 0 # Per bank write bursts
65 system.physmem.perBankWrBursts::5 0 # Per bank write bursts
66 system.physmem.perBankWrBursts::6 0 # Per bank write bursts
67 system.physmem.perBankWrBursts::7 0 # Per bank write bursts
68 system.physmem.perBankWrBursts::8 0 # Per bank write bursts
69 system.physmem.perBankWrBursts::9 0 # Per bank write bursts
70 system.physmem.perBankWrBursts::10 0 # Per bank write bursts
71 system.physmem.perBankWrBursts::11 0 # Per bank write bursts
72 system.physmem.perBankWrBursts::12 0 # Per bank write bursts
73 system.physmem.perBankWrBursts::13 0 # Per bank write bursts
74 system.physmem.perBankWrBursts::14 0 # Per bank write bursts
75 system.physmem.perBankWrBursts::15 0 # Per bank write bursts
76 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
77 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
78 system.physmem.totGap 130772548000 # Total gap between requests
79 system.physmem.readPktSize::0 0 # Read request sizes (log2)
80 system.physmem.readPktSize::1 0 # Read request sizes (log2)
81 system.physmem.readPktSize::2 0 # Read request sizes (log2)
82 system.physmem.readPktSize::3 0 # Read request sizes (log2)
83 system.physmem.readPktSize::4 0 # Read request sizes (log2)
84 system.physmem.readPktSize::5 0 # Read request sizes (log2)
85 system.physmem.readPktSize::6 3866 # Read request sizes (log2)
86 system.physmem.writePktSize::0 0 # Write request sizes (log2)
87 system.physmem.writePktSize::1 0 # Write request sizes (log2)
88 system.physmem.writePktSize::2 0 # Write request sizes (log2)
89 system.physmem.writePktSize::3 0 # Write request sizes (log2)
90 system.physmem.writePktSize::4 0 # Write request sizes (log2)
91 system.physmem.writePktSize::5 0 # Write request sizes (log2)
92 system.physmem.writePktSize::6 0 # Write request sizes (log2)
93 system.physmem.rdQLenPdf::0 3617 # What read queue length does an incoming req see
94 system.physmem.rdQLenPdf::1 237 # What read queue length does an incoming req see
95 system.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see
96 system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
97 system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
98 system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
99 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
100 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
125 system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
126 system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
127 system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
128 system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
129 system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
130 system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
131 system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
132 system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
189 system.physmem.bytesPerActivate::samples 905 # Bytes accessed per row activation
190 system.physmem.bytesPerActivate::mean 271.628729 # Bytes accessed per row activation
191 system.physmem.bytesPerActivate::gmean 179.806384 # Bytes accessed per row activation
192 system.physmem.bytesPerActivate::stdev 277.022098 # Bytes accessed per row activation
193 system.physmem.bytesPerActivate::0-127 259 28.62% 28.62% # Bytes accessed per row activation
194 system.physmem.bytesPerActivate::128-255 352 38.90% 67.51% # Bytes accessed per row activation
195 system.physmem.bytesPerActivate::256-383 86 9.50% 77.02% # Bytes accessed per row activation
196 system.physmem.bytesPerActivate::384-511 59 6.52% 83.54% # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::512-639 34 3.76% 87.29% # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::640-767 21 2.32% 89.61% # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::768-895 17 1.88% 91.49% # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::896-1023 17 1.88% 93.37% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::1024-1151 60 6.63% 100.00% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::total 905 # Bytes accessed per row activation
203 system.physmem.totQLat 27654500 # Total ticks spent queuing
204 system.physmem.totMemAccLat 100142000 # Total ticks spent from burst creation until serviced by the DRAM
205 system.physmem.totBusLat 19330000 # Total ticks spent in databus transfers
206 system.physmem.avgQLat 7153.26 # Average queueing delay per DRAM burst
207 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
208 system.physmem.avgMemAccLat 25903.26 # Average memory access latency per DRAM burst
209 system.physmem.avgRdBW 1.89 # Average DRAM read bandwidth in MiByte/s
210 system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
211 system.physmem.avgRdBWSys 1.89 # Average system read bandwidth in MiByte/s
212 system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
213 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
214 system.physmem.busUtil 0.01 # Data bus utilization in percentage
215 system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
216 system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
217 system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
218 system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
219 system.physmem.readRowHits 2957 # Number of row buffer hits during reads
220 system.physmem.writeRowHits 0 # Number of row buffer hits during writes
221 system.physmem.readRowHitRate 76.49 # Row buffer hit rate for reads
222 system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
223 system.physmem.avgGap 33826318.68 # Average gap between requests
224 system.physmem.pageHitRate 76.49 # Row buffer hit rate, read and write combined
225 system.physmem_0.actEnergy 3099600 # Energy for activate commands per rank (pJ)
226 system.physmem_0.preEnergy 1691250 # Energy for precharge commands per rank (pJ)
227 system.physmem_0.readEnergy 16161600 # Energy for read commands per rank (pJ)
228 system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
229 system.physmem_0.refreshEnergy 8541265200 # Energy for refresh commands per rank (pJ)
230 system.physmem_0.actBackEnergy 3568631490 # Energy for active background per rank (pJ)
231 system.physmem_0.preBackEnergy 75331810500 # Energy for precharge background per rank (pJ)
232 system.physmem_0.totalEnergy 87462659640 # Total energy per rank (pJ)
233 system.physmem_0.averagePower 668.826558 # Core power per rank (mW)
234 system.physmem_0.memoryStateTime::IDLE 125319167750 # Time in different power states
235 system.physmem_0.memoryStateTime::REF 4366700000 # Time in different power states
236 system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
237 system.physmem_0.memoryStateTime::ACT 1084461000 # Time in different power states
238 system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
239 system.physmem_1.actEnergy 3727080 # Energy for activate commands per rank (pJ)
240 system.physmem_1.preEnergy 2033625 # Energy for precharge commands per rank (pJ)
241 system.physmem_1.readEnergy 13782600 # Energy for read commands per rank (pJ)
242 system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
243 system.physmem_1.refreshEnergy 8541265200 # Energy for refresh commands per rank (pJ)
244 system.physmem_1.actBackEnergy 3564306900 # Energy for active background per rank (pJ)
245 system.physmem_1.preBackEnergy 75335612250 # Energy for precharge background per rank (pJ)
246 system.physmem_1.totalEnergy 87460727655 # Total energy per rank (pJ)
247 system.physmem_1.averagePower 668.811714 # Core power per rank (mW)
248 system.physmem_1.memoryStateTime::IDLE 125325942500 # Time in different power states
249 system.physmem_1.memoryStateTime::REF 4366700000 # Time in different power states
250 system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
251 system.physmem_1.memoryStateTime::ACT 1077991500 # Time in different power states
252 system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
253 system.cpu.branchPred.lookups 49732170 # Number of BP lookups
254 system.cpu.branchPred.condPredicted 39495980 # Number of conditional branches predicted
255 system.cpu.branchPred.condIncorrect 5592247 # Number of conditional branches incorrect
256 system.cpu.branchPred.BTBLookups 24154061 # Number of BTB lookups
257 system.cpu.branchPred.BTBHits 23128262 # Number of BTB hits
258 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
259 system.cpu.branchPred.BTBHitPct 95.753099 # BTB Hit Percentage
260 system.cpu.branchPred.usedRAS 1888632 # Number of times the RAS was used to get a target.
261 system.cpu.branchPred.RASInCorrect 142 # Number of incorrect RAS predictions.
262 system.cpu_clk_domain.clock 500 # Clock period in ticks
263 system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
264 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
265 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
266 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
267 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
268 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
269 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
270 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
271 system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
272 system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
273 system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
274 system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
275 system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
276 system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
277 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
278 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
279 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
280 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
281 system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
282 system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
283 system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
284 system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
285 system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
286 system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
287 system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
288 system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
289 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
290 system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
291 system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
292 system.cpu.dtb.walker.walks 0 # Table walker walks requested
293 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
294 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
295 system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
296 system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
297 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
298 system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
299 system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
300 system.cpu.dtb.inst_hits 0 # ITB inst hits
301 system.cpu.dtb.inst_misses 0 # ITB inst misses
302 system.cpu.dtb.read_hits 0 # DTB read hits
303 system.cpu.dtb.read_misses 0 # DTB read misses
304 system.cpu.dtb.write_hits 0 # DTB write hits
305 system.cpu.dtb.write_misses 0 # DTB write misses
306 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
307 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
308 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
309 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
310 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
311 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
312 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
313 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
314 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
315 system.cpu.dtb.read_accesses 0 # DTB read accesses
316 system.cpu.dtb.write_accesses 0 # DTB write accesses
317 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
318 system.cpu.dtb.hits 0 # DTB hits
319 system.cpu.dtb.misses 0 # DTB misses
320 system.cpu.dtb.accesses 0 # DTB accesses
321 system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
322 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
323 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
324 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
325 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
326 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
327 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
328 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
329 system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
330 system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
331 system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
332 system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
333 system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
334 system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
335 system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
336 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
337 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
338 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
339 system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
340 system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
341 system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
342 system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
343 system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
344 system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
345 system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
346 system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
347 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
348 system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
349 system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
350 system.cpu.itb.walker.walks 0 # Table walker walks requested
351 system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
352 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
353 system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
354 system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
355 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
356 system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
357 system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
358 system.cpu.itb.inst_hits 0 # ITB inst hits
359 system.cpu.itb.inst_misses 0 # ITB inst misses
360 system.cpu.itb.read_hits 0 # DTB read hits
361 system.cpu.itb.read_misses 0 # DTB read misses
362 system.cpu.itb.write_hits 0 # DTB write hits
363 system.cpu.itb.write_misses 0 # DTB write misses
364 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
365 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
366 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
367 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
368 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
369 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
370 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
371 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
372 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
373 system.cpu.itb.read_accesses 0 # DTB read accesses
374 system.cpu.itb.write_accesses 0 # DTB write accesses
375 system.cpu.itb.inst_accesses 0 # ITB inst accesses
376 system.cpu.itb.hits 0 # DTB hits
377 system.cpu.itb.misses 0 # DTB misses
378 system.cpu.itb.accesses 0 # DTB accesses
379 system.cpu.workload.num_syscalls 400 # Number of system calls
380 system.cpu.numCycles 261545285 # number of cpu cycles simulated
381 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
382 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
383 system.cpu.committedInsts 172317810 # Number of instructions committed
384 system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed
385 system.cpu.discardedOps 11660914 # Number of ops (including micro ops) which were discarded before commit
386 system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
387 system.cpu.cpi 1.517808 # CPI: cycles per instruction
388 system.cpu.ipc 0.658845 # IPC: instructions per cycle
389 system.cpu.tickCycles 255252020 # Number of cycles that the object actually ticked
390 system.cpu.idleCycles 6293265 # Total number of cycles that the object has spent stopped
391 system.cpu.dcache.tags.replacements 42 # number of replacements
392 system.cpu.dcache.tags.tagsinuse 1377.707606 # Cycle average of tags in use
393 system.cpu.dcache.tags.total_refs 40756382 # Total number of references to valid blocks.
394 system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks.
395 system.cpu.dcache.tags.avg_refs 22517.338122 # Average number of references to valid blocks.
396 system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
397 system.cpu.dcache.tags.occ_blocks::cpu.data 1377.707606 # Average occupied blocks per requestor
398 system.cpu.dcache.tags.occ_percent::cpu.data 0.336354 # Average percentage of cache occupancy
399 system.cpu.dcache.tags.occ_percent::total 0.336354 # Average percentage of cache occupancy
400 system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id
401 system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
402 system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id
403 system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id
404 system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id
405 system.cpu.dcache.tags.age_task_id_blocks_1024::4 1358 # Occupied blocks per task id
406 system.cpu.dcache.tags.occ_task_id_percent::1024 0.431641 # Percentage of cache occupancy per task id
407 system.cpu.dcache.tags.tag_accesses 81519460 # Number of tag accesses
408 system.cpu.dcache.tags.data_accesses 81519460 # Number of data accesses
409 system.cpu.dcache.ReadReq_hits::cpu.data 28348467 # number of ReadReq hits
410 system.cpu.dcache.ReadReq_hits::total 28348467 # number of ReadReq hits
411 system.cpu.dcache.WriteReq_hits::cpu.data 12362639 # number of WriteReq hits
412 system.cpu.dcache.WriteReq_hits::total 12362639 # number of WriteReq hits
413 system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits
414 system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits
415 system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits
416 system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits
417 system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits
418 system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits
419 system.cpu.dcache.demand_hits::cpu.data 40711106 # number of demand (read+write) hits
420 system.cpu.dcache.demand_hits::total 40711106 # number of demand (read+write) hits
421 system.cpu.dcache.overall_hits::cpu.data 40711568 # number of overall hits
422 system.cpu.dcache.overall_hits::total 40711568 # number of overall hits
423 system.cpu.dcache.ReadReq_misses::cpu.data 794 # number of ReadReq misses
424 system.cpu.dcache.ReadReq_misses::total 794 # number of ReadReq misses
425 system.cpu.dcache.WriteReq_misses::cpu.data 1648 # number of WriteReq misses
426 system.cpu.dcache.WriteReq_misses::total 1648 # number of WriteReq misses
427 system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses
428 system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses
429 system.cpu.dcache.demand_misses::cpu.data 2442 # number of demand (read+write) misses
430 system.cpu.dcache.demand_misses::total 2442 # number of demand (read+write) misses
431 system.cpu.dcache.overall_misses::cpu.data 2443 # number of overall misses
432 system.cpu.dcache.overall_misses::total 2443 # number of overall misses
433 system.cpu.dcache.ReadReq_miss_latency::cpu.data 58082000 # number of ReadReq miss cycles
434 system.cpu.dcache.ReadReq_miss_latency::total 58082000 # number of ReadReq miss cycles
435 system.cpu.dcache.WriteReq_miss_latency::cpu.data 126294500 # number of WriteReq miss cycles
436 system.cpu.dcache.WriteReq_miss_latency::total 126294500 # number of WriteReq miss cycles
437 system.cpu.dcache.demand_miss_latency::cpu.data 184376500 # number of demand (read+write) miss cycles
438 system.cpu.dcache.demand_miss_latency::total 184376500 # number of demand (read+write) miss cycles
439 system.cpu.dcache.overall_miss_latency::cpu.data 184376500 # number of overall miss cycles
440 system.cpu.dcache.overall_miss_latency::total 184376500 # number of overall miss cycles
441 system.cpu.dcache.ReadReq_accesses::cpu.data 28349261 # number of ReadReq accesses(hits+misses)
442 system.cpu.dcache.ReadReq_accesses::total 28349261 # number of ReadReq accesses(hits+misses)
443 system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
444 system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
445 system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses)
446 system.cpu.dcache.SoftPFReq_accesses::total 463 # number of SoftPFReq accesses(hits+misses)
447 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses)
448 system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses)
449 system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses)
450 system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses)
451 system.cpu.dcache.demand_accesses::cpu.data 40713548 # number of demand (read+write) accesses
452 system.cpu.dcache.demand_accesses::total 40713548 # number of demand (read+write) accesses
453 system.cpu.dcache.overall_accesses::cpu.data 40714011 # number of overall (read+write) accesses
454 system.cpu.dcache.overall_accesses::total 40714011 # number of overall (read+write) accesses
455 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses
456 system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses
457 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000133 # miss rate for WriteReq accesses
458 system.cpu.dcache.WriteReq_miss_rate::total 0.000133 # miss rate for WriteReq accesses
459 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002160 # miss rate for SoftPFReq accesses
460 system.cpu.dcache.SoftPFReq_miss_rate::total 0.002160 # miss rate for SoftPFReq accesses
461 system.cpu.dcache.demand_miss_rate::cpu.data 0.000060 # miss rate for demand accesses
462 system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses
463 system.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses
464 system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses
465 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73151.133501 # average ReadReq miss latency
466 system.cpu.dcache.ReadReq_avg_miss_latency::total 73151.133501 # average ReadReq miss latency
467 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76635.012136 # average WriteReq miss latency
468 system.cpu.dcache.WriteReq_avg_miss_latency::total 76635.012136 # average WriteReq miss latency
469 system.cpu.dcache.demand_avg_miss_latency::cpu.data 75502.252252 # average overall miss latency
470 system.cpu.dcache.demand_avg_miss_latency::total 75502.252252 # average overall miss latency
471 system.cpu.dcache.overall_avg_miss_latency::cpu.data 75471.346705 # average overall miss latency
472 system.cpu.dcache.overall_avg_miss_latency::total 75471.346705 # average overall miss latency
473 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
474 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
475 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
476 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
477 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
478 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
479 system.cpu.dcache.fast_writes 0 # number of fast writes performed
480 system.cpu.dcache.cache_copies 0 # number of cache copies performed
481 system.cpu.dcache.writebacks::writebacks 16 # number of writebacks
482 system.cpu.dcache.writebacks::total 16 # number of writebacks
483 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 83 # number of ReadReq MSHR hits
484 system.cpu.dcache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits
485 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 550 # number of WriteReq MSHR hits
486 system.cpu.dcache.WriteReq_mshr_hits::total 550 # number of WriteReq MSHR hits
487 system.cpu.dcache.demand_mshr_hits::cpu.data 633 # number of demand (read+write) MSHR hits
488 system.cpu.dcache.demand_mshr_hits::total 633 # number of demand (read+write) MSHR hits
489 system.cpu.dcache.overall_mshr_hits::cpu.data 633 # number of overall MSHR hits
490 system.cpu.dcache.overall_mshr_hits::total 633 # number of overall MSHR hits
491 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711 # number of ReadReq MSHR misses
492 system.cpu.dcache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses
493 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1098 # number of WriteReq MSHR misses
494 system.cpu.dcache.WriteReq_mshr_misses::total 1098 # number of WriteReq MSHR misses
495 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
496 system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
497 system.cpu.dcache.demand_mshr_misses::cpu.data 1809 # number of demand (read+write) MSHR misses
498 system.cpu.dcache.demand_mshr_misses::total 1809 # number of demand (read+write) MSHR misses
499 system.cpu.dcache.overall_mshr_misses::cpu.data 1810 # number of overall MSHR misses
500 system.cpu.dcache.overall_mshr_misses::total 1810 # number of overall MSHR misses
501 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51822500 # number of ReadReq MSHR miss cycles
502 system.cpu.dcache.ReadReq_mshr_miss_latency::total 51822500 # number of ReadReq MSHR miss cycles
503 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85060000 # number of WriteReq MSHR miss cycles
504 system.cpu.dcache.WriteReq_mshr_miss_latency::total 85060000 # number of WriteReq MSHR miss cycles
505 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 70000 # number of SoftPFReq MSHR miss cycles
506 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 70000 # number of SoftPFReq MSHR miss cycles
507 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 136882500 # number of demand (read+write) MSHR miss cycles
508 system.cpu.dcache.demand_mshr_miss_latency::total 136882500 # number of demand (read+write) MSHR miss cycles
509 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 136952500 # number of overall MSHR miss cycles
510 system.cpu.dcache.overall_mshr_miss_latency::total 136952500 # number of overall MSHR miss cycles
511 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses
512 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses
513 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses
514 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses
515 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002160 # mshr miss rate for SoftPFReq accesses
516 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002160 # mshr miss rate for SoftPFReq accesses
517 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for demand accesses
518 system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses
519 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses
520 system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses
521 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72886.779184 # average ReadReq mshr miss latency
522 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72886.779184 # average ReadReq mshr miss latency
523 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77468.123862 # average WriteReq mshr miss latency
524 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77468.123862 # average WriteReq mshr miss latency
525 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70000 # average SoftPFReq mshr miss latency
526 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70000 # average SoftPFReq mshr miss latency
527 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75667.495854 # average overall mshr miss latency
528 system.cpu.dcache.demand_avg_mshr_miss_latency::total 75667.495854 # average overall mshr miss latency
529 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75664.364641 # average overall mshr miss latency
530 system.cpu.dcache.overall_avg_mshr_miss_latency::total 75664.364641 # average overall mshr miss latency
531 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
532 system.cpu.icache.tags.replacements 2888 # number of replacements
533 system.cpu.icache.tags.tagsinuse 1423.991712 # Cycle average of tags in use
534 system.cpu.icache.tags.total_refs 71011798 # Total number of references to valid blocks.
535 system.cpu.icache.tags.sampled_refs 4684 # Sample count of references to valid blocks.
536 system.cpu.icache.tags.avg_refs 15160.503416 # Average number of references to valid blocks.
537 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
538 system.cpu.icache.tags.occ_blocks::cpu.inst 1423.991712 # Average occupied blocks per requestor
539 system.cpu.icache.tags.occ_percent::cpu.inst 0.695308 # Average percentage of cache occupancy
540 system.cpu.icache.tags.occ_percent::total 0.695308 # Average percentage of cache occupancy
541 system.cpu.icache.tags.occ_task_id_blocks::1024 1796 # Occupied blocks per task id
542 system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
543 system.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id
544 system.cpu.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id
545 system.cpu.icache.tags.age_task_id_blocks_1024::3 123 # Occupied blocks per task id
546 system.cpu.icache.tags.age_task_id_blocks_1024::4 1068 # Occupied blocks per task id
547 system.cpu.icache.tags.occ_task_id_percent::1024 0.876953 # Percentage of cache occupancy per task id
548 system.cpu.icache.tags.tag_accesses 142037650 # Number of tag accesses
549 system.cpu.icache.tags.data_accesses 142037650 # Number of data accesses
550 system.cpu.icache.ReadReq_hits::cpu.inst 71011798 # number of ReadReq hits
551 system.cpu.icache.ReadReq_hits::total 71011798 # number of ReadReq hits
552 system.cpu.icache.demand_hits::cpu.inst 71011798 # number of demand (read+write) hits
553 system.cpu.icache.demand_hits::total 71011798 # number of demand (read+write) hits
554 system.cpu.icache.overall_hits::cpu.inst 71011798 # number of overall hits
555 system.cpu.icache.overall_hits::total 71011798 # number of overall hits
556 system.cpu.icache.ReadReq_misses::cpu.inst 4685 # number of ReadReq misses
557 system.cpu.icache.ReadReq_misses::total 4685 # number of ReadReq misses
558 system.cpu.icache.demand_misses::cpu.inst 4685 # number of demand (read+write) misses
559 system.cpu.icache.demand_misses::total 4685 # number of demand (read+write) misses
560 system.cpu.icache.overall_misses::cpu.inst 4685 # number of overall misses
561 system.cpu.icache.overall_misses::total 4685 # number of overall misses
562 system.cpu.icache.ReadReq_miss_latency::cpu.inst 199916500 # number of ReadReq miss cycles
563 system.cpu.icache.ReadReq_miss_latency::total 199916500 # number of ReadReq miss cycles
564 system.cpu.icache.demand_miss_latency::cpu.inst 199916500 # number of demand (read+write) miss cycles
565 system.cpu.icache.demand_miss_latency::total 199916500 # number of demand (read+write) miss cycles
566 system.cpu.icache.overall_miss_latency::cpu.inst 199916500 # number of overall miss cycles
567 system.cpu.icache.overall_miss_latency::total 199916500 # number of overall miss cycles
568 system.cpu.icache.ReadReq_accesses::cpu.inst 71016483 # number of ReadReq accesses(hits+misses)
569 system.cpu.icache.ReadReq_accesses::total 71016483 # number of ReadReq accesses(hits+misses)
570 system.cpu.icache.demand_accesses::cpu.inst 71016483 # number of demand (read+write) accesses
571 system.cpu.icache.demand_accesses::total 71016483 # number of demand (read+write) accesses
572 system.cpu.icache.overall_accesses::cpu.inst 71016483 # number of overall (read+write) accesses
573 system.cpu.icache.overall_accesses::total 71016483 # number of overall (read+write) accesses
574 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses
575 system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses
576 system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses
577 system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses
578 system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses
579 system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses
580 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42671.611526 # average ReadReq miss latency
581 system.cpu.icache.ReadReq_avg_miss_latency::total 42671.611526 # average ReadReq miss latency
582 system.cpu.icache.demand_avg_miss_latency::cpu.inst 42671.611526 # average overall miss latency
583 system.cpu.icache.demand_avg_miss_latency::total 42671.611526 # average overall miss latency
584 system.cpu.icache.overall_avg_miss_latency::cpu.inst 42671.611526 # average overall miss latency
585 system.cpu.icache.overall_avg_miss_latency::total 42671.611526 # average overall miss latency
586 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
587 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
588 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
589 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
590 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
591 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
592 system.cpu.icache.fast_writes 0 # number of fast writes performed
593 system.cpu.icache.cache_copies 0 # number of cache copies performed
594 system.cpu.icache.writebacks::writebacks 2888 # number of writebacks
595 system.cpu.icache.writebacks::total 2888 # number of writebacks
596 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4685 # number of ReadReq MSHR misses
597 system.cpu.icache.ReadReq_mshr_misses::total 4685 # number of ReadReq MSHR misses
598 system.cpu.icache.demand_mshr_misses::cpu.inst 4685 # number of demand (read+write) MSHR misses
599 system.cpu.icache.demand_mshr_misses::total 4685 # number of demand (read+write) MSHR misses
600 system.cpu.icache.overall_mshr_misses::cpu.inst 4685 # number of overall MSHR misses
601 system.cpu.icache.overall_mshr_misses::total 4685 # number of overall MSHR misses
602 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 195232500 # number of ReadReq MSHR miss cycles
603 system.cpu.icache.ReadReq_mshr_miss_latency::total 195232500 # number of ReadReq MSHR miss cycles
604 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 195232500 # number of demand (read+write) MSHR miss cycles
605 system.cpu.icache.demand_mshr_miss_latency::total 195232500 # number of demand (read+write) MSHR miss cycles
606 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 195232500 # number of overall MSHR miss cycles
607 system.cpu.icache.overall_mshr_miss_latency::total 195232500 # number of overall MSHR miss cycles
608 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses
609 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses
610 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses
611 system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses
612 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses
613 system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses
614 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41671.824973 # average ReadReq mshr miss latency
615 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41671.824973 # average ReadReq mshr miss latency
616 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41671.824973 # average overall mshr miss latency
617 system.cpu.icache.demand_avg_mshr_miss_latency::total 41671.824973 # average overall mshr miss latency
618 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41671.824973 # average overall mshr miss latency
619 system.cpu.icache.overall_avg_mshr_miss_latency::total 41671.824973 # average overall mshr miss latency
620 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
621 system.cpu.l2cache.tags.replacements 0 # number of replacements
622 system.cpu.l2cache.tags.tagsinuse 2000.604140 # Cycle average of tags in use
623 system.cpu.l2cache.tags.total_refs 5191 # Total number of references to valid blocks.
624 system.cpu.l2cache.tags.sampled_refs 2784 # Sample count of references to valid blocks.
625 system.cpu.l2cache.tags.avg_refs 1.864583 # Average number of references to valid blocks.
626 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
627 system.cpu.l2cache.tags.occ_blocks::writebacks 3.029285 # Average occupied blocks per requestor
628 system.cpu.l2cache.tags.occ_blocks::cpu.inst 1506.756648 # Average occupied blocks per requestor
629 system.cpu.l2cache.tags.occ_blocks::cpu.data 490.818207 # Average occupied blocks per requestor
630 system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy
631 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.045983 # Average percentage of cache occupancy
632 system.cpu.l2cache.tags.occ_percent::cpu.data 0.014979 # Average percentage of cache occupancy
633 system.cpu.l2cache.tags.occ_percent::total 0.061054 # Average percentage of cache occupancy
634 system.cpu.l2cache.tags.occ_task_id_blocks::1024 2784 # Occupied blocks per task id
635 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
636 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id
637 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 524 # Occupied blocks per task id
638 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 151 # Occupied blocks per task id
639 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2004 # Occupied blocks per task id
640 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.084961 # Percentage of cache occupancy per task id
641 system.cpu.l2cache.tags.tag_accesses 76658 # Number of tag accesses
642 system.cpu.l2cache.tags.data_accesses 76658 # Number of data accesses
643 system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits
644 system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits
645 system.cpu.l2cache.WritebackClean_hits::writebacks 2566 # number of WritebackClean hits
646 system.cpu.l2cache.WritebackClean_hits::total 2566 # number of WritebackClean hits
647 system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits
648 system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits
649 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2524 # number of ReadCleanReq hits
650 system.cpu.l2cache.ReadCleanReq_hits::total 2524 # number of ReadCleanReq hits
651 system.cpu.l2cache.ReadSharedReq_hits::cpu.data 80 # number of ReadSharedReq hits
652 system.cpu.l2cache.ReadSharedReq_hits::total 80 # number of ReadSharedReq hits
653 system.cpu.l2cache.demand_hits::cpu.inst 2524 # number of demand (read+write) hits
654 system.cpu.l2cache.demand_hits::cpu.data 88 # number of demand (read+write) hits
655 system.cpu.l2cache.demand_hits::total 2612 # number of demand (read+write) hits
656 system.cpu.l2cache.overall_hits::cpu.inst 2524 # number of overall hits
657 system.cpu.l2cache.overall_hits::cpu.data 88 # number of overall hits
658 system.cpu.l2cache.overall_hits::total 2612 # number of overall hits
659 system.cpu.l2cache.ReadExReq_misses::cpu.data 1090 # number of ReadExReq misses
660 system.cpu.l2cache.ReadExReq_misses::total 1090 # number of ReadExReq misses
661 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2161 # number of ReadCleanReq misses
662 system.cpu.l2cache.ReadCleanReq_misses::total 2161 # number of ReadCleanReq misses
663 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 632 # number of ReadSharedReq misses
664 system.cpu.l2cache.ReadSharedReq_misses::total 632 # number of ReadSharedReq misses
665 system.cpu.l2cache.demand_misses::cpu.inst 2161 # number of demand (read+write) misses
666 system.cpu.l2cache.demand_misses::cpu.data 1722 # number of demand (read+write) misses
667 system.cpu.l2cache.demand_misses::total 3883 # number of demand (read+write) misses
668 system.cpu.l2cache.overall_misses::cpu.inst 2161 # number of overall misses
669 system.cpu.l2cache.overall_misses::cpu.data 1722 # number of overall misses
670 system.cpu.l2cache.overall_misses::total 3883 # number of overall misses
671 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 83327500 # number of ReadExReq miss cycles
672 system.cpu.l2cache.ReadExReq_miss_latency::total 83327500 # number of ReadExReq miss cycles
673 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 161329500 # number of ReadCleanReq miss cycles
674 system.cpu.l2cache.ReadCleanReq_miss_latency::total 161329500 # number of ReadCleanReq miss cycles
675 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49900500 # number of ReadSharedReq miss cycles
676 system.cpu.l2cache.ReadSharedReq_miss_latency::total 49900500 # number of ReadSharedReq miss cycles
677 system.cpu.l2cache.demand_miss_latency::cpu.inst 161329500 # number of demand (read+write) miss cycles
678 system.cpu.l2cache.demand_miss_latency::cpu.data 133228000 # number of demand (read+write) miss cycles
679 system.cpu.l2cache.demand_miss_latency::total 294557500 # number of demand (read+write) miss cycles
680 system.cpu.l2cache.overall_miss_latency::cpu.inst 161329500 # number of overall miss cycles
681 system.cpu.l2cache.overall_miss_latency::cpu.data 133228000 # number of overall miss cycles
682 system.cpu.l2cache.overall_miss_latency::total 294557500 # number of overall miss cycles
683 system.cpu.l2cache.WritebackDirty_accesses::writebacks 16 # number of WritebackDirty accesses(hits+misses)
684 system.cpu.l2cache.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses)
685 system.cpu.l2cache.WritebackClean_accesses::writebacks 2566 # number of WritebackClean accesses(hits+misses)
686 system.cpu.l2cache.WritebackClean_accesses::total 2566 # number of WritebackClean accesses(hits+misses)
687 system.cpu.l2cache.ReadExReq_accesses::cpu.data 1098 # number of ReadExReq accesses(hits+misses)
688 system.cpu.l2cache.ReadExReq_accesses::total 1098 # number of ReadExReq accesses(hits+misses)
689 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4685 # number of ReadCleanReq accesses(hits+misses)
690 system.cpu.l2cache.ReadCleanReq_accesses::total 4685 # number of ReadCleanReq accesses(hits+misses)
691 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712 # number of ReadSharedReq accesses(hits+misses)
692 system.cpu.l2cache.ReadSharedReq_accesses::total 712 # number of ReadSharedReq accesses(hits+misses)
693 system.cpu.l2cache.demand_accesses::cpu.inst 4685 # number of demand (read+write) accesses
694 system.cpu.l2cache.demand_accesses::cpu.data 1810 # number of demand (read+write) accesses
695 system.cpu.l2cache.demand_accesses::total 6495 # number of demand (read+write) accesses
696 system.cpu.l2cache.overall_accesses::cpu.inst 4685 # number of overall (read+write) accesses
697 system.cpu.l2cache.overall_accesses::cpu.data 1810 # number of overall (read+write) accesses
698 system.cpu.l2cache.overall_accesses::total 6495 # number of overall (read+write) accesses
699 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992714 # miss rate for ReadExReq accesses
700 system.cpu.l2cache.ReadExReq_miss_rate::total 0.992714 # miss rate for ReadExReq accesses
701 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.461259 # miss rate for ReadCleanReq accesses
702 system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.461259 # miss rate for ReadCleanReq accesses
703 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.887640 # miss rate for ReadSharedReq accesses
704 system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.887640 # miss rate for ReadSharedReq accesses
705 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.461259 # miss rate for demand accesses
706 system.cpu.l2cache.demand_miss_rate::cpu.data 0.951381 # miss rate for demand accesses
707 system.cpu.l2cache.demand_miss_rate::total 0.597844 # miss rate for demand accesses
708 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.461259 # miss rate for overall accesses
709 system.cpu.l2cache.overall_miss_rate::cpu.data 0.951381 # miss rate for overall accesses
710 system.cpu.l2cache.overall_miss_rate::total 0.597844 # miss rate for overall accesses
711 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76447.247706 # average ReadExReq miss latency
712 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76447.247706 # average ReadExReq miss latency
713 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74655.020824 # average ReadCleanReq miss latency
714 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74655.020824 # average ReadCleanReq miss latency
715 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78956.487342 # average ReadSharedReq miss latency
716 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78956.487342 # average ReadSharedReq miss latency
717 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74655.020824 # average overall miss latency
718 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77368.176539 # average overall miss latency
719 system.cpu.l2cache.demand_avg_miss_latency::total 75858.228174 # average overall miss latency
720 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74655.020824 # average overall miss latency
721 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77368.176539 # average overall miss latency
722 system.cpu.l2cache.overall_avg_miss_latency::total 75858.228174 # average overall miss latency
723 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
724 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
725 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
726 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
727 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
728 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
729 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
730 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
731 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits
732 system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits
733 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 14 # number of ReadSharedReq MSHR hits
734 system.cpu.l2cache.ReadSharedReq_mshr_hits::total 14 # number of ReadSharedReq MSHR hits
735 system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
736 system.cpu.l2cache.demand_mshr_hits::cpu.data 14 # number of demand (read+write) MSHR hits
737 system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits
738 system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
739 system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits
740 system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits
741 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1090 # number of ReadExReq MSHR misses
742 system.cpu.l2cache.ReadExReq_mshr_misses::total 1090 # number of ReadExReq MSHR misses
743 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2159 # number of ReadCleanReq MSHR misses
744 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2159 # number of ReadCleanReq MSHR misses
745 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 618 # number of ReadSharedReq MSHR misses
746 system.cpu.l2cache.ReadSharedReq_mshr_misses::total 618 # number of ReadSharedReq MSHR misses
747 system.cpu.l2cache.demand_mshr_misses::cpu.inst 2159 # number of demand (read+write) MSHR misses
748 system.cpu.l2cache.demand_mshr_misses::cpu.data 1708 # number of demand (read+write) MSHR misses
749 system.cpu.l2cache.demand_mshr_misses::total 3867 # number of demand (read+write) MSHR misses
750 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2159 # number of overall MSHR misses
751 system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses
752 system.cpu.l2cache.overall_mshr_misses::total 3867 # number of overall MSHR misses
753 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 72427500 # number of ReadExReq MSHR miss cycles
754 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 72427500 # number of ReadExReq MSHR miss cycles
755 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 139601500 # number of ReadCleanReq MSHR miss cycles
756 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 139601500 # number of ReadCleanReq MSHR miss cycles
757 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 42758500 # number of ReadSharedReq MSHR miss cycles
758 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 42758500 # number of ReadSharedReq MSHR miss cycles
759 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 139601500 # number of demand (read+write) MSHR miss cycles
760 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 115186000 # number of demand (read+write) MSHR miss cycles
761 system.cpu.l2cache.demand_mshr_miss_latency::total 254787500 # number of demand (read+write) MSHR miss cycles
762 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 139601500 # number of overall MSHR miss cycles
763 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 115186000 # number of overall MSHR miss cycles
764 system.cpu.l2cache.overall_mshr_miss_latency::total 254787500 # number of overall MSHR miss cycles
765 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992714 # mshr miss rate for ReadExReq accesses
766 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses
767 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.460832 # mshr miss rate for ReadCleanReq accesses
768 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.460832 # mshr miss rate for ReadCleanReq accesses
769 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.867978 # mshr miss rate for ReadSharedReq accesses
770 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.867978 # mshr miss rate for ReadSharedReq accesses
771 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.460832 # mshr miss rate for demand accesses
772 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for demand accesses
773 system.cpu.l2cache.demand_mshr_miss_rate::total 0.595381 # mshr miss rate for demand accesses
774 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.460832 # mshr miss rate for overall accesses
775 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for overall accesses
776 system.cpu.l2cache.overall_mshr_miss_rate::total 0.595381 # mshr miss rate for overall accesses
777 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66447.247706 # average ReadExReq mshr miss latency
778 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66447.247706 # average ReadExReq mshr miss latency
779 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64660.259379 # average ReadCleanReq mshr miss latency
780 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64660.259379 # average ReadCleanReq mshr miss latency
781 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69188.511327 # average ReadSharedReq mshr miss latency
782 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69188.511327 # average ReadSharedReq mshr miss latency
783 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64660.259379 # average overall mshr miss latency
784 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67439.110070 # average overall mshr miss latency
785 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65887.638997 # average overall mshr miss latency
786 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64660.259379 # average overall mshr miss latency
787 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67439.110070 # average overall mshr miss latency
788 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65887.638997 # average overall mshr miss latency
789 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
790 system.cpu.toL2Bus.snoop_filter.tot_requests 9425 # Total number of requests made to the snoop filter.
791 system.cpu.toL2Bus.snoop_filter.hit_single_requests 3064 # Number of requests hitting in the snoop filter with a single holder of the requested data.
792 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 328 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
793 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
794 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
795 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
796 system.cpu.toL2Bus.trans_dist::ReadResp 5396 # Transaction distribution
797 system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution
798 system.cpu.toL2Bus.trans_dist::WritebackClean 2888 # Transaction distribution
799 system.cpu.toL2Bus.trans_dist::CleanEvict 26 # Transaction distribution
800 system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution
801 system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution
802 system.cpu.toL2Bus.trans_dist::ReadCleanReq 4685 # Transaction distribution
803 system.cpu.toL2Bus.trans_dist::ReadSharedReq 712 # Transaction distribution
804 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12257 # Packet count per connected master and slave (bytes)
805 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3662 # Packet count per connected master and slave (bytes)
806 system.cpu.toL2Bus.pkt_count::total 15919 # Packet count per connected master and slave (bytes)
807 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 484608 # Cumulative packet size per connected master and slave (bytes)
808 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116864 # Cumulative packet size per connected master and slave (bytes)
809 system.cpu.toL2Bus.pkt_size::total 601472 # Cumulative packet size per connected master and slave (bytes)
810 system.cpu.toL2Bus.snoops 0 # Total snoops (count)
811 system.cpu.toL2Bus.snoop_fanout::samples 6495 # Request fanout histogram
812 system.cpu.toL2Bus.snoop_fanout::mean 0.071132 # Request fanout histogram
813 system.cpu.toL2Bus.snoop_fanout::stdev 0.257064 # Request fanout histogram
814 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
815 system.cpu.toL2Bus.snoop_fanout::0 6033 92.89% 92.89% # Request fanout histogram
816 system.cpu.toL2Bus.snoop_fanout::1 462 7.11% 100.00% # Request fanout histogram
817 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
818 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
819 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
820 system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
821 system.cpu.toL2Bus.snoop_fanout::total 6495 # Request fanout histogram
822 system.cpu.toL2Bus.reqLayer0.occupancy 7616500 # Layer occupancy (ticks)
823 system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
824 system.cpu.toL2Bus.respLayer0.occupancy 7026998 # Layer occupancy (ticks)
825 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
826 system.cpu.toL2Bus.respLayer1.occupancy 2721986 # Layer occupancy (ticks)
827 system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
828 system.membus.trans_dist::ReadResp 2776 # Transaction distribution
829 system.membus.trans_dist::ReadExReq 1090 # Transaction distribution
830 system.membus.trans_dist::ReadExResp 1090 # Transaction distribution
831 system.membus.trans_dist::ReadSharedReq 2776 # Transaction distribution
832 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7732 # Packet count per connected master and slave (bytes)
833 system.membus.pkt_count::total 7732 # Packet count per connected master and slave (bytes)
834 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247424 # Cumulative packet size per connected master and slave (bytes)
835 system.membus.pkt_size::total 247424 # Cumulative packet size per connected master and slave (bytes)
836 system.membus.snoops 0 # Total snoops (count)
837 system.membus.snoop_fanout::samples 3866 # Request fanout histogram
838 system.membus.snoop_fanout::mean 0 # Request fanout histogram
839 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
840 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
841 system.membus.snoop_fanout::0 3866 100.00% 100.00% # Request fanout histogram
842 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
843 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
844 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
845 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
846 system.membus.snoop_fanout::total 3866 # Request fanout histogram
847 system.membus.reqLayer0.occupancy 4535500 # Layer occupancy (ticks)
848 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
849 system.membus.respLayer1.occupancy 20543250 # Layer occupancy (ticks)
850 system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
852 ---------- End Simulation Statistics ----------
projects / gem5.git / blob