tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 default_p_state=UNDEFINED
  18 eventq_index=0
  19 exit_on_work_items=false
  20 init_param=0
  21 kernel=
  22 kernel_addr_check=true
  23 load_addr_mask=1099511627775
  24 load_offset=0
  25 mem_mode=timing
  26 mem_ranges=
  27 memories=system.physmem
  28 mmap_using_noreserve=false
  29 multi_thread=false
  30 num_work_ids=16
  31 p_state_clk_gate_bins=20
  32 p_state_clk_gate_max=1000000000000
  33 p_state_clk_gate_min=1000
  34 power_model=Null
  35 readfile=
  36 symbolfile=
  37 thermal_components=
  38 thermal_model=Null
  39 work_begin_ckpt_count=0
  40 work_begin_cpu_id_exit=-1
  41 work_begin_exit_count=0
  42 work_cpus_ckpt_count=0
  43 work_end_ckpt_count=0
  44 work_end_exit_count=0
  45 work_item_id=-1
  46 system_port=system.membus.slave[0]
  47
  48 [system.clk_domain]
  49 type=SrcClockDomain
  50 clock=1000
  51 domain_id=-1
  52 eventq_index=0
  53 init_perf_level=0
  54 voltage_domain=system.voltage_domain
  55
  56 [system.cpu]
  57 type=DerivO3CPU
  58 children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
  59 LFSTSize=1024
  60 LQEntries=16
  61 LSQCheckLoads=true
  62 LSQDepCheckShift=0
  63 SQEntries=16
  64 SSITSize=1024
  65 activity=0
  66 backComSize=5
  67 branchPred=system.cpu.branchPred
  68 cachePorts=200
  69 checker=Null
  70 clk_domain=system.cpu_clk_domain
  71 commitToDecodeDelay=1
  72 commitToFetchDelay=1
  73 commitToIEWDelay=1
  74 commitToRenameDelay=1
  75 commitWidth=8
  76 cpu_id=0
  77 decodeToFetchDelay=1
  78 decodeToRenameDelay=2
  79 decodeWidth=3
  80 default_p_state=UNDEFINED
  81 dispatchWidth=6
  82 do_checkpoint_insts=true
  83 do_quiesce=true
  84 do_statistics_insts=true
  85 dstage2_mmu=system.cpu.dstage2_mmu
  86 dtb=system.cpu.dtb
  87 eventq_index=0
  88 fetchBufferSize=16
  89 fetchQueueSize=32
  90 fetchToDecodeDelay=3
  91 fetchTrapLatency=1
  92 fetchWidth=3
  93 forwardComSize=5
  94 fuPool=system.cpu.fuPool
  95 function_trace=false
  96 function_trace_start=0
  97 iewToCommitDelay=1
  98 iewToDecodeDelay=1
  99 iewToFetchDelay=1
 100 iewToRenameDelay=1
 101 interrupts=system.cpu.interrupts
 102 isa=system.cpu.isa
 103 issueToExecuteDelay=1
 104 issueWidth=8
 105 istage2_mmu=system.cpu.istage2_mmu
 106 itb=system.cpu.itb
 107 max_insts_all_threads=0
 108 max_insts_any_thread=0
 109 max_loads_all_threads=0
 110 max_loads_any_thread=0
 111 needsTSO=false
 112 numIQEntries=32
 113 numPhysCCRegs=640
 114 numPhysFloatRegs=192
 115 numPhysIntRegs=128
 116 numROBEntries=40
 117 numRobs=1
 118 numThreads=1
 119 p_state_clk_gate_bins=20
 120 p_state_clk_gate_max=1000000000000
 121 p_state_clk_gate_min=1000
 122 power_model=Null
 123 profile=0
 124 progress_interval=0
 125 renameToDecodeDelay=1
 126 renameToFetchDelay=1
 127 renameToIEWDelay=1
 128 renameToROBDelay=1
 129 renameWidth=3
 130 simpoint_start_insts=
 131 smtCommitPolicy=RoundRobin
 132 smtFetchPolicy=SingleThread
 133 smtIQPolicy=Partitioned
 134 smtIQThreshold=100
 135 smtLSQPolicy=Partitioned
 136 smtLSQThreshold=100
 137 smtNumFetchingThreads=1
 138 smtROBPolicy=Partitioned
 139 smtROBThreshold=100
 140 socket_id=0
 141 squashWidth=8
 142 store_set_clear_period=250000
 143 switched_out=false
 144 system=system
 145 tracer=system.cpu.tracer
 146 trapLatency=13
 147 wbWidth=8
 148 workload=system.cpu.workload
 149 dcache_port=system.cpu.dcache.cpu_side
 150 icache_port=system.cpu.icache.cpu_side
 151
 152 [system.cpu.branchPred]
 153 type=BiModeBP
 154 BTBEntries=2048
 155 BTBTagSize=18
 156 RASSize=16
 157 choiceCtrBits=2
 158 choicePredictorSize=8192
 159 eventq_index=0
 160 globalCtrBits=2
 161 globalPredictorSize=8192
 162 indirectHashGHR=true
 163 indirectHashTargets=true
 164 indirectPathLength=3
 165 indirectSets=256
 166 indirectTagSize=16
 167 indirectWays=2
 168 instShiftAmt=2
 169 numThreads=1
 170 useIndirect=true
 171
 172 [system.cpu.dcache]
 173 type=Cache
 174 children=tags
 175 addr_ranges=0:18446744073709551615:0:0:0:0
 176 assoc=2
 177 clk_domain=system.cpu_clk_domain
 178 clusivity=mostly_incl
 179 default_p_state=UNDEFINED
 180 demand_mshr_reserve=1
 181 eventq_index=0
 182 hit_latency=2
 183 is_read_only=false
 184 max_miss_count=0
 185 mshrs=6
 186 p_state_clk_gate_bins=20
 187 p_state_clk_gate_max=1000000000000
 188 p_state_clk_gate_min=1000
 189 power_model=Null
 190 prefetch_on_access=false
 191 prefetcher=Null
 192 response_latency=2
 193 sequential_access=false
 194 size=32768
 195 system=system
 196 tags=system.cpu.dcache.tags
 197 tgts_per_mshr=8
 198 write_buffers=16
 199 writeback_clean=true
 200 cpu_side=system.cpu.dcache_port
 201 mem_side=system.cpu.toL2Bus.slave[1]
 202
 203 [system.cpu.dcache.tags]
 204 type=LRU
 205 assoc=2
 206 block_size=64
 207 clk_domain=system.cpu_clk_domain
 208 default_p_state=UNDEFINED
 209 eventq_index=0
 210 hit_latency=2
 211 p_state_clk_gate_bins=20
 212 p_state_clk_gate_max=1000000000000
 213 p_state_clk_gate_min=1000
 214 power_model=Null
 215 sequential_access=false
 216 size=32768
 217
 218 [system.cpu.dstage2_mmu]
 219 type=ArmStage2MMU
 220 children=stage2_tlb
 221 eventq_index=0
 222 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
 223 sys=system
 224 tlb=system.cpu.dtb
 225
 226 [system.cpu.dstage2_mmu.stage2_tlb]
 227 type=ArmTLB
 228 children=walker
 229 eventq_index=0
 230 is_stage2=true
 231 size=32
 232 walker=system.cpu.dstage2_mmu.stage2_tlb.walker
 233
 234 [system.cpu.dstage2_mmu.stage2_tlb.walker]
 235 type=ArmTableWalker
 236 clk_domain=system.cpu_clk_domain
 237 default_p_state=UNDEFINED
 238 eventq_index=0
 239 is_stage2=true
 240 num_squash_per_cycle=2
 241 p_state_clk_gate_bins=20
 242 p_state_clk_gate_max=1000000000000
 243 p_state_clk_gate_min=1000
 244 power_model=Null
 245 sys=system
 246
 247 [system.cpu.dtb]
 248 type=ArmTLB
 249 children=walker
 250 eventq_index=0
 251 is_stage2=false
 252 size=64
 253 walker=system.cpu.dtb.walker
 254
 255 [system.cpu.dtb.walker]
 256 type=ArmTableWalker
 257 clk_domain=system.cpu_clk_domain
 258 default_p_state=UNDEFINED
 259 eventq_index=0
 260 is_stage2=false
 261 num_squash_per_cycle=2
 262 p_state_clk_gate_bins=20
 263 p_state_clk_gate_max=1000000000000
 264 p_state_clk_gate_min=1000
 265 power_model=Null
 266 sys=system
 267 port=system.cpu.toL2Bus.slave[3]
 268
 269 [system.cpu.fuPool]
 270 type=FUPool
 271 children=FUList0 FUList1 FUList2 FUList3 FUList4
 272 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
 273 eventq_index=0
 274
 275 [system.cpu.fuPool.FUList0]
 276 type=FUDesc
 277 children=opList
 278 count=2
 279 eventq_index=0
 280 opList=system.cpu.fuPool.FUList0.opList
 281
 282 [system.cpu.fuPool.FUList0.opList]
 283 type=OpDesc
 284 eventq_index=0
 285 opClass=IntAlu
 286 opLat=1
 287 pipelined=true
 288
 289 [system.cpu.fuPool.FUList1]
 290 type=FUDesc
 291 children=opList0 opList1 opList2
 292 count=1
 293 eventq_index=0
 294 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
 295
 296 [system.cpu.fuPool.FUList1.opList0]
 297 type=OpDesc
 298 eventq_index=0
 299 opClass=IntMult
 300 opLat=3
 301 pipelined=true
 302
 303 [system.cpu.fuPool.FUList1.opList1]
 304 type=OpDesc
 305 eventq_index=0
 306 opClass=IntDiv
 307 opLat=12
 308 pipelined=false
 309
 310 [system.cpu.fuPool.FUList1.opList2]
 311 type=OpDesc
 312 eventq_index=0
 313 opClass=IprAccess
 314 opLat=3
 315 pipelined=true
 316
 317 [system.cpu.fuPool.FUList2]
 318 type=FUDesc
 319 children=opList
 320 count=1
 321 eventq_index=0
 322 opList=system.cpu.fuPool.FUList2.opList
 323
 324 [system.cpu.fuPool.FUList2.opList]
 325 type=OpDesc
 326 eventq_index=0
 327 opClass=MemRead
 328 opLat=2
 329 pipelined=true
 330
 331 [system.cpu.fuPool.FUList3]
 332 type=FUDesc
 333 children=opList
 334 count=1
 335 eventq_index=0
 336 opList=system.cpu.fuPool.FUList3.opList
 337
 338 [system.cpu.fuPool.FUList3.opList]
 339 type=OpDesc
 340 eventq_index=0
 341 opClass=MemWrite
 342 opLat=2
 343 pipelined=true
 344
 345 [system.cpu.fuPool.FUList4]
 346 type=FUDesc
 347 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
 348 count=2
 349 eventq_index=0
 350 opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
 351
 352 [system.cpu.fuPool.FUList4.opList00]
 353 type=OpDesc
 354 eventq_index=0
 355 opClass=SimdAdd
 356 opLat=4
 357 pipelined=true
 358
 359 [system.cpu.fuPool.FUList4.opList01]
 360 type=OpDesc
 361 eventq_index=0
 362 opClass=SimdAddAcc
 363 opLat=4
 364 pipelined=true
 365
 366 [system.cpu.fuPool.FUList4.opList02]
 367 type=OpDesc
 368 eventq_index=0
 369 opClass=SimdAlu
 370 opLat=4
 371 pipelined=true
 372
 373 [system.cpu.fuPool.FUList4.opList03]
 374 type=OpDesc
 375 eventq_index=0
 376 opClass=SimdCmp
 377 opLat=4
 378 pipelined=true
 379
 380 [system.cpu.fuPool.FUList4.opList04]
 381 type=OpDesc
 382 eventq_index=0
 383 opClass=SimdCvt
 384 opLat=3
 385 pipelined=true
 386
 387 [system.cpu.fuPool.FUList4.opList05]
 388 type=OpDesc
 389 eventq_index=0
 390 opClass=SimdMisc
 391 opLat=3
 392 pipelined=true
 393
 394 [system.cpu.fuPool.FUList4.opList06]
 395 type=OpDesc
 396 eventq_index=0
 397 opClass=SimdMult
 398 opLat=5
 399 pipelined=true
 400
 401 [system.cpu.fuPool.FUList4.opList07]
 402 type=OpDesc
 403 eventq_index=0
 404 opClass=SimdMultAcc
 405 opLat=5
 406 pipelined=true
 407
 408 [system.cpu.fuPool.FUList4.opList08]
 409 type=OpDesc
 410 eventq_index=0
 411 opClass=SimdShift
 412 opLat=3
 413 pipelined=true
 414
 415 [system.cpu.fuPool.FUList4.opList09]
 416 type=OpDesc
 417 eventq_index=0
 418 opClass=SimdShiftAcc
 419 opLat=3
 420 pipelined=true
 421
 422 [system.cpu.fuPool.FUList4.opList10]
 423 type=OpDesc
 424 eventq_index=0
 425 opClass=SimdSqrt
 426 opLat=9
 427 pipelined=true
 428
 429 [system.cpu.fuPool.FUList4.opList11]
 430 type=OpDesc
 431 eventq_index=0
 432 opClass=SimdFloatAdd
 433 opLat=5
 434 pipelined=true
 435
 436 [system.cpu.fuPool.FUList4.opList12]
 437 type=OpDesc
 438 eventq_index=0
 439 opClass=SimdFloatAlu
 440 opLat=5
 441 pipelined=true
 442
 443 [system.cpu.fuPool.FUList4.opList13]
 444 type=OpDesc
 445 eventq_index=0
 446 opClass=SimdFloatCmp
 447 opLat=3
 448 pipelined=true
 449
 450 [system.cpu.fuPool.FUList4.opList14]
 451 type=OpDesc
 452 eventq_index=0
 453 opClass=SimdFloatCvt
 454 opLat=3
 455 pipelined=true
 456
 457 [system.cpu.fuPool.FUList4.opList15]
 458 type=OpDesc
 459 eventq_index=0
 460 opClass=SimdFloatDiv
 461 opLat=3
 462 pipelined=true
 463
 464 [system.cpu.fuPool.FUList4.opList16]
 465 type=OpDesc
 466 eventq_index=0
 467 opClass=SimdFloatMisc
 468 opLat=3
 469 pipelined=true
 470
 471 [system.cpu.fuPool.FUList4.opList17]
 472 type=OpDesc
 473 eventq_index=0
 474 opClass=SimdFloatMult
 475 opLat=3
 476 pipelined=true
 477
 478 [system.cpu.fuPool.FUList4.opList18]
 479 type=OpDesc
 480 eventq_index=0
 481 opClass=SimdFloatMultAcc
 482 opLat=1
 483 pipelined=true
 484
 485 [system.cpu.fuPool.FUList4.opList19]
 486 type=OpDesc
 487 eventq_index=0
 488 opClass=SimdFloatSqrt
 489 opLat=9
 490 pipelined=true
 491
 492 [system.cpu.fuPool.FUList4.opList20]
 493 type=OpDesc
 494 eventq_index=0
 495 opClass=FloatAdd
 496 opLat=5
 497 pipelined=true
 498
 499 [system.cpu.fuPool.FUList4.opList21]
 500 type=OpDesc
 501 eventq_index=0
 502 opClass=FloatCmp
 503 opLat=5
 504 pipelined=true
 505
 506 [system.cpu.fuPool.FUList4.opList22]
 507 type=OpDesc
 508 eventq_index=0
 509 opClass=FloatCvt
 510 opLat=5
 511 pipelined=true
 512
 513 [system.cpu.fuPool.FUList4.opList23]
 514 type=OpDesc
 515 eventq_index=0
 516 opClass=FloatDiv
 517 opLat=9
 518 pipelined=false
 519
 520 [system.cpu.fuPool.FUList4.opList24]
 521 type=OpDesc
 522 eventq_index=0
 523 opClass=FloatSqrt
 524 opLat=33
 525 pipelined=false
 526
 527 [system.cpu.fuPool.FUList4.opList25]
 528 type=OpDesc
 529 eventq_index=0
 530 opClass=FloatMult
 531 opLat=4
 532 pipelined=true
 533
 534 [system.cpu.icache]
 535 type=Cache
 536 children=tags
 537 addr_ranges=0:18446744073709551615:0:0:0:0
 538 assoc=2
 539 clk_domain=system.cpu_clk_domain
 540 clusivity=mostly_incl
 541 default_p_state=UNDEFINED
 542 demand_mshr_reserve=1
 543 eventq_index=0
 544 hit_latency=1
 545 is_read_only=true
 546 max_miss_count=0
 547 mshrs=2
 548 p_state_clk_gate_bins=20
 549 p_state_clk_gate_max=1000000000000
 550 p_state_clk_gate_min=1000
 551 power_model=Null
 552 prefetch_on_access=false
 553 prefetcher=Null
 554 response_latency=1
 555 sequential_access=false
 556 size=32768
 557 system=system
 558 tags=system.cpu.icache.tags
 559 tgts_per_mshr=8
 560 write_buffers=8
 561 writeback_clean=true
 562 cpu_side=system.cpu.icache_port
 563 mem_side=system.cpu.toL2Bus.slave[0]
 564
 565 [system.cpu.icache.tags]
 566 type=LRU
 567 assoc=2
 568 block_size=64
 569 clk_domain=system.cpu_clk_domain
 570 default_p_state=UNDEFINED
 571 eventq_index=0
 572 hit_latency=1
 573 p_state_clk_gate_bins=20
 574 p_state_clk_gate_max=1000000000000
 575 p_state_clk_gate_min=1000
 576 power_model=Null
 577 sequential_access=false
 578 size=32768
 579
 580 [system.cpu.interrupts]
 581 type=ArmInterrupts
 582 eventq_index=0
 583
 584 [system.cpu.isa]
 585 type=ArmISA
 586 decoderFlavour=Generic
 587 eventq_index=0
 588 fpsid=1090793632
 589 id_aa64afr0_el1=0
 590 id_aa64afr1_el1=0
 591 id_aa64dfr0_el1=1052678
 592 id_aa64dfr1_el1=0
 593 id_aa64isar0_el1=0
 594 id_aa64isar1_el1=0
 595 id_aa64mmfr0_el1=15728642
 596 id_aa64mmfr1_el1=0
 597 id_aa64pfr0_el1=34
 598 id_aa64pfr1_el1=0
 599 id_isar0=34607377
 600 id_isar1=34677009
 601 id_isar2=555950401
 602 id_isar3=17899825
 603 id_isar4=268501314
 604 id_isar5=0
 605 id_mmfr0=270536963
 606 id_mmfr1=0
 607 id_mmfr2=19070976
 608 id_mmfr3=34611729
 609 id_pfr0=49
 610 id_pfr1=4113
 611 midr=1091551472
 612 pmu=Null
 613 system=system
 614
 615 [system.cpu.istage2_mmu]
 616 type=ArmStage2MMU
 617 children=stage2_tlb
 618 eventq_index=0
 619 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
 620 sys=system
 621 tlb=system.cpu.itb
 622
 623 [system.cpu.istage2_mmu.stage2_tlb]
 624 type=ArmTLB
 625 children=walker
 626 eventq_index=0
 627 is_stage2=true
 628 size=32
 629 walker=system.cpu.istage2_mmu.stage2_tlb.walker
 630
 631 [system.cpu.istage2_mmu.stage2_tlb.walker]
 632 type=ArmTableWalker
 633 clk_domain=system.cpu_clk_domain
 634 default_p_state=UNDEFINED
 635 eventq_index=0
 636 is_stage2=true
 637 num_squash_per_cycle=2
 638 p_state_clk_gate_bins=20
 639 p_state_clk_gate_max=1000000000000
 640 p_state_clk_gate_min=1000
 641 power_model=Null
 642 sys=system
 643
 644 [system.cpu.itb]
 645 type=ArmTLB
 646 children=walker
 647 eventq_index=0
 648 is_stage2=false
 649 size=64
 650 walker=system.cpu.itb.walker
 651
 652 [system.cpu.itb.walker]
 653 type=ArmTableWalker
 654 clk_domain=system.cpu_clk_domain
 655 default_p_state=UNDEFINED
 656 eventq_index=0
 657 is_stage2=false
 658 num_squash_per_cycle=2
 659 p_state_clk_gate_bins=20
 660 p_state_clk_gate_max=1000000000000
 661 p_state_clk_gate_min=1000
 662 power_model=Null
 663 sys=system
 664 port=system.cpu.toL2Bus.slave[2]
 665
 666 [system.cpu.l2cache]
 667 type=Cache
 668 children=prefetcher tags
 669 addr_ranges=0:18446744073709551615:0:0:0:0
 670 assoc=16
 671 clk_domain=system.cpu_clk_domain
 672 clusivity=mostly_excl
 673 default_p_state=UNDEFINED
 674 demand_mshr_reserve=1
 675 eventq_index=0
 676 hit_latency=12
 677 is_read_only=false
 678 max_miss_count=0
 679 mshrs=16
 680 p_state_clk_gate_bins=20
 681 p_state_clk_gate_max=1000000000000
 682 p_state_clk_gate_min=1000
 683 power_model=Null
 684 prefetch_on_access=true
 685 prefetcher=system.cpu.l2cache.prefetcher
 686 response_latency=12
 687 sequential_access=false
 688 size=1048576
 689 system=system
 690 tags=system.cpu.l2cache.tags
 691 tgts_per_mshr=8
 692 write_buffers=8
 693 writeback_clean=false
 694 cpu_side=system.cpu.toL2Bus.master[0]
 695 mem_side=system.membus.slave[1]
 696
 697 [system.cpu.l2cache.prefetcher]
 698 type=StridePrefetcher
 699 cache_snoop=false
 700 clk_domain=system.cpu_clk_domain
 701 default_p_state=UNDEFINED
 702 degree=8
 703 eventq_index=0
 704 latency=1
 705 max_conf=7
 706 min_conf=0
 707 on_data=true
 708 on_inst=true
 709 on_miss=false
 710 on_read=true
 711 on_write=true
 712 p_state_clk_gate_bins=20
 713 p_state_clk_gate_max=1000000000000
 714 p_state_clk_gate_min=1000
 715 power_model=Null
 716 queue_filter=true
 717 queue_size=32
 718 queue_squash=true
 719 start_conf=4
 720 sys=system
 721 table_assoc=4
 722 table_sets=16
 723 tag_prefetch=true
 724 thresh_conf=4
 725 use_master_id=true
 726
 727 [system.cpu.l2cache.tags]
 728 type=RandomRepl
 729 assoc=16
 730 block_size=64
 731 clk_domain=system.cpu_clk_domain
 732 default_p_state=UNDEFINED
 733 eventq_index=0
 734 hit_latency=12
 735 p_state_clk_gate_bins=20
 736 p_state_clk_gate_max=1000000000000
 737 p_state_clk_gate_min=1000
 738 power_model=Null
 739 sequential_access=false
 740 size=1048576
 741
 742 [system.cpu.toL2Bus]
 743 type=CoherentXBar
 744 children=snoop_filter
 745 clk_domain=system.cpu_clk_domain
 746 default_p_state=UNDEFINED
 747 eventq_index=0
 748 forward_latency=0
 749 frontend_latency=1
 750 p_state_clk_gate_bins=20
 751 p_state_clk_gate_max=1000000000000
 752 p_state_clk_gate_min=1000
 753 point_of_coherency=false
 754 power_model=Null
 755 response_latency=1
 756 snoop_filter=system.cpu.toL2Bus.snoop_filter
 757 snoop_response_latency=1
 758 system=system
 759 use_default_range=false
 760 width=32
 761 master=system.cpu.l2cache.cpu_side
 762 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 763
 764 [system.cpu.toL2Bus.snoop_filter]
 765 type=SnoopFilter
 766 eventq_index=0
 767 lookup_latency=0
 768 max_capacity=8388608
 769 system=system
 770
 771 [system.cpu.tracer]
 772 type=ExeTracer
 773 eventq_index=0
 774
 775 [system.cpu.workload]
 776 type=LiveProcess
 777 cmd=twolf smred
 778 cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing
 779 drivers=
 780 egid=100
 781 env=
 782 errout=cerr
 783 euid=100
 784 eventq_index=0
 785 executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/twolf
 786 gid=100
 787 input=cin
 788 kvmInSE=false
 789 max_stack_size=67108864
 790 output=cout
 791 pid=100
 792 ppid=99
 793 simpoint=0
 794 system=system
 795 uid=100
 796 useArchPT=false
 797
 798 [system.cpu_clk_domain]
 799 type=SrcClockDomain
 800 clock=500
 801 domain_id=-1
 802 eventq_index=0
 803 init_perf_level=0
 804 voltage_domain=system.voltage_domain
 805
 806 [system.dvfs_handler]
 807 type=DVFSHandler
 808 domains=
 809 enable=false
 810 eventq_index=0
 811 sys_clk_domain=system.clk_domain
 812 transition_latency=100000000
 813
 814 [system.membus]
 815 type=CoherentXBar
 816 children=snoop_filter
 817 clk_domain=system.clk_domain
 818 default_p_state=UNDEFINED
 819 eventq_index=0
 820 forward_latency=4
 821 frontend_latency=3
 822 p_state_clk_gate_bins=20
 823 p_state_clk_gate_max=1000000000000
 824 p_state_clk_gate_min=1000
 825 point_of_coherency=true
 826 power_model=Null
 827 response_latency=2
 828 snoop_filter=system.membus.snoop_filter
 829 snoop_response_latency=4
 830 system=system
 831 use_default_range=false
 832 width=16
 833 master=system.physmem.port
 834 slave=system.system_port system.cpu.l2cache.mem_side
 835
 836 [system.membus.snoop_filter]
 837 type=SnoopFilter
 838 eventq_index=0
 839 lookup_latency=1
 840 max_capacity=8388608
 841 system=system
 842
 843 [system.physmem]
 844 type=DRAMCtrl
 845 IDD0=0.055000
 846 IDD02=0.000000
 847 IDD2N=0.032000
 848 IDD2N2=0.000000
 849 IDD2P0=0.000000
 850 IDD2P02=0.000000
 851 IDD2P1=0.032000
 852 IDD2P12=0.000000
 853 IDD3N=0.038000
 854 IDD3N2=0.000000
 855 IDD3P0=0.000000
 856 IDD3P02=0.000000
 857 IDD3P1=0.038000
 858 IDD3P12=0.000000
 859 IDD4R=0.157000
 860 IDD4R2=0.000000
 861 IDD4W=0.125000
 862 IDD4W2=0.000000
 863 IDD5=0.235000
 864 IDD52=0.000000
 865 IDD6=0.020000
 866 IDD62=0.000000
 867 VDD=1.500000
 868 VDD2=0.000000
 869 activation_limit=4
 870 addr_mapping=RoRaBaCoCh
 871 bank_groups_per_rank=0
 872 banks_per_rank=8
 873 burst_length=8
 874 channels=1
 875 clk_domain=system.clk_domain
 876 conf_table_reported=true
 877 default_p_state=UNDEFINED
 878 device_bus_width=8
 879 device_rowbuffer_size=1024
 880 device_size=536870912
 881 devices_per_rank=8
 882 dll=true
 883 eventq_index=0
 884 in_addr_map=true
 885 kvm_map=true
 886 max_accesses_per_row=16
 887 mem_sched_policy=frfcfs
 888 min_writes_per_switch=16
 889 null=false
 890 p_state_clk_gate_bins=20
 891 p_state_clk_gate_max=1000000000000
 892 p_state_clk_gate_min=1000
 893 page_policy=open_adaptive
 894 power_model=Null
 895 range=0:134217727:0:0:0:0
 896 ranks_per_channel=2
 897 read_buffer_size=32
 898 static_backend_latency=10000
 899 static_frontend_latency=10000
 900 tBURST=5000
 901 tCCD_L=0
 902 tCK=1250
 903 tCL=13750
 904 tCS=2500
 905 tRAS=35000
 906 tRCD=13750
 907 tREFI=7800000
 908 tRFC=260000
 909 tRP=13750
 910 tRRD=6000
 911 tRRD_L=0
 912 tRTP=7500
 913 tRTW=2500
 914 tWR=15000
 915 tWTR=7500
 916 tXAW=30000
 917 tXP=6000
 918 tXPDLL=0
 919 tXS=270000
 920 tXSDLL=0
 921 write_buffer_size=64
 922 write_high_thresh_perc=85
 923 write_low_thresh_perc=50
 924 port=system.membus.master[0]
 925
 926 [system.voltage_domain]
 927 type=VoltageDomain
 928 eventq_index=0
 929 voltage=1.000000
 930