tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 full_system=false
   5 time_sync_enable=false
   6 time_sync_period=100000000000
   7 time_sync_spin_threshold=100000000
   8
   9 [system]
  10 type=System
  11 children=cpu membus physmem
  12 boot_osflags=a
  13 init_param=0
  14 kernel=
  15 load_addr_mask=1099511627775
  16 mem_mode=atomic
  17 memories=system.physmem
  18 num_work_ids=16
  19 physmem=system.physmem
  20 readfile=
  21 symbolfile=
  22 work_begin_ckpt_count=0
  23 work_begin_cpu_id_exit=-1
  24 work_begin_exit_count=0
  25 work_cpus_ckpt_count=0
  26 work_end_ckpt_count=0
  27 work_end_exit_count=0
  28 work_item_id=-1
  29 system_port=system.membus.slave[0]
  30
  31 [system.cpu]
  32 type=DerivO3CPU
  33 children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
  34 BTBEntries=4096
  35 BTBTagSize=16
  36 LFSTSize=1024
  37 LQEntries=32
  38 LSQCheckLoads=true
  39 LSQDepCheckShift=4
  40 RASSize=16
  41 SQEntries=32
  42 SSITSize=1024
  43 activity=0
  44 backComSize=5
  45 cachePorts=200
  46 checker=Null
  47 choiceCtrBits=2
  48 choicePredictorSize=8192
  49 clock=500
  50 commitToDecodeDelay=1
  51 commitToFetchDelay=1
  52 commitToIEWDelay=1
  53 commitToRenameDelay=1
  54 commitWidth=8
  55 cpu_id=0
  56 decodeToFetchDelay=1
  57 decodeToRenameDelay=1
  58 decodeWidth=8
  59 defer_registration=false
  60 dispatchWidth=8
  61 do_checkpoint_insts=true
  62 do_quiesce=true
  63 do_statistics_insts=true
  64 dtb=system.cpu.dtb
  65 fetchToDecodeDelay=1
  66 fetchTrapLatency=1
  67 fetchWidth=8
  68 forwardComSize=5
  69 fuPool=system.cpu.fuPool
  70 function_trace=false
  71 function_trace_start=0
  72 globalCtrBits=2
  73 globalHistoryBits=13
  74 globalPredictorSize=8192
  75 iewToCommitDelay=1
  76 iewToDecodeDelay=1
  77 iewToFetchDelay=1
  78 iewToRenameDelay=1
  79 instShiftAmt=2
  80 interrupts=system.cpu.interrupts
  81 issueToExecuteDelay=1
  82 issueWidth=8
  83 itb=system.cpu.itb
  84 localCtrBits=2
  85 localHistoryBits=11
  86 localHistoryTableSize=2048
  87 localPredictorSize=2048
  88 max_insts_all_threads=0
  89 max_insts_any_thread=0
  90 max_loads_all_threads=0
  91 max_loads_any_thread=0
  92 needsTSO=false
  93 numIQEntries=64
  94 numPhysFloatRegs=256
  95 numPhysIntRegs=256
  96 numROBEntries=192
  97 numRobs=1
  98 numThreads=1
  99 phase=0
 100 predType=tournament
 101 profile=0
 102 progress_interval=0
 103 renameToDecodeDelay=1
 104 renameToFetchDelay=1
 105 renameToIEWDelay=2
 106 renameToROBDelay=1
 107 renameWidth=8
 108 smtCommitPolicy=RoundRobin
 109 smtFetchPolicy=SingleThread
 110 smtIQPolicy=Partitioned
 111 smtIQThreshold=100
 112 smtLSQPolicy=Partitioned
 113 smtLSQThreshold=100
 114 smtNumFetchingThreads=1
 115 smtROBPolicy=Partitioned
 116 smtROBThreshold=100
 117 squashWidth=8
 118 store_set_clear_period=250000
 119 system=system
 120 tracer=system.cpu.tracer
 121 trapLatency=13
 122 wbDepth=1
 123 wbWidth=8
 124 workload=system.cpu.workload
 125 dcache_port=system.cpu.dcache.cpu_side
 126 icache_port=system.cpu.icache.cpu_side
 127
 128 [system.cpu.dcache]
 129 type=BaseCache
 130 addr_ranges=0:18446744073709551615
 131 assoc=2
 132 block_size=64
 133 forward_snoops=true
 134 hash_delay=1
 135 is_top_level=true
 136 latency=1000
 137 max_miss_count=0
 138 mshrs=10
 139 prefetch_on_access=false
 140 prefetcher=Null
 141 prioritizeRequests=false
 142 repl=Null
 143 size=262144
 144 subblock_size=0
 145 system=system
 146 tgts_per_mshr=20
 147 trace_addr=0
 148 two_queue=false
 149 write_buffers=8
 150 cpu_side=system.cpu.dcache_port
 151 mem_side=system.cpu.toL2Bus.slave[1]
 152
 153 [system.cpu.dtb]
 154 type=ArmTLB
 155 children=walker
 156 size=64
 157 walker=system.cpu.dtb.walker
 158
 159 [system.cpu.dtb.walker]
 160 type=ArmTableWalker
 161 max_backoff=100000
 162 min_backoff=0
 163 sys=system
 164 port=system.cpu.toL2Bus.slave[3]
 165
 166 [system.cpu.fuPool]
 167 type=FUPool
 168 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 169 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 170
 171 [system.cpu.fuPool.FUList0]
 172 type=FUDesc
 173 children=opList
 174 count=6
 175 opList=system.cpu.fuPool.FUList0.opList
 176
 177 [system.cpu.fuPool.FUList0.opList]
 178 type=OpDesc
 179 issueLat=1
 180 opClass=IntAlu
 181 opLat=1
 182
 183 [system.cpu.fuPool.FUList1]
 184 type=FUDesc
 185 children=opList0 opList1
 186 count=2
 187 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 188
 189 [system.cpu.fuPool.FUList1.opList0]
 190 type=OpDesc
 191 issueLat=1
 192 opClass=IntMult
 193 opLat=3
 194
 195 [system.cpu.fuPool.FUList1.opList1]
 196 type=OpDesc
 197 issueLat=19
 198 opClass=IntDiv
 199 opLat=20
 200
 201 [system.cpu.fuPool.FUList2]
 202 type=FUDesc
 203 children=opList0 opList1 opList2
 204 count=4
 205 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 206
 207 [system.cpu.fuPool.FUList2.opList0]
 208 type=OpDesc
 209 issueLat=1
 210 opClass=FloatAdd
 211 opLat=2
 212
 213 [system.cpu.fuPool.FUList2.opList1]
 214 type=OpDesc
 215 issueLat=1
 216 opClass=FloatCmp
 217 opLat=2
 218
 219 [system.cpu.fuPool.FUList2.opList2]
 220 type=OpDesc
 221 issueLat=1
 222 opClass=FloatCvt
 223 opLat=2
 224
 225 [system.cpu.fuPool.FUList3]
 226 type=FUDesc
 227 children=opList0 opList1 opList2
 228 count=2
 229 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 230
 231 [system.cpu.fuPool.FUList3.opList0]
 232 type=OpDesc
 233 issueLat=1
 234 opClass=FloatMult
 235 opLat=4
 236
 237 [system.cpu.fuPool.FUList3.opList1]
 238 type=OpDesc
 239 issueLat=12
 240 opClass=FloatDiv
 241 opLat=12
 242
 243 [system.cpu.fuPool.FUList3.opList2]
 244 type=OpDesc
 245 issueLat=24
 246 opClass=FloatSqrt
 247 opLat=24
 248
 249 [system.cpu.fuPool.FUList4]
 250 type=FUDesc
 251 children=opList
 252 count=0
 253 opList=system.cpu.fuPool.FUList4.opList
 254
 255 [system.cpu.fuPool.FUList4.opList]
 256 type=OpDesc
 257 issueLat=1
 258 opClass=MemRead
 259 opLat=1
 260
 261 [system.cpu.fuPool.FUList5]
 262 type=FUDesc
 263 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 264 count=4
 265 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 266
 267 [system.cpu.fuPool.FUList5.opList00]
 268 type=OpDesc
 269 issueLat=1
 270 opClass=SimdAdd
 271 opLat=1
 272
 273 [system.cpu.fuPool.FUList5.opList01]
 274 type=OpDesc
 275 issueLat=1
 276 opClass=SimdAddAcc
 277 opLat=1
 278
 279 [system.cpu.fuPool.FUList5.opList02]
 280 type=OpDesc
 281 issueLat=1
 282 opClass=SimdAlu
 283 opLat=1
 284
 285 [system.cpu.fuPool.FUList5.opList03]
 286 type=OpDesc
 287 issueLat=1
 288 opClass=SimdCmp
 289 opLat=1
 290
 291 [system.cpu.fuPool.FUList5.opList04]
 292 type=OpDesc
 293 issueLat=1
 294 opClass=SimdCvt
 295 opLat=1
 296
 297 [system.cpu.fuPool.FUList5.opList05]
 298 type=OpDesc
 299 issueLat=1
 300 opClass=SimdMisc
 301 opLat=1
 302
 303 [system.cpu.fuPool.FUList5.opList06]
 304 type=OpDesc
 305 issueLat=1
 306 opClass=SimdMult
 307 opLat=1
 308
 309 [system.cpu.fuPool.FUList5.opList07]
 310 type=OpDesc
 311 issueLat=1
 312 opClass=SimdMultAcc
 313 opLat=1
 314
 315 [system.cpu.fuPool.FUList5.opList08]
 316 type=OpDesc
 317 issueLat=1
 318 opClass=SimdShift
 319 opLat=1
 320
 321 [system.cpu.fuPool.FUList5.opList09]
 322 type=OpDesc
 323 issueLat=1
 324 opClass=SimdShiftAcc
 325 opLat=1
 326
 327 [system.cpu.fuPool.FUList5.opList10]
 328 type=OpDesc
 329 issueLat=1
 330 opClass=SimdSqrt
 331 opLat=1
 332
 333 [system.cpu.fuPool.FUList5.opList11]
 334 type=OpDesc
 335 issueLat=1
 336 opClass=SimdFloatAdd
 337 opLat=1
 338
 339 [system.cpu.fuPool.FUList5.opList12]
 340 type=OpDesc
 341 issueLat=1
 342 opClass=SimdFloatAlu
 343 opLat=1
 344
 345 [system.cpu.fuPool.FUList5.opList13]
 346 type=OpDesc
 347 issueLat=1
 348 opClass=SimdFloatCmp
 349 opLat=1
 350
 351 [system.cpu.fuPool.FUList5.opList14]
 352 type=OpDesc
 353 issueLat=1
 354 opClass=SimdFloatCvt
 355 opLat=1
 356
 357 [system.cpu.fuPool.FUList5.opList15]
 358 type=OpDesc
 359 issueLat=1
 360 opClass=SimdFloatDiv
 361 opLat=1
 362
 363 [system.cpu.fuPool.FUList5.opList16]
 364 type=OpDesc
 365 issueLat=1
 366 opClass=SimdFloatMisc
 367 opLat=1
 368
 369 [system.cpu.fuPool.FUList5.opList17]
 370 type=OpDesc
 371 issueLat=1
 372 opClass=SimdFloatMult
 373 opLat=1
 374
 375 [system.cpu.fuPool.FUList5.opList18]
 376 type=OpDesc
 377 issueLat=1
 378 opClass=SimdFloatMultAcc
 379 opLat=1
 380
 381 [system.cpu.fuPool.FUList5.opList19]
 382 type=OpDesc
 383 issueLat=1
 384 opClass=SimdFloatSqrt
 385 opLat=1
 386
 387 [system.cpu.fuPool.FUList6]
 388 type=FUDesc
 389 children=opList
 390 count=0
 391 opList=system.cpu.fuPool.FUList6.opList
 392
 393 [system.cpu.fuPool.FUList6.opList]
 394 type=OpDesc
 395 issueLat=1
 396 opClass=MemWrite
 397 opLat=1
 398
 399 [system.cpu.fuPool.FUList7]
 400 type=FUDesc
 401 children=opList0 opList1
 402 count=4
 403 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 404
 405 [system.cpu.fuPool.FUList7.opList0]
 406 type=OpDesc
 407 issueLat=1
 408 opClass=MemRead
 409 opLat=1
 410
 411 [system.cpu.fuPool.FUList7.opList1]
 412 type=OpDesc
 413 issueLat=1
 414 opClass=MemWrite
 415 opLat=1
 416
 417 [system.cpu.fuPool.FUList8]
 418 type=FUDesc
 419 children=opList
 420 count=1
 421 opList=system.cpu.fuPool.FUList8.opList
 422
 423 [system.cpu.fuPool.FUList8.opList]
 424 type=OpDesc
 425 issueLat=3
 426 opClass=IprAccess
 427 opLat=3
 428
 429 [system.cpu.icache]
 430 type=BaseCache
 431 addr_ranges=0:18446744073709551615
 432 assoc=2
 433 block_size=64
 434 forward_snoops=true
 435 hash_delay=1
 436 is_top_level=true
 437 latency=1000
 438 max_miss_count=0
 439 mshrs=10
 440 prefetch_on_access=false
 441 prefetcher=Null
 442 prioritizeRequests=false
 443 repl=Null
 444 size=131072
 445 subblock_size=0
 446 system=system
 447 tgts_per_mshr=20
 448 trace_addr=0
 449 two_queue=false
 450 write_buffers=8
 451 cpu_side=system.cpu.icache_port
 452 mem_side=system.cpu.toL2Bus.slave[0]
 453
 454 [system.cpu.interrupts]
 455 type=ArmInterrupts
 456
 457 [system.cpu.itb]
 458 type=ArmTLB
 459 children=walker
 460 size=64
 461 walker=system.cpu.itb.walker
 462
 463 [system.cpu.itb.walker]
 464 type=ArmTableWalker
 465 max_backoff=100000
 466 min_backoff=0
 467 sys=system
 468 port=system.cpu.toL2Bus.slave[2]
 469
 470 [system.cpu.l2cache]
 471 type=BaseCache
 472 addr_ranges=0:18446744073709551615
 473 assoc=2
 474 block_size=64
 475 forward_snoops=true
 476 hash_delay=1
 477 is_top_level=false
 478 latency=1000
 479 max_miss_count=0
 480 mshrs=10
 481 prefetch_on_access=false
 482 prefetcher=Null
 483 prioritizeRequests=false
 484 repl=Null
 485 size=2097152
 486 subblock_size=0
 487 system=system
 488 tgts_per_mshr=5
 489 trace_addr=0
 490 two_queue=false
 491 write_buffers=8
 492 cpu_side=system.cpu.toL2Bus.master[0]
 493 mem_side=system.membus.slave[1]
 494
 495 [system.cpu.toL2Bus]
 496 type=Bus
 497 block_size=64
 498 bus_id=0
 499 clock=1000
 500 header_cycles=1
 501 use_default_range=false
 502 width=64
 503 master=system.cpu.l2cache.cpu_side
 504 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 505
 506 [system.cpu.tracer]
 507 type=ExeTracer
 508
 509 [system.cpu.workload]
 510 type=LiveProcess
 511 cmd=twolf smred
 512 cwd=build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing
 513 egid=100
 514 env=
 515 errout=cerr
 516 euid=100
 517 executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/twolf
 518 gid=100
 519 input=cin
 520 max_stack_size=67108864
 521 output=cout
 522 pid=100
 523 ppid=99
 524 simpoint=0
 525 system=system
 526 uid=100
 527
 528 [system.membus]
 529 type=Bus
 530 block_size=64
 531 bus_id=0
 532 clock=1000
 533 header_cycles=1
 534 use_default_range=false
 535 width=64
 536 master=system.physmem.port[0]
 537 slave=system.system_port system.cpu.l2cache.mem_side
 538
 539 [system.physmem]
 540 type=PhysicalMemory
 541 file=
 542 latency=30000
 543 latency_var=0
 544 null=false
 545 range=0:134217727
 546 zero=false
 547 port=system.membus.master[0]
 548