tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 default_p_state=UNDEFINED
  18 eventq_index=0
  19 exit_on_work_items=false
  20 init_param=0
  21 kernel=
  22 kernel_addr_check=true
  23 load_addr_mask=1099511627775
  24 load_offset=0
  25 mem_mode=timing
  26 mem_ranges=
  27 memories=system.physmem
  28 mmap_using_noreserve=false
  29 multi_thread=false
  30 num_work_ids=16
  31 p_state_clk_gate_bins=20
  32 p_state_clk_gate_max=1000000000000
  33 p_state_clk_gate_min=1000
  34 power_model=Null
  35 readfile=
  36 symbolfile=
  37 thermal_components=
  38 thermal_model=Null
  39 work_begin_ckpt_count=0
  40 work_begin_cpu_id_exit=-1
  41 work_begin_exit_count=0
  42 work_cpus_ckpt_count=0
  43 work_end_ckpt_count=0
  44 work_end_exit_count=0
  45 work_item_id=-1
  46 system_port=system.membus.slave[0]
  47
  48 [system.clk_domain]
  49 type=SrcClockDomain
  50 clock=1000
  51 domain_id=-1
  52 eventq_index=0
  53 init_perf_level=0
  54 voltage_domain=system.voltage_domain
  55
  56 [system.cpu]
  57 type=DerivO3CPU
  58 children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
  59 LFSTSize=1024
  60 LQEntries=16
  61 LSQCheckLoads=true
  62 LSQDepCheckShift=0
  63 SQEntries=16
  64 SSITSize=1024
  65 activity=0
  66 backComSize=5
  67 branchPred=system.cpu.branchPred
  68 cacheStorePorts=200
  69 checker=Null
  70 clk_domain=system.cpu_clk_domain
  71 commitToDecodeDelay=1
  72 commitToFetchDelay=1
  73 commitToIEWDelay=1
  74 commitToRenameDelay=1
  75 commitWidth=8
  76 cpu_id=0
  77 decodeToFetchDelay=1
  78 decodeToRenameDelay=2
  79 decodeWidth=3
  80 default_p_state=UNDEFINED
  81 dispatchWidth=6
  82 do_checkpoint_insts=true
  83 do_quiesce=true
  84 do_statistics_insts=true
  85 dstage2_mmu=system.cpu.dstage2_mmu
  86 dtb=system.cpu.dtb
  87 eventq_index=0
  88 fetchBufferSize=16
  89 fetchQueueSize=32
  90 fetchToDecodeDelay=3
  91 fetchTrapLatency=1
  92 fetchWidth=3
  93 forwardComSize=5
  94 fuPool=system.cpu.fuPool
  95 function_trace=false
  96 function_trace_start=0
  97 iewToCommitDelay=1
  98 iewToDecodeDelay=1
  99 iewToFetchDelay=1
 100 iewToRenameDelay=1
 101 interrupts=system.cpu.interrupts
 102 isa=system.cpu.isa
 103 issueToExecuteDelay=1
 104 issueWidth=8
 105 istage2_mmu=system.cpu.istage2_mmu
 106 itb=system.cpu.itb
 107 max_insts_all_threads=0
 108 max_insts_any_thread=0
 109 max_loads_all_threads=0
 110 max_loads_any_thread=0
 111 needsTSO=false
 112 numIQEntries=32
 113 numPhysCCRegs=640
 114 numPhysFloatRegs=192
 115 numPhysIntRegs=128
 116 numROBEntries=40
 117 numRobs=1
 118 numThreads=1
 119 p_state_clk_gate_bins=20
 120 p_state_clk_gate_max=1000000000000
 121 p_state_clk_gate_min=1000
 122 power_model=Null
 123 profile=0
 124 progress_interval=0
 125 renameToDecodeDelay=1
 126 renameToFetchDelay=1
 127 renameToIEWDelay=1
 128 renameToROBDelay=1
 129 renameWidth=3
 130 simpoint_start_insts=
 131 smtCommitPolicy=RoundRobin
 132 smtFetchPolicy=SingleThread
 133 smtIQPolicy=Partitioned
 134 smtIQThreshold=100
 135 smtLSQPolicy=Partitioned
 136 smtLSQThreshold=100
 137 smtNumFetchingThreads=1
 138 smtROBPolicy=Partitioned
 139 smtROBThreshold=100
 140 socket_id=0
 141 squashWidth=8
 142 store_set_clear_period=250000
 143 switched_out=false
 144 syscallRetryLatency=10000
 145 system=system
 146 tracer=system.cpu.tracer
 147 trapLatency=13
 148 wbWidth=8
 149 workload=system.cpu.workload
 150 dcache_port=system.cpu.dcache.cpu_side
 151 icache_port=system.cpu.icache.cpu_side
 152
 153 [system.cpu.branchPred]
 154 type=BiModeBP
 155 BTBEntries=2048
 156 BTBTagSize=18
 157 RASSize=16
 158 choiceCtrBits=2
 159 choicePredictorSize=8192
 160 eventq_index=0
 161 globalCtrBits=2
 162 globalPredictorSize=8192
 163 indirectHashGHR=true
 164 indirectHashTargets=true
 165 indirectPathLength=3
 166 indirectSets=256
 167 indirectTagSize=16
 168 indirectWays=2
 169 instShiftAmt=2
 170 numThreads=1
 171 useIndirect=true
 172
 173 [system.cpu.dcache]
 174 type=Cache
 175 children=tags
 176 addr_ranges=0:18446744073709551615:0:0:0:0
 177 assoc=2
 178 clk_domain=system.cpu_clk_domain
 179 clusivity=mostly_incl
 180 data_latency=2
 181 default_p_state=UNDEFINED
 182 demand_mshr_reserve=1
 183 eventq_index=0
 184 is_read_only=false
 185 max_miss_count=0
 186 mshrs=6
 187 p_state_clk_gate_bins=20
 188 p_state_clk_gate_max=1000000000000
 189 p_state_clk_gate_min=1000
 190 power_model=Null
 191 prefetch_on_access=false
 192 prefetcher=Null
 193 response_latency=2
 194 sequential_access=false
 195 size=32768
 196 system=system
 197 tag_latency=2
 198 tags=system.cpu.dcache.tags
 199 tgts_per_mshr=8
 200 write_buffers=16
 201 writeback_clean=true
 202 cpu_side=system.cpu.dcache_port
 203 mem_side=system.cpu.toL2Bus.slave[1]
 204
 205 [system.cpu.dcache.tags]
 206 type=LRU
 207 assoc=2
 208 block_size=64
 209 clk_domain=system.cpu_clk_domain
 210 data_latency=2
 211 default_p_state=UNDEFINED
 212 eventq_index=0
 213 p_state_clk_gate_bins=20
 214 p_state_clk_gate_max=1000000000000
 215 p_state_clk_gate_min=1000
 216 power_model=Null
 217 sequential_access=false
 218 size=32768
 219 tag_latency=2
 220
 221 [system.cpu.dstage2_mmu]
 222 type=ArmStage2MMU
 223 children=stage2_tlb
 224 eventq_index=0
 225 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
 226 sys=system
 227 tlb=system.cpu.dtb
 228
 229 [system.cpu.dstage2_mmu.stage2_tlb]
 230 type=ArmTLB
 231 children=walker
 232 eventq_index=0
 233 is_stage2=true
 234 size=32
 235 walker=system.cpu.dstage2_mmu.stage2_tlb.walker
 236
 237 [system.cpu.dstage2_mmu.stage2_tlb.walker]
 238 type=ArmTableWalker
 239 clk_domain=system.cpu_clk_domain
 240 default_p_state=UNDEFINED
 241 eventq_index=0
 242 is_stage2=true
 243 num_squash_per_cycle=2
 244 p_state_clk_gate_bins=20
 245 p_state_clk_gate_max=1000000000000
 246 p_state_clk_gate_min=1000
 247 power_model=Null
 248 sys=system
 249
 250 [system.cpu.dtb]
 251 type=ArmTLB
 252 children=walker
 253 eventq_index=0
 254 is_stage2=false
 255 size=64
 256 walker=system.cpu.dtb.walker
 257
 258 [system.cpu.dtb.walker]
 259 type=ArmTableWalker
 260 clk_domain=system.cpu_clk_domain
 261 default_p_state=UNDEFINED
 262 eventq_index=0
 263 is_stage2=false
 264 num_squash_per_cycle=2
 265 p_state_clk_gate_bins=20
 266 p_state_clk_gate_max=1000000000000
 267 p_state_clk_gate_min=1000
 268 power_model=Null
 269 sys=system
 270 port=system.cpu.toL2Bus.slave[3]
 271
 272 [system.cpu.fuPool]
 273 type=FUPool
 274 children=FUList0 FUList1 FUList2 FUList3 FUList4
 275 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
 276 eventq_index=0
 277
 278 [system.cpu.fuPool.FUList0]
 279 type=FUDesc
 280 children=opList
 281 count=2
 282 eventq_index=0
 283 opList=system.cpu.fuPool.FUList0.opList
 284
 285 [system.cpu.fuPool.FUList0.opList]
 286 type=OpDesc
 287 eventq_index=0
 288 opClass=IntAlu
 289 opLat=1
 290 pipelined=true
 291
 292 [system.cpu.fuPool.FUList1]
 293 type=FUDesc
 294 children=opList0 opList1 opList2
 295 count=1
 296 eventq_index=0
 297 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
 298
 299 [system.cpu.fuPool.FUList1.opList0]
 300 type=OpDesc
 301 eventq_index=0
 302 opClass=IntMult
 303 opLat=3
 304 pipelined=true
 305
 306 [system.cpu.fuPool.FUList1.opList1]
 307 type=OpDesc
 308 eventq_index=0
 309 opClass=IntDiv
 310 opLat=12
 311 pipelined=false
 312
 313 [system.cpu.fuPool.FUList1.opList2]
 314 type=OpDesc
 315 eventq_index=0
 316 opClass=IprAccess
 317 opLat=3
 318 pipelined=true
 319
 320 [system.cpu.fuPool.FUList2]
 321 type=FUDesc
 322 children=opList0 opList1
 323 count=1
 324 eventq_index=0
 325 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1
 326
 327 [system.cpu.fuPool.FUList2.opList0]
 328 type=OpDesc
 329 eventq_index=0
 330 opClass=MemRead
 331 opLat=2
 332 pipelined=true
 333
 334 [system.cpu.fuPool.FUList2.opList1]
 335 type=OpDesc
 336 eventq_index=0
 337 opClass=FloatMemRead
 338 opLat=2
 339 pipelined=true
 340
 341 [system.cpu.fuPool.FUList3]
 342 type=FUDesc
 343 children=opList0 opList1
 344 count=1
 345 eventq_index=0
 346 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1
 347
 348 [system.cpu.fuPool.FUList3.opList0]
 349 type=OpDesc
 350 eventq_index=0
 351 opClass=MemWrite
 352 opLat=2
 353 pipelined=true
 354
 355 [system.cpu.fuPool.FUList3.opList1]
 356 type=OpDesc
 357 eventq_index=0
 358 opClass=FloatMemWrite
 359 opLat=2
 360 pipelined=true
 361
 362 [system.cpu.fuPool.FUList4]
 363 type=FUDesc
 364 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27
 365 count=2
 366 eventq_index=0
 367 opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27
 368
 369 [system.cpu.fuPool.FUList4.opList00]
 370 type=OpDesc
 371 eventq_index=0
 372 opClass=SimdAdd
 373 opLat=4
 374 pipelined=true
 375
 376 [system.cpu.fuPool.FUList4.opList01]
 377 type=OpDesc
 378 eventq_index=0
 379 opClass=SimdAddAcc
 380 opLat=4
 381 pipelined=true
 382
 383 [system.cpu.fuPool.FUList4.opList02]
 384 type=OpDesc
 385 eventq_index=0
 386 opClass=SimdAlu
 387 opLat=4
 388 pipelined=true
 389
 390 [system.cpu.fuPool.FUList4.opList03]
 391 type=OpDesc
 392 eventq_index=0
 393 opClass=SimdCmp
 394 opLat=4
 395 pipelined=true
 396
 397 [system.cpu.fuPool.FUList4.opList04]
 398 type=OpDesc
 399 eventq_index=0
 400 opClass=SimdCvt
 401 opLat=3
 402 pipelined=true
 403
 404 [system.cpu.fuPool.FUList4.opList05]
 405 type=OpDesc
 406 eventq_index=0
 407 opClass=SimdMisc
 408 opLat=3
 409 pipelined=true
 410
 411 [system.cpu.fuPool.FUList4.opList06]
 412 type=OpDesc
 413 eventq_index=0
 414 opClass=SimdMult
 415 opLat=5
 416 pipelined=true
 417
 418 [system.cpu.fuPool.FUList4.opList07]
 419 type=OpDesc
 420 eventq_index=0
 421 opClass=SimdMultAcc
 422 opLat=5
 423 pipelined=true
 424
 425 [system.cpu.fuPool.FUList4.opList08]
 426 type=OpDesc
 427 eventq_index=0
 428 opClass=SimdShift
 429 opLat=3
 430 pipelined=true
 431
 432 [system.cpu.fuPool.FUList4.opList09]
 433 type=OpDesc
 434 eventq_index=0
 435 opClass=SimdShiftAcc
 436 opLat=3
 437 pipelined=true
 438
 439 [system.cpu.fuPool.FUList4.opList10]
 440 type=OpDesc
 441 eventq_index=0
 442 opClass=SimdSqrt
 443 opLat=9
 444 pipelined=true
 445
 446 [system.cpu.fuPool.FUList4.opList11]
 447 type=OpDesc
 448 eventq_index=0
 449 opClass=SimdFloatAdd
 450 opLat=5
 451 pipelined=true
 452
 453 [system.cpu.fuPool.FUList4.opList12]
 454 type=OpDesc
 455 eventq_index=0
 456 opClass=SimdFloatAlu
 457 opLat=5
 458 pipelined=true
 459
 460 [system.cpu.fuPool.FUList4.opList13]
 461 type=OpDesc
 462 eventq_index=0
 463 opClass=SimdFloatCmp
 464 opLat=3
 465 pipelined=true
 466
 467 [system.cpu.fuPool.FUList4.opList14]
 468 type=OpDesc
 469 eventq_index=0
 470 opClass=SimdFloatCvt
 471 opLat=3
 472 pipelined=true
 473
 474 [system.cpu.fuPool.FUList4.opList15]
 475 type=OpDesc
 476 eventq_index=0
 477 opClass=SimdFloatDiv
 478 opLat=3
 479 pipelined=true
 480
 481 [system.cpu.fuPool.FUList4.opList16]
 482 type=OpDesc
 483 eventq_index=0
 484 opClass=SimdFloatMisc
 485 opLat=3
 486 pipelined=true
 487
 488 [system.cpu.fuPool.FUList4.opList17]
 489 type=OpDesc
 490 eventq_index=0
 491 opClass=SimdFloatMult
 492 opLat=3
 493 pipelined=true
 494
 495 [system.cpu.fuPool.FUList4.opList18]
 496 type=OpDesc
 497 eventq_index=0
 498 opClass=SimdFloatMultAcc
 499 opLat=5
 500 pipelined=true
 501
 502 [system.cpu.fuPool.FUList4.opList19]
 503 type=OpDesc
 504 eventq_index=0
 505 opClass=SimdFloatSqrt
 506 opLat=9
 507 pipelined=true
 508
 509 [system.cpu.fuPool.FUList4.opList20]
 510 type=OpDesc
 511 eventq_index=0
 512 opClass=FloatAdd
 513 opLat=5
 514 pipelined=true
 515
 516 [system.cpu.fuPool.FUList4.opList21]
 517 type=OpDesc
 518 eventq_index=0
 519 opClass=FloatCmp
 520 opLat=5
 521 pipelined=true
 522
 523 [system.cpu.fuPool.FUList4.opList22]
 524 type=OpDesc
 525 eventq_index=0
 526 opClass=FloatCvt
 527 opLat=5
 528 pipelined=true
 529
 530 [system.cpu.fuPool.FUList4.opList23]
 531 type=OpDesc
 532 eventq_index=0
 533 opClass=FloatDiv
 534 opLat=9
 535 pipelined=false
 536
 537 [system.cpu.fuPool.FUList4.opList24]
 538 type=OpDesc
 539 eventq_index=0
 540 opClass=FloatSqrt
 541 opLat=33
 542 pipelined=false
 543
 544 [system.cpu.fuPool.FUList4.opList25]
 545 type=OpDesc
 546 eventq_index=0
 547 opClass=FloatMult
 548 opLat=4
 549 pipelined=true
 550
 551 [system.cpu.fuPool.FUList4.opList26]
 552 type=OpDesc
 553 eventq_index=0
 554 opClass=FloatMultAcc
 555 opLat=5
 556 pipelined=true
 557
 558 [system.cpu.fuPool.FUList4.opList27]
 559 type=OpDesc
 560 eventq_index=0
 561 opClass=FloatMisc
 562 opLat=3
 563 pipelined=true
 564
 565 [system.cpu.icache]
 566 type=Cache
 567 children=tags
 568 addr_ranges=0:18446744073709551615:0:0:0:0
 569 assoc=2
 570 clk_domain=system.cpu_clk_domain
 571 clusivity=mostly_incl
 572 data_latency=1
 573 default_p_state=UNDEFINED
 574 demand_mshr_reserve=1
 575 eventq_index=0
 576 is_read_only=true
 577 max_miss_count=0
 578 mshrs=2
 579 p_state_clk_gate_bins=20
 580 p_state_clk_gate_max=1000000000000
 581 p_state_clk_gate_min=1000
 582 power_model=Null
 583 prefetch_on_access=false
 584 prefetcher=Null
 585 response_latency=1
 586 sequential_access=false
 587 size=32768
 588 system=system
 589 tag_latency=1
 590 tags=system.cpu.icache.tags
 591 tgts_per_mshr=8
 592 write_buffers=8
 593 writeback_clean=true
 594 cpu_side=system.cpu.icache_port
 595 mem_side=system.cpu.toL2Bus.slave[0]
 596
 597 [system.cpu.icache.tags]
 598 type=LRU
 599 assoc=2
 600 block_size=64
 601 clk_domain=system.cpu_clk_domain
 602 data_latency=1
 603 default_p_state=UNDEFINED
 604 eventq_index=0
 605 p_state_clk_gate_bins=20
 606 p_state_clk_gate_max=1000000000000
 607 p_state_clk_gate_min=1000
 608 power_model=Null
 609 sequential_access=false
 610 size=32768
 611 tag_latency=1
 612
 613 [system.cpu.interrupts]
 614 type=ArmInterrupts
 615 eventq_index=0
 616
 617 [system.cpu.isa]
 618 type=ArmISA
 619 decoderFlavour=Generic
 620 eventq_index=0
 621 fpsid=1090793632
 622 id_aa64afr0_el1=0
 623 id_aa64afr1_el1=0
 624 id_aa64dfr0_el1=1052678
 625 id_aa64dfr1_el1=0
 626 id_aa64isar0_el1=0
 627 id_aa64isar1_el1=0
 628 id_aa64mmfr0_el1=15728642
 629 id_aa64mmfr1_el1=0
 630 id_isar0=34607377
 631 id_isar1=34677009
 632 id_isar2=555950401
 633 id_isar3=17899825
 634 id_isar4=268501314
 635 id_isar5=0
 636 id_mmfr0=270536963
 637 id_mmfr1=0
 638 id_mmfr2=19070976
 639 id_mmfr3=34611729
 640 midr=1091551472
 641 pmu=Null
 642 system=system
 643
 644 [system.cpu.istage2_mmu]
 645 type=ArmStage2MMU
 646 children=stage2_tlb
 647 eventq_index=0
 648 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
 649 sys=system
 650 tlb=system.cpu.itb
 651
 652 [system.cpu.istage2_mmu.stage2_tlb]
 653 type=ArmTLB
 654 children=walker
 655 eventq_index=0
 656 is_stage2=true
 657 size=32
 658 walker=system.cpu.istage2_mmu.stage2_tlb.walker
 659
 660 [system.cpu.istage2_mmu.stage2_tlb.walker]
 661 type=ArmTableWalker
 662 clk_domain=system.cpu_clk_domain
 663 default_p_state=UNDEFINED
 664 eventq_index=0
 665 is_stage2=true
 666 num_squash_per_cycle=2
 667 p_state_clk_gate_bins=20
 668 p_state_clk_gate_max=1000000000000
 669 p_state_clk_gate_min=1000
 670 power_model=Null
 671 sys=system
 672
 673 [system.cpu.itb]
 674 type=ArmTLB
 675 children=walker
 676 eventq_index=0
 677 is_stage2=false
 678 size=64
 679 walker=system.cpu.itb.walker
 680
 681 [system.cpu.itb.walker]
 682 type=ArmTableWalker
 683 clk_domain=system.cpu_clk_domain
 684 default_p_state=UNDEFINED
 685 eventq_index=0
 686 is_stage2=false
 687 num_squash_per_cycle=2
 688 p_state_clk_gate_bins=20
 689 p_state_clk_gate_max=1000000000000
 690 p_state_clk_gate_min=1000
 691 power_model=Null
 692 sys=system
 693 port=system.cpu.toL2Bus.slave[2]
 694
 695 [system.cpu.l2cache]
 696 type=Cache
 697 children=prefetcher tags
 698 addr_ranges=0:18446744073709551615:0:0:0:0
 699 assoc=16
 700 clk_domain=system.cpu_clk_domain
 701 clusivity=mostly_excl
 702 data_latency=12
 703 default_p_state=UNDEFINED
 704 demand_mshr_reserve=1
 705 eventq_index=0
 706 is_read_only=false
 707 max_miss_count=0
 708 mshrs=16
 709 p_state_clk_gate_bins=20
 710 p_state_clk_gate_max=1000000000000
 711 p_state_clk_gate_min=1000
 712 power_model=Null
 713 prefetch_on_access=true
 714 prefetcher=system.cpu.l2cache.prefetcher
 715 response_latency=12
 716 sequential_access=false
 717 size=1048576
 718 system=system
 719 tag_latency=12
 720 tags=system.cpu.l2cache.tags
 721 tgts_per_mshr=8
 722 write_buffers=8
 723 writeback_clean=false
 724 cpu_side=system.cpu.toL2Bus.master[0]
 725 mem_side=system.membus.slave[1]
 726
 727 [system.cpu.l2cache.prefetcher]
 728 type=StridePrefetcher
 729 cache_snoop=false
 730 clk_domain=system.cpu_clk_domain
 731 default_p_state=UNDEFINED
 732 degree=8
 733 eventq_index=0
 734 latency=1
 735 max_conf=7
 736 min_conf=0
 737 on_data=true
 738 on_inst=true
 739 on_miss=false
 740 on_read=true
 741 on_write=true
 742 p_state_clk_gate_bins=20
 743 p_state_clk_gate_max=1000000000000
 744 p_state_clk_gate_min=1000
 745 power_model=Null
 746 queue_filter=true
 747 queue_size=32
 748 queue_squash=true
 749 start_conf=4
 750 sys=system
 751 table_assoc=4
 752 table_sets=16
 753 tag_prefetch=true
 754 thresh_conf=4
 755 use_master_id=true
 756
 757 [system.cpu.l2cache.tags]
 758 type=RandomRepl
 759 assoc=16
 760 block_size=64
 761 clk_domain=system.cpu_clk_domain
 762 data_latency=12
 763 default_p_state=UNDEFINED
 764 eventq_index=0
 765 p_state_clk_gate_bins=20
 766 p_state_clk_gate_max=1000000000000
 767 p_state_clk_gate_min=1000
 768 power_model=Null
 769 sequential_access=false
 770 size=1048576
 771 tag_latency=12
 772
 773 [system.cpu.toL2Bus]
 774 type=CoherentXBar
 775 children=snoop_filter
 776 clk_domain=system.cpu_clk_domain
 777 default_p_state=UNDEFINED
 778 eventq_index=0
 779 forward_latency=0
 780 frontend_latency=1
 781 p_state_clk_gate_bins=20
 782 p_state_clk_gate_max=1000000000000
 783 p_state_clk_gate_min=1000
 784 point_of_coherency=false
 785 power_model=Null
 786 response_latency=1
 787 snoop_filter=system.cpu.toL2Bus.snoop_filter
 788 snoop_response_latency=1
 789 system=system
 790 use_default_range=false
 791 width=32
 792 master=system.cpu.l2cache.cpu_side
 793 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 794
 795 [system.cpu.toL2Bus.snoop_filter]
 796 type=SnoopFilter
 797 eventq_index=0
 798 lookup_latency=0
 799 max_capacity=8388608
 800 system=system
 801
 802 [system.cpu.tracer]
 803 type=ExeTracer
 804 eventq_index=0
 805
 806 [system.cpu.workload]
 807 type=Process
 808 cmd=twolf smred
 809 cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing
 810 drivers=
 811 egid=100
 812 env=
 813 errout=cerr
 814 euid=100
 815 eventq_index=0
 816 executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/twolf
 817 gid=100
 818 input=cin
 819 kvmInSE=false
 820 maxStackSize=67108864
 821 output=cout
 822 pgid=100
 823 pid=100
 824 ppid=0
 825 simpoint=0
 826 system=system
 827 uid=100
 828 useArchPT=false
 829
 830 [system.cpu_clk_domain]
 831 type=SrcClockDomain
 832 clock=500
 833 domain_id=-1
 834 eventq_index=0
 835 init_perf_level=0
 836 voltage_domain=system.voltage_domain
 837
 838 [system.dvfs_handler]
 839 type=DVFSHandler
 840 domains=
 841 enable=false
 842 eventq_index=0
 843 sys_clk_domain=system.clk_domain
 844 transition_latency=100000000
 845
 846 [system.membus]
 847 type=CoherentXBar
 848 children=snoop_filter
 849 clk_domain=system.clk_domain
 850 default_p_state=UNDEFINED
 851 eventq_index=0
 852 forward_latency=4
 853 frontend_latency=3
 854 p_state_clk_gate_bins=20
 855 p_state_clk_gate_max=1000000000000
 856 p_state_clk_gate_min=1000
 857 point_of_coherency=true
 858 power_model=Null
 859 response_latency=2
 860 snoop_filter=system.membus.snoop_filter
 861 snoop_response_latency=4
 862 system=system
 863 use_default_range=false
 864 width=16
 865 master=system.physmem.port
 866 slave=system.system_port system.cpu.l2cache.mem_side
 867
 868 [system.membus.snoop_filter]
 869 type=SnoopFilter
 870 eventq_index=0
 871 lookup_latency=1
 872 max_capacity=8388608
 873 system=system
 874
 875 [system.physmem]
 876 type=DRAMCtrl
 877 IDD0=0.055000
 878 IDD02=0.000000
 879 IDD2N=0.032000
 880 IDD2N2=0.000000
 881 IDD2P0=0.000000
 882 IDD2P02=0.000000
 883 IDD2P1=0.032000
 884 IDD2P12=0.000000
 885 IDD3N=0.038000
 886 IDD3N2=0.000000
 887 IDD3P0=0.000000
 888 IDD3P02=0.000000
 889 IDD3P1=0.038000
 890 IDD3P12=0.000000
 891 IDD4R=0.157000
 892 IDD4R2=0.000000
 893 IDD4W=0.125000
 894 IDD4W2=0.000000
 895 IDD5=0.235000
 896 IDD52=0.000000
 897 IDD6=0.020000
 898 IDD62=0.000000
 899 VDD=1.500000
 900 VDD2=0.000000
 901 activation_limit=4
 902 addr_mapping=RoRaBaCoCh
 903 bank_groups_per_rank=0
 904 banks_per_rank=8
 905 burst_length=8
 906 channels=1
 907 clk_domain=system.clk_domain
 908 conf_table_reported=true
 909 default_p_state=UNDEFINED
 910 device_bus_width=8
 911 device_rowbuffer_size=1024
 912 device_size=536870912
 913 devices_per_rank=8
 914 dll=true
 915 eventq_index=0
 916 in_addr_map=true
 917 kvm_map=true
 918 max_accesses_per_row=16
 919 mem_sched_policy=frfcfs
 920 min_writes_per_switch=16
 921 null=false
 922 p_state_clk_gate_bins=20
 923 p_state_clk_gate_max=1000000000000
 924 p_state_clk_gate_min=1000
 925 page_policy=open_adaptive
 926 power_model=Null
 927 range=0:134217727:0:0:0:0
 928 ranks_per_channel=2
 929 read_buffer_size=32
 930 static_backend_latency=10000
 931 static_frontend_latency=10000
 932 tBURST=5000
 933 tCCD_L=0
 934 tCK=1250
 935 tCL=13750
 936 tCS=2500
 937 tRAS=35000
 938 tRCD=13750
 939 tREFI=7800000
 940 tRFC=260000
 941 tRP=13750
 942 tRRD=6000
 943 tRRD_L=0
 944 tRTP=7500
 945 tRTW=2500
 946 tWR=15000
 947 tWTR=7500
 948 tXAW=30000
 949 tXP=6000
 950 tXPDLL=0
 951 tXS=270000
 952 tXSDLL=0
 953 write_buffer_size=64
 954 write_high_thresh_perc=85
 955 write_low_thresh_perc=50
 956 port=system.membus.master[0]
 957
 958 [system.voltage_domain]
 959 type=VoltageDomain
 960 eventq_index=0
 961 voltage=1.000000
 962