tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 full_system=false
   5 time_sync_enable=false
   6 time_sync_period=100000000000
   7 time_sync_spin_threshold=100000000
   8
   9 [system]
  10 type=System
  11 children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
  12 boot_osflags=a
  13 cache_line_size=64
  14 clk_domain=system.clk_domain
  15 init_param=0
  16 kernel=
  17 load_addr_mask=1099511627775
  18 mem_mode=timing
  19 mem_ranges=
  20 memories=system.physmem
  21 num_work_ids=16
  22 readfile=
  23 symbolfile=
  24 work_begin_ckpt_count=0
  25 work_begin_cpu_id_exit=-1
  26 work_begin_exit_count=0
  27 work_cpus_ckpt_count=0
  28 work_end_ckpt_count=0
  29 work_end_exit_count=0
  30 work_item_id=-1
  31 system_port=system.membus.slave[0]
  32
  33 [system.clk_domain]
  34 type=SrcClockDomain
  35 clock=1000
  36 voltage_domain=system.voltage_domain
  37
  38 [system.cpu]
  39 type=DerivO3CPU
  40 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
  41 LFSTSize=1024
  42 LQEntries=32
  43 LSQCheckLoads=true
  44 LSQDepCheckShift=4
  45 SQEntries=32
  46 SSITSize=1024
  47 activity=0
  48 backComSize=5
  49 branchPred=system.cpu.branchPred
  50 cachePorts=200
  51 checker=Null
  52 clk_domain=system.cpu_clk_domain
  53 commitToDecodeDelay=1
  54 commitToFetchDelay=1
  55 commitToIEWDelay=1
  56 commitToRenameDelay=1
  57 commitWidth=8
  58 cpu_id=0
  59 decodeToFetchDelay=1
  60 decodeToRenameDelay=1
  61 decodeWidth=8
  62 dispatchWidth=8
  63 do_checkpoint_insts=true
  64 do_quiesce=true
  65 do_statistics_insts=true
  66 dtb=system.cpu.dtb
  67 fetchToDecodeDelay=1
  68 fetchTrapLatency=1
  69 fetchWidth=8
  70 forwardComSize=5
  71 fuPool=system.cpu.fuPool
  72 function_trace=false
  73 function_trace_start=0
  74 iewToCommitDelay=1
  75 iewToDecodeDelay=1
  76 iewToFetchDelay=1
  77 iewToRenameDelay=1
  78 interrupts=system.cpu.interrupts
  79 isa=system.cpu.isa
  80 issueToExecuteDelay=1
  81 issueWidth=8
  82 itb=system.cpu.itb
  83 max_insts_all_threads=0
  84 max_insts_any_thread=0
  85 max_loads_all_threads=0
  86 max_loads_any_thread=0
  87 needsTSO=false
  88 numIQEntries=64
  89 numPhysCCRegs=0
  90 numPhysFloatRegs=256
  91 numPhysIntRegs=256
  92 numROBEntries=192
  93 numRobs=1
  94 numThreads=1
  95 profile=0
  96 progress_interval=0
  97 renameToDecodeDelay=1
  98 renameToFetchDelay=1
  99 renameToIEWDelay=2
 100 renameToROBDelay=1
 101 renameWidth=8
 102 simpoint_start_insts=
 103 smtCommitPolicy=RoundRobin
 104 smtFetchPolicy=SingleThread
 105 smtIQPolicy=Partitioned
 106 smtIQThreshold=100
 107 smtLSQPolicy=Partitioned
 108 smtLSQThreshold=100
 109 smtNumFetchingThreads=1
 110 smtROBPolicy=Partitioned
 111 smtROBThreshold=100
 112 squashWidth=8
 113 store_set_clear_period=250000
 114 switched_out=false
 115 system=system
 116 tracer=system.cpu.tracer
 117 trapLatency=13
 118 wbDepth=1
 119 wbWidth=8
 120 workload=system.cpu.workload
 121 dcache_port=system.cpu.dcache.cpu_side
 122 icache_port=system.cpu.icache.cpu_side
 123
 124 [system.cpu.branchPred]
 125 type=BranchPredictor
 126 BTBEntries=4096
 127 BTBTagSize=16
 128 RASSize=16
 129 choiceCtrBits=2
 130 choicePredictorSize=8192
 131 globalCtrBits=2
 132 globalPredictorSize=8192
 133 instShiftAmt=2
 134 localCtrBits=2
 135 localHistoryTableSize=2048
 136 localPredictorSize=2048
 137 numThreads=1
 138 predType=tournament
 139
 140 [system.cpu.dcache]
 141 type=BaseCache
 142 children=tags
 143 addr_ranges=0:18446744073709551615
 144 assoc=2
 145 clk_domain=system.cpu_clk_domain
 146 forward_snoops=true
 147 hit_latency=2
 148 is_top_level=true
 149 max_miss_count=0
 150 mshrs=4
 151 prefetch_on_access=false
 152 prefetcher=Null
 153 response_latency=2
 154 size=262144
 155 system=system
 156 tags=system.cpu.dcache.tags
 157 tgts_per_mshr=20
 158 two_queue=false
 159 write_buffers=8
 160 cpu_side=system.cpu.dcache_port
 161 mem_side=system.cpu.toL2Bus.slave[1]
 162
 163 [system.cpu.dcache.tags]
 164 type=LRU
 165 assoc=2
 166 block_size=64
 167 clk_domain=system.cpu_clk_domain
 168 hit_latency=2
 169 size=262144
 170
 171 [system.cpu.dtb]
 172 type=ArmTLB
 173 children=walker
 174 size=64
 175 walker=system.cpu.dtb.walker
 176
 177 [system.cpu.dtb.walker]
 178 type=ArmTableWalker
 179 clk_domain=system.cpu_clk_domain
 180 num_squash_per_cycle=2
 181 sys=system
 182 port=system.cpu.toL2Bus.slave[3]
 183
 184 [system.cpu.fuPool]
 185 type=FUPool
 186 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 187 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 188
 189 [system.cpu.fuPool.FUList0]
 190 type=FUDesc
 191 children=opList
 192 count=6
 193 opList=system.cpu.fuPool.FUList0.opList
 194
 195 [system.cpu.fuPool.FUList0.opList]
 196 type=OpDesc
 197 issueLat=1
 198 opClass=IntAlu
 199 opLat=1
 200
 201 [system.cpu.fuPool.FUList1]
 202 type=FUDesc
 203 children=opList0 opList1
 204 count=2
 205 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 206
 207 [system.cpu.fuPool.FUList1.opList0]
 208 type=OpDesc
 209 issueLat=1
 210 opClass=IntMult
 211 opLat=3
 212
 213 [system.cpu.fuPool.FUList1.opList1]
 214 type=OpDesc
 215 issueLat=19
 216 opClass=IntDiv
 217 opLat=20
 218
 219 [system.cpu.fuPool.FUList2]
 220 type=FUDesc
 221 children=opList0 opList1 opList2
 222 count=4
 223 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 224
 225 [system.cpu.fuPool.FUList2.opList0]
 226 type=OpDesc
 227 issueLat=1
 228 opClass=FloatAdd
 229 opLat=2
 230
 231 [system.cpu.fuPool.FUList2.opList1]
 232 type=OpDesc
 233 issueLat=1
 234 opClass=FloatCmp
 235 opLat=2
 236
 237 [system.cpu.fuPool.FUList2.opList2]
 238 type=OpDesc
 239 issueLat=1
 240 opClass=FloatCvt
 241 opLat=2
 242
 243 [system.cpu.fuPool.FUList3]
 244 type=FUDesc
 245 children=opList0 opList1 opList2
 246 count=2
 247 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 248
 249 [system.cpu.fuPool.FUList3.opList0]
 250 type=OpDesc
 251 issueLat=1
 252 opClass=FloatMult
 253 opLat=4
 254
 255 [system.cpu.fuPool.FUList3.opList1]
 256 type=OpDesc
 257 issueLat=12
 258 opClass=FloatDiv
 259 opLat=12
 260
 261 [system.cpu.fuPool.FUList3.opList2]
 262 type=OpDesc
 263 issueLat=24
 264 opClass=FloatSqrt
 265 opLat=24
 266
 267 [system.cpu.fuPool.FUList4]
 268 type=FUDesc
 269 children=opList
 270 count=0
 271 opList=system.cpu.fuPool.FUList4.opList
 272
 273 [system.cpu.fuPool.FUList4.opList]
 274 type=OpDesc
 275 issueLat=1
 276 opClass=MemRead
 277 opLat=1
 278
 279 [system.cpu.fuPool.FUList5]
 280 type=FUDesc
 281 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 282 count=4
 283 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 284
 285 [system.cpu.fuPool.FUList5.opList00]
 286 type=OpDesc
 287 issueLat=1
 288 opClass=SimdAdd
 289 opLat=1
 290
 291 [system.cpu.fuPool.FUList5.opList01]
 292 type=OpDesc
 293 issueLat=1
 294 opClass=SimdAddAcc
 295 opLat=1
 296
 297 [system.cpu.fuPool.FUList5.opList02]
 298 type=OpDesc
 299 issueLat=1
 300 opClass=SimdAlu
 301 opLat=1
 302
 303 [system.cpu.fuPool.FUList5.opList03]
 304 type=OpDesc
 305 issueLat=1
 306 opClass=SimdCmp
 307 opLat=1
 308
 309 [system.cpu.fuPool.FUList5.opList04]
 310 type=OpDesc
 311 issueLat=1
 312 opClass=SimdCvt
 313 opLat=1
 314
 315 [system.cpu.fuPool.FUList5.opList05]
 316 type=OpDesc
 317 issueLat=1
 318 opClass=SimdMisc
 319 opLat=1
 320
 321 [system.cpu.fuPool.FUList5.opList06]
 322 type=OpDesc
 323 issueLat=1
 324 opClass=SimdMult
 325 opLat=1
 326
 327 [system.cpu.fuPool.FUList5.opList07]
 328 type=OpDesc
 329 issueLat=1
 330 opClass=SimdMultAcc
 331 opLat=1
 332
 333 [system.cpu.fuPool.FUList5.opList08]
 334 type=OpDesc
 335 issueLat=1
 336 opClass=SimdShift
 337 opLat=1
 338
 339 [system.cpu.fuPool.FUList5.opList09]
 340 type=OpDesc
 341 issueLat=1
 342 opClass=SimdShiftAcc
 343 opLat=1
 344
 345 [system.cpu.fuPool.FUList5.opList10]
 346 type=OpDesc
 347 issueLat=1
 348 opClass=SimdSqrt
 349 opLat=1
 350
 351 [system.cpu.fuPool.FUList5.opList11]
 352 type=OpDesc
 353 issueLat=1
 354 opClass=SimdFloatAdd
 355 opLat=1
 356
 357 [system.cpu.fuPool.FUList5.opList12]
 358 type=OpDesc
 359 issueLat=1
 360 opClass=SimdFloatAlu
 361 opLat=1
 362
 363 [system.cpu.fuPool.FUList5.opList13]
 364 type=OpDesc
 365 issueLat=1
 366 opClass=SimdFloatCmp
 367 opLat=1
 368
 369 [system.cpu.fuPool.FUList5.opList14]
 370 type=OpDesc
 371 issueLat=1
 372 opClass=SimdFloatCvt
 373 opLat=1
 374
 375 [system.cpu.fuPool.FUList5.opList15]
 376 type=OpDesc
 377 issueLat=1
 378 opClass=SimdFloatDiv
 379 opLat=1
 380
 381 [system.cpu.fuPool.FUList5.opList16]
 382 type=OpDesc
 383 issueLat=1
 384 opClass=SimdFloatMisc
 385 opLat=1
 386
 387 [system.cpu.fuPool.FUList5.opList17]
 388 type=OpDesc
 389 issueLat=1
 390 opClass=SimdFloatMult
 391 opLat=1
 392
 393 [system.cpu.fuPool.FUList5.opList18]
 394 type=OpDesc
 395 issueLat=1
 396 opClass=SimdFloatMultAcc
 397 opLat=1
 398
 399 [system.cpu.fuPool.FUList5.opList19]
 400 type=OpDesc
 401 issueLat=1
 402 opClass=SimdFloatSqrt
 403 opLat=1
 404
 405 [system.cpu.fuPool.FUList6]
 406 type=FUDesc
 407 children=opList
 408 count=0
 409 opList=system.cpu.fuPool.FUList6.opList
 410
 411 [system.cpu.fuPool.FUList6.opList]
 412 type=OpDesc
 413 issueLat=1
 414 opClass=MemWrite
 415 opLat=1
 416
 417 [system.cpu.fuPool.FUList7]
 418 type=FUDesc
 419 children=opList0 opList1
 420 count=4
 421 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 422
 423 [system.cpu.fuPool.FUList7.opList0]
 424 type=OpDesc
 425 issueLat=1
 426 opClass=MemRead
 427 opLat=1
 428
 429 [system.cpu.fuPool.FUList7.opList1]
 430 type=OpDesc
 431 issueLat=1
 432 opClass=MemWrite
 433 opLat=1
 434
 435 [system.cpu.fuPool.FUList8]
 436 type=FUDesc
 437 children=opList
 438 count=1
 439 opList=system.cpu.fuPool.FUList8.opList
 440
 441 [system.cpu.fuPool.FUList8.opList]
 442 type=OpDesc
 443 issueLat=3
 444 opClass=IprAccess
 445 opLat=3
 446
 447 [system.cpu.icache]
 448 type=BaseCache
 449 children=tags
 450 addr_ranges=0:18446744073709551615
 451 assoc=2
 452 clk_domain=system.cpu_clk_domain
 453 forward_snoops=true
 454 hit_latency=2
 455 is_top_level=true
 456 max_miss_count=0
 457 mshrs=4
 458 prefetch_on_access=false
 459 prefetcher=Null
 460 response_latency=2
 461 size=131072
 462 system=system
 463 tags=system.cpu.icache.tags
 464 tgts_per_mshr=20
 465 two_queue=false
 466 write_buffers=8
 467 cpu_side=system.cpu.icache_port
 468 mem_side=system.cpu.toL2Bus.slave[0]
 469
 470 [system.cpu.icache.tags]
 471 type=LRU
 472 assoc=2
 473 block_size=64
 474 clk_domain=system.cpu_clk_domain
 475 hit_latency=2
 476 size=131072
 477
 478 [system.cpu.interrupts]
 479 type=ArmInterrupts
 480
 481 [system.cpu.isa]
 482 type=ArmISA
 483 fpsid=1090793632
 484 id_isar0=34607377
 485 id_isar1=34677009
 486 id_isar2=555950401
 487 id_isar3=17899825
 488 id_isar4=268501314
 489 id_isar5=0
 490 id_mmfr0=3
 491 id_mmfr1=0
 492 id_mmfr2=19070976
 493 id_mmfr3=4027589137
 494 id_pfr0=49
 495 id_pfr1=1
 496 midr=890224640
 497
 498 [system.cpu.itb]
 499 type=ArmTLB
 500 children=walker
 501 size=64
 502 walker=system.cpu.itb.walker
 503
 504 [system.cpu.itb.walker]
 505 type=ArmTableWalker
 506 clk_domain=system.cpu_clk_domain
 507 num_squash_per_cycle=2
 508 sys=system
 509 port=system.cpu.toL2Bus.slave[2]
 510
 511 [system.cpu.l2cache]
 512 type=BaseCache
 513 children=tags
 514 addr_ranges=0:18446744073709551615
 515 assoc=8
 516 clk_domain=system.cpu_clk_domain
 517 forward_snoops=true
 518 hit_latency=20
 519 is_top_level=false
 520 max_miss_count=0
 521 mshrs=20
 522 prefetch_on_access=false
 523 prefetcher=Null
 524 response_latency=20
 525 size=2097152
 526 system=system
 527 tags=system.cpu.l2cache.tags
 528 tgts_per_mshr=12
 529 two_queue=false
 530 write_buffers=8
 531 cpu_side=system.cpu.toL2Bus.master[0]
 532 mem_side=system.membus.slave[1]
 533
 534 [system.cpu.l2cache.tags]
 535 type=LRU
 536 assoc=8
 537 block_size=64
 538 clk_domain=system.cpu_clk_domain
 539 hit_latency=20
 540 size=2097152
 541
 542 [system.cpu.toL2Bus]
 543 type=CoherentBus
 544 clk_domain=system.cpu_clk_domain
 545 header_cycles=1
 546 system=system
 547 use_default_range=false
 548 width=32
 549 master=system.cpu.l2cache.cpu_side
 550 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 551
 552 [system.cpu.tracer]
 553 type=ExeTracer
 554
 555 [system.cpu.workload]
 556 type=LiveProcess
 557 cmd=twolf smred
 558 cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing
 559 egid=100
 560 env=
 561 errout=cerr
 562 euid=100
 563 executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
 564 gid=100
 565 input=cin
 566 max_stack_size=67108864
 567 output=cout
 568 pid=100
 569 ppid=99
 570 simpoint=0
 571 system=system
 572 uid=100
 573
 574 [system.cpu_clk_domain]
 575 type=SrcClockDomain
 576 clock=500
 577 voltage_domain=system.voltage_domain
 578
 579 [system.membus]
 580 type=CoherentBus
 581 clk_domain=system.clk_domain
 582 header_cycles=1
 583 system=system
 584 use_default_range=false
 585 width=8
 586 master=system.physmem.port
 587 slave=system.system_port system.cpu.l2cache.mem_side
 588
 589 [system.physmem]
 590 type=SimpleDRAM
 591 activation_limit=4
 592 addr_mapping=RaBaChCo
 593 banks_per_rank=8
 594 burst_length=8
 595 channels=1
 596 clk_domain=system.clk_domain
 597 conf_table_reported=true
 598 device_bus_width=8
 599 device_rowbuffer_size=1024
 600 devices_per_rank=8
 601 in_addr_map=true
 602 mem_sched_policy=frfcfs
 603 null=false
 604 page_policy=open
 605 range=0:134217727
 606 ranks_per_channel=2
 607 read_buffer_size=32
 608 static_backend_latency=10000
 609 static_frontend_latency=10000
 610 tBURST=5000
 611 tCL=13750
 612 tRCD=13750
 613 tREFI=7800000
 614 tRFC=300000
 615 tRP=13750
 616 tWTR=7500
 617 tXAW=40000
 618 write_buffer_size=32
 619 write_thresh_perc=70
 620 port=system.membus.master[0]
 621
 622 [system.voltage_domain]
 623 type=VoltageDomain
 624 voltage=1.000000
 625