2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.074201 # Number of seconds simulated
4 sim_ticks 74201024500 # Number of ticks simulated
5 final_tick 74201024500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 115322 # Simulator instruction rate (inst/s)
8 host_op_rate 126267 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 49662501 # Simulator tick rate (ticks/s)
10 host_mem_usage 251448 # Number of bytes of host memory used
11 host_seconds 1494.11 # Real time elapsed on the host
12 sim_insts 172303021 # Number of instructions simulated
13 sim_ops 188656503 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 131328 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 111872 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 243200 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 131328 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 131328 # Number of instructions bytes read from this memory
19 system.physmem.num_reads::cpu.inst 2052 # Number of read requests responded to by this memory
20 system.physmem.num_reads::cpu.data 1748 # Number of read requests responded to by this memory
21 system.physmem.num_reads::total 3800 # Number of read requests responded to by this memory
22 system.physmem.bw_read::cpu.inst 1769895 # Total read bandwidth from this memory (bytes/s)
23 system.physmem.bw_read::cpu.data 1507688 # Total read bandwidth from this memory (bytes/s)
24 system.physmem.bw_read::total 3277583 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_inst_read::cpu.inst 1769895 # Instruction read bandwidth from this memory (bytes/s)
26 system.physmem.bw_inst_read::total 1769895 # Instruction read bandwidth from this memory (bytes/s)
27 system.physmem.bw_total::cpu.inst 1769895 # Total bandwidth to/from this memory (bytes/s)
28 system.physmem.bw_total::cpu.data 1507688 # Total bandwidth to/from this memory (bytes/s)
29 system.physmem.bw_total::total 3277583 # Total bandwidth to/from this memory (bytes/s)
30 system.physmem.readReqs 3801 # Total number of read requests accepted by DRAM controller
31 system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
32 system.physmem.readBursts 3801 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
33 system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
34 system.physmem.bytesRead 243200 # Total number of bytes read from memory
35 system.physmem.bytesWritten 0 # Total number of bytes written to memory
36 system.physmem.bytesConsumedRd 243200 # bytesRead derated as per pkt->getSize()
37 system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
38 system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
39 system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed
40 system.physmem.perBankRdReqs::0 308 # Track reads on a per bank basis
41 system.physmem.perBankRdReqs::1 215 # Track reads on a per bank basis
42 system.physmem.perBankRdReqs::2 134 # Track reads on a per bank basis
43 system.physmem.perBankRdReqs::3 308 # Track reads on a per bank basis
44 system.physmem.perBankRdReqs::4 298 # Track reads on a per bank basis
45 system.physmem.perBankRdReqs::5 300 # Track reads on a per bank basis
46 system.physmem.perBankRdReqs::6 261 # Track reads on a per bank basis
47 system.physmem.perBankRdReqs::7 216 # Track reads on a per bank basis
48 system.physmem.perBankRdReqs::8 246 # Track reads on a per bank basis
49 system.physmem.perBankRdReqs::9 215 # Track reads on a per bank basis
50 system.physmem.perBankRdReqs::10 289 # Track reads on a per bank basis
51 system.physmem.perBankRdReqs::11 194 # Track reads on a per bank basis
52 system.physmem.perBankRdReqs::12 191 # Track reads on a per bank basis
53 system.physmem.perBankRdReqs::13 208 # Track reads on a per bank basis
54 system.physmem.perBankRdReqs::14 218 # Track reads on a per bank basis
55 system.physmem.perBankRdReqs::15 200 # Track reads on a per bank basis
56 system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
57 system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
58 system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
59 system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
60 system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
61 system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
62 system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
63 system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
64 system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
65 system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
66 system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
67 system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
68 system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
69 system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
70 system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
71 system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
72 system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
73 system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
74 system.physmem.totGap 74201006000 # Total gap between requests
75 system.physmem.readPktSize::0 0 # Categorize read packet sizes
76 system.physmem.readPktSize::1 0 # Categorize read packet sizes
77 system.physmem.readPktSize::2 0 # Categorize read packet sizes
78 system.physmem.readPktSize::3 0 # Categorize read packet sizes
79 system.physmem.readPktSize::4 0 # Categorize read packet sizes
80 system.physmem.readPktSize::5 0 # Categorize read packet sizes
81 system.physmem.readPktSize::6 3801 # Categorize read packet sizes
82 system.physmem.writePktSize::0 0 # Categorize write packet sizes
83 system.physmem.writePktSize::1 0 # Categorize write packet sizes
84 system.physmem.writePktSize::2 0 # Categorize write packet sizes
85 system.physmem.writePktSize::3 0 # Categorize write packet sizes
86 system.physmem.writePktSize::4 0 # Categorize write packet sizes
87 system.physmem.writePktSize::5 0 # Categorize write packet sizes
88 system.physmem.writePktSize::6 0 # Categorize write packet sizes
89 system.physmem.rdQLenPdf::0 2829 # What read queue length does an incoming req see
90 system.physmem.rdQLenPdf::1 792 # What read queue length does an incoming req see
91 system.physmem.rdQLenPdf::2 136 # What read queue length does an incoming req see
92 system.physmem.rdQLenPdf::3 38 # What read queue length does an incoming req see
93 system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
94 system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
95 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
96 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
97 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
98 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
99 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
100 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
121 system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
122 system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
123 system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
124 system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
125 system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
126 system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
127 system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
128 system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
129 system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
130 system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
131 system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
132 system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
153 system.physmem.bytesPerActivate::samples 389 # Bytes accessed per row activation
154 system.physmem.bytesPerActivate::mean 616.966581 # Bytes accessed per row activation
155 system.physmem.bytesPerActivate::gmean 221.267348 # Bytes accessed per row activation
156 system.physmem.bytesPerActivate::stdev 1216.553816 # Bytes accessed per row activation
157 system.physmem.bytesPerActivate::64-65 139 35.73% 35.73% # Bytes accessed per row activation
158 system.physmem.bytesPerActivate::128-129 59 15.17% 50.90% # Bytes accessed per row activation
159 system.physmem.bytesPerActivate::192-193 33 8.48% 59.38% # Bytes accessed per row activation
160 system.physmem.bytesPerActivate::256-257 24 6.17% 65.55% # Bytes accessed per row activation
161 system.physmem.bytesPerActivate::320-321 15 3.86% 69.41% # Bytes accessed per row activation
162 system.physmem.bytesPerActivate::384-385 13 3.34% 72.75% # Bytes accessed per row activation
163 system.physmem.bytesPerActivate::448-449 4 1.03% 73.78% # Bytes accessed per row activation
164 system.physmem.bytesPerActivate::512-513 7 1.80% 75.58% # Bytes accessed per row activation
165 system.physmem.bytesPerActivate::576-577 5 1.29% 76.86% # Bytes accessed per row activation
166 system.physmem.bytesPerActivate::640-641 8 2.06% 78.92% # Bytes accessed per row activation
167 system.physmem.bytesPerActivate::704-705 4 1.03% 79.95% # Bytes accessed per row activation
168 system.physmem.bytesPerActivate::768-769 4 1.03% 80.98% # Bytes accessed per row activation
169 system.physmem.bytesPerActivate::832-833 3 0.77% 81.75% # Bytes accessed per row activation
170 system.physmem.bytesPerActivate::896-897 3 0.77% 82.52% # Bytes accessed per row activation
171 system.physmem.bytesPerActivate::960-961 5 1.29% 83.80% # Bytes accessed per row activation
172 system.physmem.bytesPerActivate::1024-1025 4 1.03% 84.83% # Bytes accessed per row activation
173 system.physmem.bytesPerActivate::1088-1089 4 1.03% 85.86% # Bytes accessed per row activation
174 system.physmem.bytesPerActivate::1152-1153 1 0.26% 86.12% # Bytes accessed per row activation
175 system.physmem.bytesPerActivate::1216-1217 1 0.26% 86.38% # Bytes accessed per row activation
176 system.physmem.bytesPerActivate::1280-1281 3 0.77% 87.15% # Bytes accessed per row activation
177 system.physmem.bytesPerActivate::1344-1345 3 0.77% 87.92% # Bytes accessed per row activation
178 system.physmem.bytesPerActivate::1408-1409 3 0.77% 88.69% # Bytes accessed per row activation
179 system.physmem.bytesPerActivate::1472-1473 2 0.51% 89.20% # Bytes accessed per row activation
180 system.physmem.bytesPerActivate::1536-1537 1 0.26% 89.46% # Bytes accessed per row activation
181 system.physmem.bytesPerActivate::1600-1601 3 0.77% 90.23% # Bytes accessed per row activation
182 system.physmem.bytesPerActivate::1664-1665 3 0.77% 91.00% # Bytes accessed per row activation
183 system.physmem.bytesPerActivate::1728-1729 1 0.26% 91.26% # Bytes accessed per row activation
184 system.physmem.bytesPerActivate::1792-1793 1 0.26% 91.52% # Bytes accessed per row activation
185 system.physmem.bytesPerActivate::1920-1921 1 0.26% 91.77% # Bytes accessed per row activation
186 system.physmem.bytesPerActivate::2048-2049 1 0.26% 92.03% # Bytes accessed per row activation
187 system.physmem.bytesPerActivate::2112-2113 2 0.51% 92.54% # Bytes accessed per row activation
188 system.physmem.bytesPerActivate::2176-2177 1 0.26% 92.80% # Bytes accessed per row activation
189 system.physmem.bytesPerActivate::2304-2305 1 0.26% 93.06% # Bytes accessed per row activation
190 system.physmem.bytesPerActivate::2368-2369 1 0.26% 93.32% # Bytes accessed per row activation
191 system.physmem.bytesPerActivate::2432-2433 1 0.26% 93.57% # Bytes accessed per row activation
192 system.physmem.bytesPerActivate::2624-2625 1 0.26% 93.83% # Bytes accessed per row activation
193 system.physmem.bytesPerActivate::2688-2689 1 0.26% 94.09% # Bytes accessed per row activation
194 system.physmem.bytesPerActivate::2816-2817 1 0.26% 94.34% # Bytes accessed per row activation
195 system.physmem.bytesPerActivate::2944-2945 1 0.26% 94.60% # Bytes accessed per row activation
196 system.physmem.bytesPerActivate::3008-3009 1 0.26% 94.86% # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::3072-3073 1 0.26% 95.12% # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::3200-3201 1 0.26% 95.37% # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::3264-3265 4 1.03% 96.40% # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::3712-3713 1 0.26% 96.66% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::4032-4033 1 0.26% 96.92% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::4352-4353 1 0.26% 97.17% # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::4416-4417 1 0.26% 97.43% # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::4480-4481 1 0.26% 97.69% # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::4800-4801 1 0.26% 97.94% # Bytes accessed per row activation
206 system.physmem.bytesPerActivate::5120-5121 1 0.26% 98.20% # Bytes accessed per row activation
207 system.physmem.bytesPerActivate::5248-5249 1 0.26% 98.46% # Bytes accessed per row activation
208 system.physmem.bytesPerActivate::6208-6209 1 0.26% 98.71% # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::6720-6721 1 0.26% 98.97% # Bytes accessed per row activation
210 system.physmem.bytesPerActivate::6848-6849 1 0.26% 99.23% # Bytes accessed per row activation
211 system.physmem.bytesPerActivate::8128-8129 1 0.26% 99.49% # Bytes accessed per row activation
212 system.physmem.bytesPerActivate::8192-8193 2 0.51% 100.00% # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::total 389 # Bytes accessed per row activation
214 system.physmem.totQLat 12962000 # Total cycles spent in queuing delays
215 system.physmem.totMemAccLat 86183250 # Sum of mem lat for all requests
216 system.physmem.totBusLat 19005000 # Total cycles spent in databus access
217 system.physmem.totBankLat 54216250 # Total cycles spent in bank access
218 system.physmem.avgQLat 3410.16 # Average queueing delay per request
219 system.physmem.avgBankLat 14263.68 # Average bank access latency per request
220 system.physmem.avgBusLat 5000.00 # Average bus latency per request
221 system.physmem.avgMemAccLat 22673.84 # Average memory access latency
222 system.physmem.avgRdBW 3.28 # Average achieved read bandwidth in MB/s
223 system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
224 system.physmem.avgConsumedRdBW 3.28 # Average consumed read bandwidth in MB/s
225 system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
226 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
227 system.physmem.busUtil 0.03 # Data bus utilization in percentage
228 system.physmem.avgRdQLen 0.00 # Average read queue length over time
229 system.physmem.avgWrQLen 0.00 # Average write queue length over time
230 system.physmem.readRowHits 3412 # Number of row buffer hits during reads
231 system.physmem.writeRowHits 0 # Number of row buffer hits during writes
232 system.physmem.readRowHitRate 89.77 # Row buffer hit rate for reads
233 system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
234 system.physmem.avgGap 19521443.30 # Average gap between requests
235 system.membus.throughput 3277583 # Throughput (bytes/s)
236 system.membus.trans_dist::ReadReq 2726 # Transaction distribution
237 system.membus.trans_dist::ReadResp 2725 # Transaction distribution
238 system.membus.trans_dist::UpgradeReq 2 # Transaction distribution
239 system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
240 system.membus.trans_dist::ReadExReq 1075 # Transaction distribution
241 system.membus.trans_dist::ReadExResp 1075 # Transaction distribution
242 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7605 # Packet count per connected master and slave (bytes)
243 system.membus.pkt_count::total 7605 # Packet count per connected master and slave (bytes)
244 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 243200 # Cumulative packet size per connected master and slave (bytes)
245 system.membus.tot_pkt_size::total 243200 # Cumulative packet size per connected master and slave (bytes)
246 system.membus.data_through_bus 243200 # Total data (bytes)
247 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
248 system.membus.reqLayer0.occupancy 4684500 # Layer occupancy (ticks)
249 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
250 system.membus.respLayer1.occupancy 35707998 # Layer occupancy (ticks)
251 system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
252 system.cpu.branchPred.lookups 94803777 # Number of BP lookups
253 system.cpu.branchPred.condPredicted 74793629 # Number of conditional branches predicted
254 system.cpu.branchPred.condIncorrect 6279390 # Number of conditional branches incorrect
255 system.cpu.branchPred.BTBLookups 44652033 # Number of BTB lookups
256 system.cpu.branchPred.BTBHits 43049215 # Number of BTB hits
257 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
258 system.cpu.branchPred.BTBHitPct 96.410425 # BTB Hit Percentage
259 system.cpu.branchPred.usedRAS 4355984 # Number of times the RAS was used to get a target.
260 system.cpu.branchPred.RASInCorrect 88442 # Number of incorrect RAS predictions.
261 system.cpu.dtb.inst_hits 0 # ITB inst hits
262 system.cpu.dtb.inst_misses 0 # ITB inst misses
263 system.cpu.dtb.read_hits 0 # DTB read hits
264 system.cpu.dtb.read_misses 0 # DTB read misses
265 system.cpu.dtb.write_hits 0 # DTB write hits
266 system.cpu.dtb.write_misses 0 # DTB write misses
267 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
268 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
269 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
270 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
271 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
272 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
273 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
274 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
275 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
276 system.cpu.dtb.read_accesses 0 # DTB read accesses
277 system.cpu.dtb.write_accesses 0 # DTB write accesses
278 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
279 system.cpu.dtb.hits 0 # DTB hits
280 system.cpu.dtb.misses 0 # DTB misses
281 system.cpu.dtb.accesses 0 # DTB accesses
282 system.cpu.itb.inst_hits 0 # ITB inst hits
283 system.cpu.itb.inst_misses 0 # ITB inst misses
284 system.cpu.itb.read_hits 0 # DTB read hits
285 system.cpu.itb.read_misses 0 # DTB read misses
286 system.cpu.itb.write_hits 0 # DTB write hits
287 system.cpu.itb.write_misses 0 # DTB write misses
288 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
289 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
290 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
291 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
292 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
293 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
294 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
295 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
296 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
297 system.cpu.itb.read_accesses 0 # DTB read accesses
298 system.cpu.itb.write_accesses 0 # DTB write accesses
299 system.cpu.itb.inst_accesses 0 # ITB inst accesses
300 system.cpu.itb.hits 0 # DTB hits
301 system.cpu.itb.misses 0 # DTB misses
302 system.cpu.itb.accesses 0 # DTB accesses
303 system.cpu.workload.num_syscalls 400 # Number of system calls
304 system.cpu.numCycles 148402050 # number of cpu cycles simulated
305 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
306 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
307 system.cpu.fetch.icacheStallCycles 39645282 # Number of cycles fetch is stalled on an Icache miss
308 system.cpu.fetch.Insts 380210735 # Number of instructions fetch has processed
309 system.cpu.fetch.Branches 94803777 # Number of branches that fetch encountered
310 system.cpu.fetch.predictedBranches 47405199 # Number of branches that fetch has predicted taken
311 system.cpu.fetch.Cycles 80366135 # Number of cycles fetch has run and was not squashing or blocked
312 system.cpu.fetch.SquashCycles 27283939 # Number of cycles fetch has spent squashing
313 system.cpu.fetch.BlockedCycles 7211893 # Number of cycles fetch has spent blocked
314 system.cpu.fetch.MiscStallCycles 12 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
315 system.cpu.fetch.PendingTrapStallCycles 5835 # Number of stall cycles due to pending traps
316 system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions
317 system.cpu.fetch.IcacheWaitRetryStallCycles 74 # Number of stall cycles due to full MSHR
318 system.cpu.fetch.CacheLines 36839707 # Number of cache lines fetched
319 system.cpu.fetch.IcacheSquashes 1829204 # Number of outstanding Icache misses that were squashed
320 system.cpu.fetch.rateDist::samples 148218142 # Number of instructions fetched each cycle (Total)
321 system.cpu.fetch.rateDist::mean 2.802317 # Number of instructions fetched each cycle (Total)
322 system.cpu.fetch.rateDist::stdev 3.153165 # Number of instructions fetched each cycle (Total)
323 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
324 system.cpu.fetch.rateDist::0 68020669 45.89% 45.89% # Number of instructions fetched each cycle (Total)
325 system.cpu.fetch.rateDist::1 5263809 3.55% 49.44% # Number of instructions fetched each cycle (Total)
326 system.cpu.fetch.rateDist::2 10529342 7.10% 56.55% # Number of instructions fetched each cycle (Total)
327 system.cpu.fetch.rateDist::3 10284383 6.94% 63.49% # Number of instructions fetched each cycle (Total)
328 system.cpu.fetch.rateDist::4 8663442 5.85% 69.33% # Number of instructions fetched each cycle (Total)
329 system.cpu.fetch.rateDist::5 6544357 4.42% 73.75% # Number of instructions fetched each cycle (Total)
330 system.cpu.fetch.rateDist::6 6237651 4.21% 77.96% # Number of instructions fetched each cycle (Total)
331 system.cpu.fetch.rateDist::7 8018779 5.41% 83.37% # Number of instructions fetched each cycle (Total)
332 system.cpu.fetch.rateDist::8 24655710 16.63% 100.00% # Number of instructions fetched each cycle (Total)
333 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
334 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
335 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
336 system.cpu.fetch.rateDist::total 148218142 # Number of instructions fetched each cycle (Total)
337 system.cpu.fetch.branchRate 0.638831 # Number of branch fetches per cycle
338 system.cpu.fetch.rate 2.562032 # Number of inst fetches per cycle
339 system.cpu.decode.IdleCycles 45496346 # Number of cycles decode is idle
340 system.cpu.decode.BlockedCycles 5881053 # Number of cycles decode is blocked
341 system.cpu.decode.RunCycles 74801402 # Number of cycles decode is running
342 system.cpu.decode.UnblockCycles 1203851 # Number of cycles decode is unblocking
343 system.cpu.decode.SquashCycles 20835490 # Number of cycles decode is squashing
344 system.cpu.decode.BranchResolved 14335605 # Number of times decode resolved a branch
345 system.cpu.decode.BranchMispred 164633 # Number of times decode detected a branch misprediction
346 system.cpu.decode.DecodedInsts 392823460 # Number of instructions handled by decode
347 system.cpu.decode.SquashedInsts 736203 # Number of squashed instructions handled by decode
348 system.cpu.rename.SquashCycles 20835490 # Number of cycles rename is squashing
349 system.cpu.rename.IdleCycles 50883815 # Number of cycles rename is idle
350 system.cpu.rename.BlockCycles 724795 # Number of cycles rename is blocking
351 system.cpu.rename.serializeStallCycles 600466 # count of cycles rename stalled for serializing inst
352 system.cpu.rename.RunCycles 70555670 # Number of cycles rename is running
353 system.cpu.rename.UnblockCycles 4617906 # Number of cycles rename is unblocking
354 system.cpu.rename.RenamedInsts 371356593 # Number of instructions processed by rename
355 system.cpu.rename.ROBFullEvents 28 # Number of times rename has blocked due to ROB full
356 system.cpu.rename.IQFullEvents 342994 # Number of times rename has blocked due to IQ full
357 system.cpu.rename.LSQFullEvents 3662384 # Number of times rename has blocked due to LSQ full
358 system.cpu.rename.FullRegisterEvents 29 # Number of times there has been no free registers
359 system.cpu.rename.RenamedOperands 631760398 # Number of destination operands rename has renamed
360 system.cpu.rename.RenameLookups 1581883462 # Number of register rename lookups that rename has made
361 system.cpu.rename.int_rename_lookups 1507069248 # Number of integer rename lookups
362 system.cpu.rename.fp_rename_lookups 3196133 # Number of floating rename lookups
363 system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed
364 system.cpu.rename.UndoneMaps 333716259 # Number of HB maps that are undone due to squashing
365 system.cpu.rename.serializingInsts 25188 # count of serializing insts renamed
366 system.cpu.rename.tempSerializingInsts 25185 # count of temporary serializing insts renamed
367 system.cpu.rename.skidInsts 13032916 # count of insts added to the skid buffer
368 system.cpu.memDep0.insertedLoads 43019038 # Number of loads inserted to the mem dependence unit.
369 system.cpu.memDep0.insertedStores 16425001 # Number of stores inserted to the mem dependence unit.
370 system.cpu.memDep0.conflictingLoads 5693552 # Number of conflicting loads.
371 system.cpu.memDep0.conflictingStores 3686945 # Number of conflicting stores.
372 system.cpu.iq.iqInstsAdded 329243417 # Number of instructions added to the IQ (excludes non-spec)
373 system.cpu.iq.iqNonSpecInstsAdded 47203 # Number of non-speculative instructions added to the IQ
374 system.cpu.iq.iqInstsIssued 249464214 # Number of instructions issued
375 system.cpu.iq.iqSquashedInstsIssued 795417 # Number of squashed instructions issued
376 system.cpu.iq.iqSquashedInstsExamined 139561180 # Number of squashed instructions iterated over during squash; mainly for profiling
377 system.cpu.iq.iqSquashedOperandsExamined 362246737 # Number of squashed operands that are examined and possibly removed from graph
378 system.cpu.iq.iqSquashedNonSpecRemoved 1987 # Number of squashed non-spec instructions that were removed
379 system.cpu.iq.issued_per_cycle::samples 148218142 # Number of insts issued each cycle
380 system.cpu.iq.issued_per_cycle::mean 1.683088 # Number of insts issued each cycle
381 system.cpu.iq.issued_per_cycle::stdev 1.761802 # Number of insts issued each cycle
382 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
383 system.cpu.iq.issued_per_cycle::0 56048230 37.81% 37.81% # Number of insts issued each cycle
384 system.cpu.iq.issued_per_cycle::1 22642926 15.28% 53.09% # Number of insts issued each cycle
385 system.cpu.iq.issued_per_cycle::2 24814212 16.74% 69.83% # Number of insts issued each cycle
386 system.cpu.iq.issued_per_cycle::3 20312337 13.70% 83.54% # Number of insts issued each cycle
387 system.cpu.iq.issued_per_cycle::4 12552656 8.47% 92.01% # Number of insts issued each cycle
388 system.cpu.iq.issued_per_cycle::5 6518158 4.40% 96.40% # Number of insts issued each cycle
389 system.cpu.iq.issued_per_cycle::6 4033272 2.72% 99.13% # Number of insts issued each cycle
390 system.cpu.iq.issued_per_cycle::7 1116001 0.75% 99.88% # Number of insts issued each cycle
391 system.cpu.iq.issued_per_cycle::8 180350 0.12% 100.00% # Number of insts issued each cycle
392 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
393 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
394 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
395 system.cpu.iq.issued_per_cycle::total 148218142 # Number of insts issued each cycle
396 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
397 system.cpu.iq.fu_full::IntAlu 965237 38.47% 38.47% # attempts to use FU when none available
398 system.cpu.iq.fu_full::IntMult 5595 0.22% 38.69% # attempts to use FU when none available
399 system.cpu.iq.fu_full::IntDiv 0 0.00% 38.69% # attempts to use FU when none available
400 system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.69% # attempts to use FU when none available
401 system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.69% # attempts to use FU when none available
402 system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.69% # attempts to use FU when none available
403 system.cpu.iq.fu_full::FloatMult 0 0.00% 38.69% # attempts to use FU when none available
404 system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.69% # attempts to use FU when none available
405 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.69% # attempts to use FU when none available
406 system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.69% # attempts to use FU when none available
407 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.69% # attempts to use FU when none available
408 system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.69% # attempts to use FU when none available
409 system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.69% # attempts to use FU when none available
410 system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.69% # attempts to use FU when none available
411 system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.69% # attempts to use FU when none available
412 system.cpu.iq.fu_full::SimdMult 0 0.00% 38.69% # attempts to use FU when none available
413 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.69% # attempts to use FU when none available
414 system.cpu.iq.fu_full::SimdShift 0 0.00% 38.69% # attempts to use FU when none available
415 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.69% # attempts to use FU when none available
416 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.69% # attempts to use FU when none available
417 system.cpu.iq.fu_full::SimdFloatAdd 98 0.00% 38.70% # attempts to use FU when none available
418 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.70% # attempts to use FU when none available
419 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.70% # attempts to use FU when none available
420 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.70% # attempts to use FU when none available
421 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.70% # attempts to use FU when none available
422 system.cpu.iq.fu_full::SimdFloatMisc 50 0.00% 38.70% # attempts to use FU when none available
423 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.70% # attempts to use FU when none available
424 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.70% # attempts to use FU when none available
425 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.70% # attempts to use FU when none available
426 system.cpu.iq.fu_full::MemRead 1168121 46.56% 85.25% # attempts to use FU when none available
427 system.cpu.iq.fu_full::MemWrite 370007 14.75% 100.00% # attempts to use FU when none available
428 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
429 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
430 system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
431 system.cpu.iq.FU_type_0::IntAlu 194903493 78.13% 78.13% # Type of FU issued
432 system.cpu.iq.FU_type_0::IntMult 979289 0.39% 78.52% # Type of FU issued
433 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued
434 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued
435 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.52% # Type of FU issued
436 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.52% # Type of FU issued
437 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.52% # Type of FU issued
438 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.52% # Type of FU issued
439 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.52% # Type of FU issued
440 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.52% # Type of FU issued
441 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.52% # Type of FU issued
442 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.52% # Type of FU issued
443 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.52% # Type of FU issued
444 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.52% # Type of FU issued
445 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.52% # Type of FU issued
446 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.52% # Type of FU issued
447 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.52% # Type of FU issued
448 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.52% # Type of FU issued
449 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.52% # Type of FU issued
450 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.52% # Type of FU issued
451 system.cpu.iq.FU_type_0::SimdFloatAdd 33083 0.01% 78.53% # Type of FU issued
452 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.53% # Type of FU issued
453 system.cpu.iq.FU_type_0::SimdFloatCmp 164442 0.07% 78.60% # Type of FU issued
454 system.cpu.iq.FU_type_0::SimdFloatCvt 254821 0.10% 78.70% # Type of FU issued
455 system.cpu.iq.FU_type_0::SimdFloatDiv 76413 0.03% 78.73% # Type of FU issued
456 system.cpu.iq.FU_type_0::SimdFloatMisc 465720 0.19% 78.92% # Type of FU issued
457 system.cpu.iq.FU_type_0::SimdFloatMult 206380 0.08% 79.00% # Type of FU issued
458 system.cpu.iq.FU_type_0::SimdFloatMultAcc 71858 0.03% 79.03% # Type of FU issued
459 system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 79.03% # Type of FU issued
460 system.cpu.iq.FU_type_0::MemRead 38359883 15.38% 94.41% # Type of FU issued
461 system.cpu.iq.FU_type_0::MemWrite 13948512 5.59% 100.00% # Type of FU issued
462 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
463 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
464 system.cpu.iq.FU_type_0::total 249464214 # Type of FU issued
465 system.cpu.iq.rate 1.681002 # Inst issue rate
466 system.cpu.iq.fu_busy_cnt 2509108 # FU busy when requested
467 system.cpu.iq.fu_busy_rate 0.010058 # FU busy rate (busy events/executed inst)
468 system.cpu.iq.int_inst_queue_reads 646714008 # Number of integer instruction queue reads
469 system.cpu.iq.int_inst_queue_writes 466681926 # Number of integer instruction queue writes
470 system.cpu.iq.int_inst_queue_wakeup_accesses 237887502 # Number of integer instruction queue wakeup accesses
471 system.cpu.iq.fp_inst_queue_reads 3737087 # Number of floating instruction queue reads
472 system.cpu.iq.fp_inst_queue_writes 2188015 # Number of floating instruction queue writes
473 system.cpu.iq.fp_inst_queue_wakeup_accesses 1841410 # Number of floating instruction queue wakeup accesses
474 system.cpu.iq.int_alu_accesses 250098110 # Number of integer alu accesses
475 system.cpu.iq.fp_alu_accesses 1875212 # Number of floating point alu accesses
476 system.cpu.iew.lsq.thread0.forwLoads 2005238 # Number of loads that had data forwarded from stores
477 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
478 system.cpu.iew.lsq.thread0.squashedLoads 13169554 # Number of loads squashed
479 system.cpu.iew.lsq.thread0.ignoredResponses 11470 # Number of memory responses ignored because the instruction is squashed
480 system.cpu.iew.lsq.thread0.memOrderViolation 18663 # Number of memory ordering violations
481 system.cpu.iew.lsq.thread0.squashedStores 3780367 # Number of stores squashed
482 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
483 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
484 system.cpu.iew.lsq.thread0.rescheduledLoads 11 # Number of loads that were rescheduled
485 system.cpu.iew.lsq.thread0.cacheBlocked 113 # Number of times an access to memory failed due to the cache being blocked
486 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
487 system.cpu.iew.iewSquashCycles 20835490 # Number of cycles IEW is squashing
488 system.cpu.iew.iewBlockCycles 18710 # Number of cycles IEW is blocking
489 system.cpu.iew.iewUnblockCycles 879 # Number of cycles IEW is unblocking
490 system.cpu.iew.iewDispatchedInsts 329307607 # Number of instructions dispatched to IQ
491 system.cpu.iew.iewDispSquashedInsts 785363 # Number of squashed instructions skipped by dispatch
492 system.cpu.iew.iewDispLoadInsts 43019038 # Number of dispatched load instructions
493 system.cpu.iew.iewDispStoreInsts 16425001 # Number of dispatched store instructions
494 system.cpu.iew.iewDispNonSpecInsts 24795 # Number of dispatched non-speculative instructions
495 system.cpu.iew.iewIQFullEvents 182 # Number of times the IQ has become full, causing a stall
496 system.cpu.iew.iewLSQFullEvents 275 # Number of times the LSQ has become full, causing a stall
497 system.cpu.iew.memOrderViolationEvents 18663 # Number of memory order violations
498 system.cpu.iew.predictedTakenIncorrect 3889158 # Number of branches that were predicted taken incorrectly
499 system.cpu.iew.predictedNotTakenIncorrect 3759638 # Number of branches that were predicted not taken incorrectly
500 system.cpu.iew.branchMispredicts 7648796 # Number of branch mispredicts detected at execute
501 system.cpu.iew.iewExecutedInsts 242968769 # Number of executed instructions
502 system.cpu.iew.iewExecLoadInsts 36856935 # Number of load instructions executed
503 system.cpu.iew.iewExecSquashedInsts 6495445 # Number of squashed instructions skipped in execute
504 system.cpu.iew.exec_swp 0 # number of swp insts executed
505 system.cpu.iew.exec_nop 16987 # number of nop insts executed
506 system.cpu.iew.exec_refs 50502724 # number of memory reference insts executed
507 system.cpu.iew.exec_branches 53433142 # Number of branches executed
508 system.cpu.iew.exec_stores 13645789 # Number of stores executed
509 system.cpu.iew.exec_rate 1.637233 # Inst execution rate
510 system.cpu.iew.wb_sent 240789077 # cumulative count of insts sent to commit
511 system.cpu.iew.wb_count 239728912 # cumulative count of insts written-back
512 system.cpu.iew.wb_producers 148477198 # num instructions producing a value
513 system.cpu.iew.wb_consumers 267296630 # num instructions consuming a value
514 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
515 system.cpu.iew.wb_rate 1.615402 # insts written-back per cycle
516 system.cpu.iew.wb_fanout 0.555477 # average fanout of values written-back
517 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
518 system.cpu.commit.commitSquashedInsts 140636703 # The number of squashed insts skipped by commit
519 system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards
520 system.cpu.commit.branchMispredicts 6125970 # The number of times a branch was mispredicted
521 system.cpu.commit.committed_per_cycle::samples 127382652 # Number of insts commited each cycle
522 system.cpu.commit.committed_per_cycle::mean 1.481135 # Number of insts commited each cycle
523 system.cpu.commit.committed_per_cycle::stdev 2.185870 # Number of insts commited each cycle
524 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
525 system.cpu.commit.committed_per_cycle::0 57681624 45.28% 45.28% # Number of insts commited each cycle
526 system.cpu.commit.committed_per_cycle::1 31696418 24.88% 70.17% # Number of insts commited each cycle
527 system.cpu.commit.committed_per_cycle::2 13781439 10.82% 80.98% # Number of insts commited each cycle
528 system.cpu.commit.committed_per_cycle::3 7634613 5.99% 86.98% # Number of insts commited each cycle
529 system.cpu.commit.committed_per_cycle::4 4380226 3.44% 90.42% # Number of insts commited each cycle
530 system.cpu.commit.committed_per_cycle::5 1319827 1.04% 91.45% # Number of insts commited each cycle
531 system.cpu.commit.committed_per_cycle::6 1706186 1.34% 92.79% # Number of insts commited each cycle
532 system.cpu.commit.committed_per_cycle::7 1307951 1.03% 93.82% # Number of insts commited each cycle
533 system.cpu.commit.committed_per_cycle::8 7874368 6.18% 100.00% # Number of insts commited each cycle
534 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
535 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
536 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
537 system.cpu.commit.committed_per_cycle::total 127382652 # Number of insts commited each cycle
538 system.cpu.commit.committedInsts 172317409 # Number of instructions committed
539 system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed
540 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
541 system.cpu.commit.refs 42494118 # Number of memory references committed
542 system.cpu.commit.loads 29849484 # Number of loads committed
543 system.cpu.commit.membars 22408 # Number of memory barriers committed
544 system.cpu.commit.branches 40300311 # Number of branches committed
545 system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions.
546 system.cpu.commit.int_insts 150106217 # Number of committed integer instructions.
547 system.cpu.commit.function_calls 1848934 # Number of function calls committed.
548 system.cpu.commit.bw_lim_events 7874368 # number cycles where commit BW limit reached
549 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
550 system.cpu.rob.rob_reads 448810677 # The number of ROB reads
551 system.cpu.rob.rob_writes 679560182 # The number of ROB writes
552 system.cpu.timesIdled 2800 # Number of times that the entire CPU went into an idle state and unscheduled itself
553 system.cpu.idleCycles 183908 # Total number of cycles that the CPU has spent unscheduled due to idling
554 system.cpu.committedInsts 172303021 # Number of Instructions Simulated
555 system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated
556 system.cpu.committedInsts_total 172303021 # Number of Instructions Simulated
557 system.cpu.cpi 0.861285 # CPI: Cycles Per Instruction
558 system.cpu.cpi_total 0.861285 # CPI: Total CPI of All Threads
559 system.cpu.ipc 1.161056 # IPC: Instructions Per Cycle
560 system.cpu.ipc_total 1.161056 # IPC: Total IPC of All Threads
561 system.cpu.int_regfile_reads 1079439367 # number of integer regfile reads
562 system.cpu.int_regfile_writes 384873719 # number of integer regfile writes
563 system.cpu.fp_regfile_reads 2913212 # number of floating regfile reads
564 system.cpu.fp_regfile_writes 2497494 # number of floating regfile writes
565 system.cpu.misc_regfile_reads 54494427 # number of misc regfile reads
566 system.cpu.misc_regfile_writes 820036 # number of misc regfile writes
567 system.cpu.toL2Bus.throughput 5172543 # Throughput (bytes/s)
568 system.cpu.toL2Bus.trans_dist::ReadReq 4897 # Transaction distribution
569 system.cpu.toL2Bus.trans_dist::ReadResp 4896 # Transaction distribution
570 system.cpu.toL2Bus.trans_dist::Writeback 18 # Transaction distribution
571 system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution
572 system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution
573 system.cpu.toL2Bus.trans_dist::ReadExReq 1083 # Transaction distribution
574 system.cpu.toL2Bus.trans_dist::ReadExResp 1083 # Transaction distribution
575 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8247 # Packet count per connected master and slave (bytes)
576 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3732 # Packet count per connected master and slave (bytes)
577 system.cpu.toL2Bus.pkt_count::total 11979 # Packet count per connected master and slave (bytes)
578 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 263808 # Cumulative packet size per connected master and slave (bytes)
579 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119872 # Cumulative packet size per connected master and slave (bytes)
580 system.cpu.toL2Bus.tot_pkt_size::total 383680 # Cumulative packet size per connected master and slave (bytes)
581 system.cpu.toL2Bus.data_through_bus 383680 # Total data (bytes)
582 system.cpu.toL2Bus.snoop_data_through_bus 128 # Total snoop data (bytes)
583 system.cpu.toL2Bus.reqLayer0.occupancy 3018000 # Layer occupancy (ticks)
584 system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
585 system.cpu.toL2Bus.respLayer0.occupancy 6609745 # Layer occupancy (ticks)
586 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
587 system.cpu.toL2Bus.respLayer1.occupancy 3106490 # Layer occupancy (ticks)
588 system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
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592 system.cpu.icache.tags.sampled_refs 4122 # Sample count of references to valid blocks.
593 system.cpu.icache.tags.avg_refs 8936.044881 # Average number of references to valid blocks.
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595 system.cpu.icache.tags.occ_blocks::cpu.inst 1346.456608 # Average occupied blocks per requestor
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597 system.cpu.icache.tags.occ_percent::total 0.657450 # Average percentage of cache occupancy
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599 system.cpu.icache.ReadReq_hits::total 36834377 # number of ReadReq hits
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605 system.cpu.icache.ReadReq_misses::total 5330 # number of ReadReq misses
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607 system.cpu.icache.demand_misses::total 5330 # number of demand (read+write) misses
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611 system.cpu.icache.ReadReq_miss_latency::total 215954243 # number of ReadReq miss cycles
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613 system.cpu.icache.demand_miss_latency::total 215954243 # number of demand (read+write) miss cycles
614 system.cpu.icache.overall_miss_latency::cpu.inst 215954243 # number of overall miss cycles
615 system.cpu.icache.overall_miss_latency::total 215954243 # number of overall miss cycles
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617 system.cpu.icache.ReadReq_accesses::total 36839707 # number of ReadReq accesses(hits+misses)
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620 system.cpu.icache.overall_accesses::cpu.inst 36839707 # number of overall (read+write) accesses
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623 system.cpu.icache.ReadReq_miss_rate::total 0.000145 # miss rate for ReadReq accesses
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625 system.cpu.icache.demand_miss_rate::total 0.000145 # miss rate for demand accesses
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627 system.cpu.icache.overall_miss_rate::total 0.000145 # miss rate for overall accesses
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631 system.cpu.icache.demand_avg_miss_latency::total 40516.743527 # average overall miss latency
632 system.cpu.icache.overall_avg_miss_latency::cpu.inst 40516.743527 # average overall miss latency
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636 system.cpu.icache.blocked::no_mshrs 21 # number of cycles access was blocked
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649 system.cpu.icache.ReadReq_mshr_misses::total 4125 # number of ReadReq MSHR misses
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656 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 162387254 # number of demand (read+write) MSHR miss cycles
657 system.cpu.icache.demand_mshr_miss_latency::total 162387254 # number of demand (read+write) MSHR miss cycles
658 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 162387254 # number of overall MSHR miss cycles
659 system.cpu.icache.overall_mshr_miss_latency::total 162387254 # number of overall MSHR miss cycles
660 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for ReadReq accesses
661 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000112 # mshr miss rate for ReadReq accesses
662 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for demand accesses
663 system.cpu.icache.demand_mshr_miss_rate::total 0.000112 # mshr miss rate for demand accesses
664 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for overall accesses
665 system.cpu.icache.overall_mshr_miss_rate::total 0.000112 # mshr miss rate for overall accesses
666 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39366.607030 # average ReadReq mshr miss latency
667 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39366.607030 # average ReadReq mshr miss latency
668 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39366.607030 # average overall mshr miss latency
669 system.cpu.icache.demand_avg_mshr_miss_latency::total 39366.607030 # average overall mshr miss latency
670 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39366.607030 # average overall mshr miss latency
671 system.cpu.icache.overall_avg_mshr_miss_latency::total 39366.607030 # average overall mshr miss latency
672 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
673 system.cpu.l2cache.tags.replacements 0 # number of replacements
674 system.cpu.l2cache.tags.tagsinuse 1961.044100 # Cycle average of tags in use
675 system.cpu.l2cache.tags.total_refs 2153 # Total number of references to valid blocks.
676 system.cpu.l2cache.tags.sampled_refs 2735 # Sample count of references to valid blocks.
677 system.cpu.l2cache.tags.avg_refs 0.787203 # Average number of references to valid blocks.
678 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
679 system.cpu.l2cache.tags.occ_blocks::writebacks 4.994051 # Average occupied blocks per requestor
680 system.cpu.l2cache.tags.occ_blocks::cpu.inst 1423.034105 # Average occupied blocks per requestor
681 system.cpu.l2cache.tags.occ_blocks::cpu.data 533.015945 # Average occupied blocks per requestor
682 system.cpu.l2cache.tags.occ_percent::writebacks 0.000152 # Average percentage of cache occupancy
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684 system.cpu.l2cache.tags.occ_percent::cpu.data 0.016266 # Average percentage of cache occupancy
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687 system.cpu.l2cache.ReadReq_hits::cpu.data 87 # number of ReadReq hits
688 system.cpu.l2cache.ReadReq_hits::total 2152 # number of ReadReq hits
689 system.cpu.l2cache.Writeback_hits::writebacks 18 # number of Writeback hits
690 system.cpu.l2cache.Writeback_hits::total 18 # number of Writeback hits
691 system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits
692 system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits
693 system.cpu.l2cache.demand_hits::cpu.inst 2065 # number of demand (read+write) hits
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695 system.cpu.l2cache.demand_hits::total 2160 # number of demand (read+write) hits
696 system.cpu.l2cache.overall_hits::cpu.inst 2065 # number of overall hits
697 system.cpu.l2cache.overall_hits::cpu.data 95 # number of overall hits
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721 system.cpu.l2cache.overall_miss_latency::cpu.data 115412000 # number of overall miss cycles
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725 system.cpu.l2cache.ReadReq_accesses::total 4895 # number of ReadReq accesses(hits+misses)
726 system.cpu.l2cache.Writeback_accesses::writebacks 18 # number of Writeback accesses(hits+misses)
727 system.cpu.l2cache.Writeback_accesses::total 18 # number of Writeback accesses(hits+misses)
728 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses)
729 system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses)
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742 system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
743 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992613 # miss rate for ReadExReq accesses
744 system.cpu.l2cache.ReadExReq_miss_rate::total 0.992613 # miss rate for ReadExReq accesses
745 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.499151 # miss rate for demand accesses
746 system.cpu.l2cache.demand_miss_rate::cpu.data 0.948787 # miss rate for demand accesses
747 system.cpu.l2cache.demand_miss_rate::total 0.638675 # miss rate for demand accesses
748 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.499151 # miss rate for overall accesses
749 system.cpu.l2cache.overall_miss_rate::cpu.data 0.948787 # miss rate for overall accesses
750 system.cpu.l2cache.overall_miss_rate::total 0.638675 # miss rate for overall accesses
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752 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68998.905109 # average ReadReq miss latency
753 system.cpu.l2cache.ReadReq_avg_miss_latency::total 67395.916879 # average ReadReq miss latency
754 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 63393.255814 # average ReadExReq miss latency
755 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 63393.255814 # average ReadExReq miss latency
756 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66862.366375 # average overall miss latency
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758 system.cpu.l2cache.demand_avg_miss_latency::total 66268.923520 # average overall miss latency
759 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66862.366375 # average overall miss latency
760 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65575 # average overall miss latency
761 system.cpu.l2cache.overall_avg_miss_latency::total 66268.923520 # average overall miss latency
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763 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
764 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
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766 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
767 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
768 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
769 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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771 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 12 # number of ReadReq MSHR hits
772 system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits
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777 system.cpu.l2cache.overall_mshr_hits::cpu.data 12 # number of overall MSHR hits
778 system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits
779 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2053 # number of ReadReq MSHR misses
780 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 673 # number of ReadReq MSHR misses
781 system.cpu.l2cache.ReadReq_mshr_misses::total 2726 # number of ReadReq MSHR misses
782 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses
783 system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses
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785 system.cpu.l2cache.ReadExReq_mshr_misses::total 1075 # number of ReadExReq MSHR misses
786 system.cpu.l2cache.demand_mshr_misses::cpu.inst 2053 # number of demand (read+write) MSHR misses
787 system.cpu.l2cache.demand_mshr_misses::cpu.data 1748 # number of demand (read+write) MSHR misses
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789 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2053 # number of overall MSHR misses
790 system.cpu.l2cache.overall_mshr_misses::cpu.data 1748 # number of overall MSHR misses
791 system.cpu.l2cache.overall_mshr_misses::total 3801 # number of overall MSHR misses
792 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 111409500 # number of ReadReq MSHR miss cycles
793 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 38132750 # number of ReadReq MSHR miss cycles
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795 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles
796 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles
797 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54590750 # number of ReadExReq MSHR miss cycles
798 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54590750 # number of ReadExReq MSHR miss cycles
799 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 111409500 # number of demand (read+write) MSHR miss cycles
800 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 92723500 # number of demand (read+write) MSHR miss cycles
801 system.cpu.l2cache.demand_mshr_miss_latency::total 204133000 # number of demand (read+write) MSHR miss cycles
802 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 111409500 # number of overall MSHR miss cycles
803 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 92723500 # number of overall MSHR miss cycles
804 system.cpu.l2cache.overall_mshr_miss_latency::total 204133000 # number of overall MSHR miss cycles
805 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.497938 # mshr miss rate for ReadReq accesses
806 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871762 # mshr miss rate for ReadReq accesses
807 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.556895 # mshr miss rate for ReadReq accesses
808 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
809 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
810 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992613 # mshr miss rate for ReadExReq accesses
811 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992613 # mshr miss rate for ReadExReq accesses
812 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.497938 # mshr miss rate for demand accesses
813 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.942318 # mshr miss rate for demand accesses
814 system.cpu.l2cache.demand_mshr_miss_rate::total 0.635831 # mshr miss rate for demand accesses
815 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.497938 # mshr miss rate for overall accesses
816 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.942318 # mshr miss rate for overall accesses
817 system.cpu.l2cache.overall_mshr_miss_rate::total 0.635831 # mshr miss rate for overall accesses
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819 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56660.846954 # average ReadReq mshr miss latency
820 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54857.758621 # average ReadReq mshr miss latency
821 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
822 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
823 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50782.093023 # average ReadExReq mshr miss latency
824 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50782.093023 # average ReadExReq mshr miss latency
825 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54266.682903 # average overall mshr miss latency
826 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53045.480549 # average overall mshr miss latency
827 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53705.077611 # average overall mshr miss latency
828 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54266.682903 # average overall mshr miss latency
829 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53045.480549 # average overall mshr miss latency
830 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53705.077611 # average overall mshr miss latency
831 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
832 system.cpu.dcache.tags.replacements 57 # number of replacements
833 system.cpu.dcache.tags.tagsinuse 1404.261851 # Cycle average of tags in use
834 system.cpu.dcache.tags.total_refs 46798452 # Total number of references to valid blocks.
835 system.cpu.dcache.tags.sampled_refs 1855 # Sample count of references to valid blocks.
836 system.cpu.dcache.tags.avg_refs 25228.276011 # Average number of references to valid blocks.
837 system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
838 system.cpu.dcache.tags.occ_blocks::cpu.data 1404.261851 # Average occupied blocks per requestor
839 system.cpu.dcache.tags.occ_percent::cpu.data 0.342837 # Average percentage of cache occupancy
840 system.cpu.dcache.tags.occ_percent::total 0.342837 # Average percentage of cache occupancy
841 system.cpu.dcache.ReadReq_hits::cpu.data 34397014 # number of ReadReq hits
842 system.cpu.dcache.ReadReq_hits::total 34397014 # number of ReadReq hits
843 system.cpu.dcache.WriteReq_hits::cpu.data 12356557 # number of WriteReq hits
844 system.cpu.dcache.WriteReq_hits::total 12356557 # number of WriteReq hits
845 system.cpu.dcache.LoadLockedReq_hits::cpu.data 22472 # number of LoadLockedReq hits
846 system.cpu.dcache.LoadLockedReq_hits::total 22472 # number of LoadLockedReq hits
847 system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits
848 system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits
849 system.cpu.dcache.demand_hits::cpu.data 46753571 # number of demand (read+write) hits
850 system.cpu.dcache.demand_hits::total 46753571 # number of demand (read+write) hits
851 system.cpu.dcache.overall_hits::cpu.data 46753571 # number of overall hits
852 system.cpu.dcache.overall_hits::total 46753571 # number of overall hits
853 system.cpu.dcache.ReadReq_misses::cpu.data 1913 # number of ReadReq misses
854 system.cpu.dcache.ReadReq_misses::total 1913 # number of ReadReq misses
855 system.cpu.dcache.WriteReq_misses::cpu.data 7730 # number of WriteReq misses
856 system.cpu.dcache.WriteReq_misses::total 7730 # number of WriteReq misses
857 system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
858 system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
859 system.cpu.dcache.demand_misses::cpu.data 9643 # number of demand (read+write) misses
860 system.cpu.dcache.demand_misses::total 9643 # number of demand (read+write) misses
861 system.cpu.dcache.overall_misses::cpu.data 9643 # number of overall misses
862 system.cpu.dcache.overall_misses::total 9643 # number of overall misses
863 system.cpu.dcache.ReadReq_miss_latency::cpu.data 114314976 # number of ReadReq miss cycles
864 system.cpu.dcache.ReadReq_miss_latency::total 114314976 # number of ReadReq miss cycles
865 system.cpu.dcache.WriteReq_miss_latency::cpu.data 447415748 # number of WriteReq miss cycles
866 system.cpu.dcache.WriteReq_miss_latency::total 447415748 # number of WriteReq miss cycles
867 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142500 # number of LoadLockedReq miss cycles
868 system.cpu.dcache.LoadLockedReq_miss_latency::total 142500 # number of LoadLockedReq miss cycles
869 system.cpu.dcache.demand_miss_latency::cpu.data 561730724 # number of demand (read+write) miss cycles
870 system.cpu.dcache.demand_miss_latency::total 561730724 # number of demand (read+write) miss cycles
871 system.cpu.dcache.overall_miss_latency::cpu.data 561730724 # number of overall miss cycles
872 system.cpu.dcache.overall_miss_latency::total 561730724 # number of overall miss cycles
873 system.cpu.dcache.ReadReq_accesses::cpu.data 34398927 # number of ReadReq accesses(hits+misses)
874 system.cpu.dcache.ReadReq_accesses::total 34398927 # number of ReadReq accesses(hits+misses)
875 system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
876 system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
877 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22474 # number of LoadLockedReq accesses(hits+misses)
878 system.cpu.dcache.LoadLockedReq_accesses::total 22474 # number of LoadLockedReq accesses(hits+misses)
879 system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses)
880 system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses)
881 system.cpu.dcache.demand_accesses::cpu.data 46763214 # number of demand (read+write) accesses
882 system.cpu.dcache.demand_accesses::total 46763214 # number of demand (read+write) accesses
883 system.cpu.dcache.overall_accesses::cpu.data 46763214 # number of overall (read+write) accesses
884 system.cpu.dcache.overall_accesses::total 46763214 # number of overall (read+write) accesses
885 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000056 # miss rate for ReadReq accesses
886 system.cpu.dcache.ReadReq_miss_rate::total 0.000056 # miss rate for ReadReq accesses
887 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000625 # miss rate for WriteReq accesses
888 system.cpu.dcache.WriteReq_miss_rate::total 0.000625 # miss rate for WriteReq accesses
889 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000089 # miss rate for LoadLockedReq accesses
890 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000089 # miss rate for LoadLockedReq accesses
891 system.cpu.dcache.demand_miss_rate::cpu.data 0.000206 # miss rate for demand accesses
892 system.cpu.dcache.demand_miss_rate::total 0.000206 # miss rate for demand accesses
893 system.cpu.dcache.overall_miss_rate::cpu.data 0.000206 # miss rate for overall accesses
894 system.cpu.dcache.overall_miss_rate::total 0.000206 # miss rate for overall accesses
895 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59756.913748 # average ReadReq miss latency
896 system.cpu.dcache.ReadReq_avg_miss_latency::total 59756.913748 # average ReadReq miss latency
897 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57880.433118 # average WriteReq miss latency
898 system.cpu.dcache.WriteReq_avg_miss_latency::total 57880.433118 # average WriteReq miss latency
899 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71250 # average LoadLockedReq miss latency
900 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71250 # average LoadLockedReq miss latency
901 system.cpu.dcache.demand_avg_miss_latency::cpu.data 58252.693560 # average overall miss latency
902 system.cpu.dcache.demand_avg_miss_latency::total 58252.693560 # average overall miss latency
903 system.cpu.dcache.overall_avg_miss_latency::cpu.data 58252.693560 # average overall miss latency
904 system.cpu.dcache.overall_avg_miss_latency::total 58252.693560 # average overall miss latency
905 system.cpu.dcache.blocked_cycles::no_mshrs 597 # number of cycles access was blocked
906 system.cpu.dcache.blocked_cycles::no_targets 154 # number of cycles access was blocked
907 system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked
908 system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
909 system.cpu.dcache.avg_blocked_cycles::no_mshrs 54.272727 # average number of cycles each access was blocked
910 system.cpu.dcache.avg_blocked_cycles::no_targets 77 # average number of cycles each access was blocked
911 system.cpu.dcache.fast_writes 0 # number of fast writes performed
912 system.cpu.dcache.cache_copies 0 # number of cache copies performed
913 system.cpu.dcache.writebacks::writebacks 18 # number of writebacks
914 system.cpu.dcache.writebacks::total 18 # number of writebacks
915 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1140 # number of ReadReq MSHR hits
916 system.cpu.dcache.ReadReq_mshr_hits::total 1140 # number of ReadReq MSHR hits
917 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6646 # number of WriteReq MSHR hits
918 system.cpu.dcache.WriteReq_mshr_hits::total 6646 # number of WriteReq MSHR hits
919 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
920 system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
921 system.cpu.dcache.demand_mshr_hits::cpu.data 7786 # number of demand (read+write) MSHR hits
922 system.cpu.dcache.demand_mshr_hits::total 7786 # number of demand (read+write) MSHR hits
923 system.cpu.dcache.overall_mshr_hits::cpu.data 7786 # number of overall MSHR hits
924 system.cpu.dcache.overall_mshr_hits::total 7786 # number of overall MSHR hits
925 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 773 # number of ReadReq MSHR misses
926 system.cpu.dcache.ReadReq_mshr_misses::total 773 # number of ReadReq MSHR misses
927 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1084 # number of WriteReq MSHR misses
928 system.cpu.dcache.WriteReq_mshr_misses::total 1084 # number of WriteReq MSHR misses
929 system.cpu.dcache.demand_mshr_misses::cpu.data 1857 # number of demand (read+write) MSHR misses
930 system.cpu.dcache.demand_mshr_misses::total 1857 # number of demand (read+write) MSHR misses
931 system.cpu.dcache.overall_mshr_misses::cpu.data 1857 # number of overall MSHR misses
932 system.cpu.dcache.overall_mshr_misses::total 1857 # number of overall MSHR misses
933 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 48960262 # number of ReadReq MSHR miss cycles
934 system.cpu.dcache.ReadReq_mshr_miss_latency::total 48960262 # number of ReadReq MSHR miss cycles
935 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 69313496 # number of WriteReq MSHR miss cycles
936 system.cpu.dcache.WriteReq_mshr_miss_latency::total 69313496 # number of WriteReq MSHR miss cycles
937 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 118273758 # number of demand (read+write) MSHR miss cycles
938 system.cpu.dcache.demand_mshr_miss_latency::total 118273758 # number of demand (read+write) MSHR miss cycles
939 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 118273758 # number of overall MSHR miss cycles
940 system.cpu.dcache.overall_mshr_miss_latency::total 118273758 # number of overall MSHR miss cycles
941 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses
942 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
943 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses
944 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses
945 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses
946 system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses
947 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses
948 system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses
949 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63337.984476 # average ReadReq mshr miss latency
950 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63337.984476 # average ReadReq mshr miss latency
951 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63942.339483 # average WriteReq mshr miss latency
952 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63942.339483 # average WriteReq mshr miss latency
953 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63690.768982 # average overall mshr miss latency
954 system.cpu.dcache.demand_avg_mshr_miss_latency::total 63690.768982 # average overall mshr miss latency
955 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63690.768982 # average overall mshr miss latency
956 system.cpu.dcache.overall_avg_mshr_miss_latency::total 63690.768982 # average overall mshr miss latency
957 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
959 ---------- End Simulation Statistics ----------
projects / gem5.git / blob