tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 eventq_index=0
  18 init_param=0
  19 kernel=
  20 kernel_addr_check=true
  21 load_addr_mask=1099511627775
  22 load_offset=0
  23 mem_mode=timing
  24 mem_ranges=
  25 memories=system.physmem
  26 num_work_ids=16
  27 readfile=
  28 symbolfile=
  29 work_begin_ckpt_count=0
  30 work_begin_cpu_id_exit=-1
  31 work_begin_exit_count=0
  32 work_cpus_ckpt_count=0
  33 work_end_ckpt_count=0
  34 work_end_exit_count=0
  35 work_item_id=-1
  36 system_port=system.membus.slave[0]
  37
  38 [system.clk_domain]
  39 type=SrcClockDomain
  40 clock=1000
  41 domain_id=-1
  42 eventq_index=0
  43 init_perf_level=0
  44 voltage_domain=system.voltage_domain
  45
  46 [system.cpu]
  47 type=TimingSimpleCPU
  48 children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
  49 branchPred=Null
  50 checker=Null
  51 clk_domain=system.cpu_clk_domain
  52 cpu_id=0
  53 do_checkpoint_insts=true
  54 do_quiesce=true
  55 do_statistics_insts=true
  56 dstage2_mmu=system.cpu.dstage2_mmu
  57 dtb=system.cpu.dtb
  58 eventq_index=0
  59 function_trace=false
  60 function_trace_start=0
  61 interrupts=system.cpu.interrupts
  62 isa=system.cpu.isa
  63 istage2_mmu=system.cpu.istage2_mmu
  64 itb=system.cpu.itb
  65 max_insts_all_threads=0
  66 max_insts_any_thread=0
  67 max_loads_all_threads=0
  68 max_loads_any_thread=0
  69 numThreads=1
  70 profile=0
  71 progress_interval=0
  72 simpoint_start_insts=
  73 socket_id=0
  74 switched_out=false
  75 system=system
  76 tracer=system.cpu.tracer
  77 workload=system.cpu.workload
  78 dcache_port=system.cpu.dcache.cpu_side
  79 icache_port=system.cpu.icache.cpu_side
  80
  81 [system.cpu.dcache]
  82 type=BaseCache
  83 children=tags
  84 addr_ranges=0:18446744073709551615
  85 assoc=2
  86 clk_domain=system.cpu_clk_domain
  87 eventq_index=0
  88 forward_snoops=true
  89 hit_latency=2
  90 is_top_level=true
  91 max_miss_count=0
  92 mshrs=4
  93 prefetch_on_access=false
  94 prefetcher=Null
  95 response_latency=2
  96 sequential_access=false
  97 size=262144
  98 system=system
  99 tags=system.cpu.dcache.tags
 100 tgts_per_mshr=20
 101 two_queue=false
 102 write_buffers=8
 103 cpu_side=system.cpu.dcache_port
 104 mem_side=system.cpu.toL2Bus.slave[1]
 105
 106 [system.cpu.dcache.tags]
 107 type=LRU
 108 assoc=2
 109 block_size=64
 110 clk_domain=system.cpu_clk_domain
 111 eventq_index=0
 112 hit_latency=2
 113 sequential_access=false
 114 size=262144
 115
 116 [system.cpu.dstage2_mmu]
 117 type=ArmStage2MMU
 118 children=stage2_tlb
 119 eventq_index=0
 120 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
 121 tlb=system.cpu.dtb
 122
 123 [system.cpu.dstage2_mmu.stage2_tlb]
 124 type=ArmTLB
 125 children=walker
 126 eventq_index=0
 127 is_stage2=true
 128 size=32
 129 walker=system.cpu.dstage2_mmu.stage2_tlb.walker
 130
 131 [system.cpu.dstage2_mmu.stage2_tlb.walker]
 132 type=ArmTableWalker
 133 clk_domain=system.cpu_clk_domain
 134 eventq_index=0
 135 is_stage2=true
 136 num_squash_per_cycle=2
 137 sys=system
 138 port=system.cpu.toL2Bus.slave[5]
 139
 140 [system.cpu.dtb]
 141 type=ArmTLB
 142 children=walker
 143 eventq_index=0
 144 is_stage2=false
 145 size=64
 146 walker=system.cpu.dtb.walker
 147
 148 [system.cpu.dtb.walker]
 149 type=ArmTableWalker
 150 clk_domain=system.cpu_clk_domain
 151 eventq_index=0
 152 is_stage2=false
 153 num_squash_per_cycle=2
 154 sys=system
 155 port=system.cpu.toL2Bus.slave[3]
 156
 157 [system.cpu.icache]
 158 type=BaseCache
 159 children=tags
 160 addr_ranges=0:18446744073709551615
 161 assoc=2
 162 clk_domain=system.cpu_clk_domain
 163 eventq_index=0
 164 forward_snoops=true
 165 hit_latency=2
 166 is_top_level=true
 167 max_miss_count=0
 168 mshrs=4
 169 prefetch_on_access=false
 170 prefetcher=Null
 171 response_latency=2
 172 sequential_access=false
 173 size=131072
 174 system=system
 175 tags=system.cpu.icache.tags
 176 tgts_per_mshr=20
 177 two_queue=false
 178 write_buffers=8
 179 cpu_side=system.cpu.icache_port
 180 mem_side=system.cpu.toL2Bus.slave[0]
 181
 182 [system.cpu.icache.tags]
 183 type=LRU
 184 assoc=2
 185 block_size=64
 186 clk_domain=system.cpu_clk_domain
 187 eventq_index=0
 188 hit_latency=2
 189 sequential_access=false
 190 size=131072
 191
 192 [system.cpu.interrupts]
 193 type=ArmInterrupts
 194 eventq_index=0
 195
 196 [system.cpu.isa]
 197 type=ArmISA
 198 eventq_index=0
 199 fpsid=1090793632
 200 id_aa64afr0_el1=0
 201 id_aa64afr1_el1=0
 202 id_aa64dfr0_el1=1052678
 203 id_aa64dfr1_el1=0
 204 id_aa64isar0_el1=0
 205 id_aa64isar1_el1=0
 206 id_aa64mmfr0_el1=15728642
 207 id_aa64mmfr1_el1=0
 208 id_aa64pfr0_el1=17
 209 id_aa64pfr1_el1=0
 210 id_isar0=34607377
 211 id_isar1=34677009
 212 id_isar2=555950401
 213 id_isar3=17899825
 214 id_isar4=268501314
 215 id_isar5=0
 216 id_mmfr0=270536963
 217 id_mmfr1=0
 218 id_mmfr2=19070976
 219 id_mmfr3=34611729
 220 id_pfr0=49
 221 id_pfr1=4113
 222 midr=1091551472
 223 system=system
 224
 225 [system.cpu.istage2_mmu]
 226 type=ArmStage2MMU
 227 children=stage2_tlb
 228 eventq_index=0
 229 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
 230 tlb=system.cpu.itb
 231
 232 [system.cpu.istage2_mmu.stage2_tlb]
 233 type=ArmTLB
 234 children=walker
 235 eventq_index=0
 236 is_stage2=true
 237 size=32
 238 walker=system.cpu.istage2_mmu.stage2_tlb.walker
 239
 240 [system.cpu.istage2_mmu.stage2_tlb.walker]
 241 type=ArmTableWalker
 242 clk_domain=system.cpu_clk_domain
 243 eventq_index=0
 244 is_stage2=true
 245 num_squash_per_cycle=2
 246 sys=system
 247 port=system.cpu.toL2Bus.slave[4]
 248
 249 [system.cpu.itb]
 250 type=ArmTLB
 251 children=walker
 252 eventq_index=0
 253 is_stage2=false
 254 size=64
 255 walker=system.cpu.itb.walker
 256
 257 [system.cpu.itb.walker]
 258 type=ArmTableWalker
 259 clk_domain=system.cpu_clk_domain
 260 eventq_index=0
 261 is_stage2=false
 262 num_squash_per_cycle=2
 263 sys=system
 264 port=system.cpu.toL2Bus.slave[2]
 265
 266 [system.cpu.l2cache]
 267 type=BaseCache
 268 children=tags
 269 addr_ranges=0:18446744073709551615
 270 assoc=8
 271 clk_domain=system.cpu_clk_domain
 272 eventq_index=0
 273 forward_snoops=true
 274 hit_latency=20
 275 is_top_level=false
 276 max_miss_count=0
 277 mshrs=20
 278 prefetch_on_access=false
 279 prefetcher=Null
 280 response_latency=20
 281 sequential_access=false
 282 size=2097152
 283 system=system
 284 tags=system.cpu.l2cache.tags
 285 tgts_per_mshr=12
 286 two_queue=false
 287 write_buffers=8
 288 cpu_side=system.cpu.toL2Bus.master[0]
 289 mem_side=system.membus.slave[1]
 290
 291 [system.cpu.l2cache.tags]
 292 type=LRU
 293 assoc=8
 294 block_size=64
 295 clk_domain=system.cpu_clk_domain
 296 eventq_index=0
 297 hit_latency=20
 298 sequential_access=false
 299 size=2097152
 300
 301 [system.cpu.toL2Bus]
 302 type=CoherentBus
 303 clk_domain=system.cpu_clk_domain
 304 eventq_index=0
 305 header_cycles=1
 306 system=system
 307 use_default_range=false
 308 width=32
 309 master=system.cpu.l2cache.cpu_side
 310 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
 311
 312 [system.cpu.tracer]
 313 type=ExeTracer
 314 eventq_index=0
 315
 316 [system.cpu.workload]
 317 type=LiveProcess
 318 cmd=twolf smred
 319 cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing
 320 egid=100
 321 env=
 322 errout=cerr
 323 euid=100
 324 eventq_index=0
 325 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf
 326 gid=100
 327 input=cin
 328 max_stack_size=67108864
 329 output=cout
 330 pid=100
 331 ppid=99
 332 simpoint=0
 333 system=system
 334 uid=100
 335
 336 [system.cpu_clk_domain]
 337 type=SrcClockDomain
 338 clock=500
 339 domain_id=-1
 340 eventq_index=0
 341 init_perf_level=0
 342 voltage_domain=system.voltage_domain
 343
 344 [system.dvfs_handler]
 345 type=DVFSHandler
 346 domains=
 347 enable=false
 348 eventq_index=0
 349 sys_clk_domain=system.clk_domain
 350 transition_latency=100000000
 351
 352 [system.membus]
 353 type=CoherentBus
 354 clk_domain=system.clk_domain
 355 eventq_index=0
 356 header_cycles=1
 357 system=system
 358 use_default_range=false
 359 width=8
 360 master=system.physmem.port
 361 slave=system.system_port system.cpu.l2cache.mem_side
 362
 363 [system.physmem]
 364 type=SimpleMemory
 365 bandwidth=73.000000
 366 clk_domain=system.clk_domain
 367 conf_table_reported=true
 368 eventq_index=0
 369 in_addr_map=true
 370 latency=30000
 371 latency_var=0
 372 null=false
 373 range=0:134217727
 374 port=system.membus.master[0]
 375
 376 [system.voltage_domain]
 377 type=VoltageDomain
 378 eventq_index=0
 379 voltage=1.000000
 380