6 time_sync_period=100000000000
7 time_sync_spin_threshold=100000000
11 children=cpu membus physmem
15 load_addr_mask=1099511627775
17 memories=system.physmem
19 physmem=system.physmem
22 work_begin_ckpt_count=0
23 work_begin_cpu_id_exit=-1
24 work_begin_exit_count=0
25 work_cpus_ckpt_count=0
29 system_port=system.membus.slave[0]
33 children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
37 defer_registration=false
38 do_checkpoint_insts=true
40 do_statistics_insts=true
43 function_trace_start=0
44 interrupts=system.cpu.interrupts
46 max_insts_all_threads=0
47 max_insts_any_thread=0
48 max_loads_all_threads=0
49 max_loads_any_thread=0
55 tracer=system.cpu.tracer
56 workload=system.cpu.workload
57 dcache_port=system.cpu.dcache.cpu_side
58 icache_port=system.cpu.icache.cpu_side
62 addr_ranges=0:18446744073709551615
71 prefetch_on_access=false
73 prioritizeRequests=false
82 cpu_side=system.cpu.dcache_port
83 mem_side=system.cpu.toL2Bus.slave[1]
89 walker=system.cpu.dtb.walker
91 [system.cpu.dtb.walker]
96 port=system.cpu.toL2Bus.slave[3]
100 addr_ranges=0:18446744073709551615
109 prefetch_on_access=false
111 prioritizeRequests=false
120 cpu_side=system.cpu.icache_port
121 mem_side=system.cpu.toL2Bus.slave[0]
123 [system.cpu.interrupts]
130 walker=system.cpu.itb.walker
132 [system.cpu.itb.walker]
137 port=system.cpu.toL2Bus.slave[2]
141 addr_ranges=0:18446744073709551615
150 prefetch_on_access=false
152 prioritizeRequests=false
161 cpu_side=system.cpu.toL2Bus.master[0]
162 mem_side=system.membus.slave[1]
170 use_default_range=false
172 master=system.cpu.l2cache.cpu_side
173 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
178 [system.cpu.workload]
181 cwd=build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing
186 executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/twolf
189 max_stack_size=67108864
203 use_default_range=false
205 master=system.physmem.port[0]
206 slave=system.system_port system.cpu.l2cache.mem_side
216 port=system.membus.master[0]