2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.232072 # Number of seconds simulated
4 sim_ticks 232072304000 # Number of ticks simulated
5 final_tick 232072304000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 1198657 # Simulator instruction rate (inst/s)
8 host_op_rate 1312657 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 1618778979 # Simulator tick rate (ticks/s)
10 host_mem_usage 245268 # Number of bytes of host memory used
11 host_seconds 143.36 # Real time elapsed on the host
12 sim_insts 171842483 # Number of instructions simulated
13 sim_ops 188185920 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 110336 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 220992 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 110656 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 110656 # Number of instructions bytes read from this memory
19 system.physmem.num_reads::cpu.inst 1729 # Number of read requests responded to by this memory
20 system.physmem.num_reads::cpu.data 1724 # Number of read requests responded to by this memory
21 system.physmem.num_reads::total 3453 # Number of read requests responded to by this memory
22 system.physmem.bw_read::cpu.inst 476817 # Total read bandwidth from this memory (bytes/s)
23 system.physmem.bw_read::cpu.data 475438 # Total read bandwidth from this memory (bytes/s)
24 system.physmem.bw_read::total 952255 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_inst_read::cpu.inst 476817 # Instruction read bandwidth from this memory (bytes/s)
26 system.physmem.bw_inst_read::total 476817 # Instruction read bandwidth from this memory (bytes/s)
27 system.physmem.bw_total::cpu.inst 476817 # Total bandwidth to/from this memory (bytes/s)
28 system.physmem.bw_total::cpu.data 475438 # Total bandwidth to/from this memory (bytes/s)
29 system.physmem.bw_total::total 952255 # Total bandwidth to/from this memory (bytes/s)
30 system.membus.throughput 952255 # Throughput (bytes/s)
31 system.membus.trans_dist::ReadReq 2361 # Transaction distribution
32 system.membus.trans_dist::ReadResp 2361 # Transaction distribution
33 system.membus.trans_dist::ReadExReq 1092 # Transaction distribution
34 system.membus.trans_dist::ReadExResp 1092 # Transaction distribution
35 system.membus.pkt_count_system.cpu.l2cache.mem_side 6906 # Packet count per connected master and slave (bytes)
36 system.membus.pkt_count 6906 # Packet count per connected master and slave (bytes)
37 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 220992 # Cumulative packet size per connected master and slave (bytes)
38 system.membus.tot_pkt_size 220992 # Cumulative packet size per connected master and slave (bytes)
39 system.membus.data_through_bus 220992 # Total data (bytes)
40 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
41 system.membus.reqLayer0.occupancy 3453000 # Layer occupancy (ticks)
42 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
43 system.membus.respLayer1.occupancy 31077000 # Layer occupancy (ticks)
44 system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
45 system.cpu.dtb.inst_hits 0 # ITB inst hits
46 system.cpu.dtb.inst_misses 0 # ITB inst misses
47 system.cpu.dtb.read_hits 0 # DTB read hits
48 system.cpu.dtb.read_misses 0 # DTB read misses
49 system.cpu.dtb.write_hits 0 # DTB write hits
50 system.cpu.dtb.write_misses 0 # DTB write misses
51 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
52 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
53 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
54 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
55 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
56 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
57 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
58 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
59 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
60 system.cpu.dtb.read_accesses 0 # DTB read accesses
61 system.cpu.dtb.write_accesses 0 # DTB write accesses
62 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
63 system.cpu.dtb.hits 0 # DTB hits
64 system.cpu.dtb.misses 0 # DTB misses
65 system.cpu.dtb.accesses 0 # DTB accesses
66 system.cpu.itb.inst_hits 0 # ITB inst hits
67 system.cpu.itb.inst_misses 0 # ITB inst misses
68 system.cpu.itb.read_hits 0 # DTB read hits
69 system.cpu.itb.read_misses 0 # DTB read misses
70 system.cpu.itb.write_hits 0 # DTB write hits
71 system.cpu.itb.write_misses 0 # DTB write misses
72 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
73 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
74 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
75 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
76 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
77 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
78 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
79 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
80 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
81 system.cpu.itb.read_accesses 0 # DTB read accesses
82 system.cpu.itb.write_accesses 0 # DTB write accesses
83 system.cpu.itb.inst_accesses 0 # ITB inst accesses
84 system.cpu.itb.hits 0 # DTB hits
85 system.cpu.itb.misses 0 # DTB misses
86 system.cpu.itb.accesses 0 # DTB accesses
87 system.cpu.workload.num_syscalls 400 # Number of system calls
88 system.cpu.numCycles 464144608 # number of cpu cycles simulated
89 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
90 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
91 system.cpu.committedInsts 171842483 # Number of instructions committed
92 system.cpu.committedOps 188185920 # Number of ops (including micro ops) committed
93 system.cpu.num_int_alu_accesses 150106218 # Number of integer alu accesses
94 system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses
95 system.cpu.num_func_calls 3545028 # number of times a function call or return occured
96 system.cpu.num_conditional_control_insts 32494341 # number of instructions that are conditional controls
97 system.cpu.num_int_insts 150106218 # number of integer instructions
98 system.cpu.num_fp_insts 1752310 # number of float instructions
99 system.cpu.num_int_register_reads 898652246 # number of times the integer registers were read
100 system.cpu.num_int_register_writes 294073517 # number of times the integer registers were written
101 system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read
102 system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written
103 system.cpu.num_mem_refs 42494119 # number of memory refs
104 system.cpu.num_load_insts 29849484 # Number of load instructions
105 system.cpu.num_store_insts 12644635 # Number of store instructions
106 system.cpu.num_idle_cycles 0 # Number of idle cycles
107 system.cpu.num_busy_cycles 464144608 # Number of busy cycles
108 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
109 system.cpu.idle_fraction 0 # Percentage of idle cycles
110 system.cpu.icache.replacements 1506 # number of replacements
111 system.cpu.icache.tagsinuse 1147.986161 # Cycle average of tags in use
112 system.cpu.icache.total_refs 189857001 # Total number of references to valid blocks.
113 system.cpu.icache.sampled_refs 3051 # Sample count of references to valid blocks.
114 system.cpu.icache.avg_refs 62227.794494 # Average number of references to valid blocks.
115 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
116 system.cpu.icache.occ_blocks::cpu.inst 1147.986161 # Average occupied blocks per requestor
117 system.cpu.icache.occ_percent::cpu.inst 0.560540 # Average percentage of cache occupancy
118 system.cpu.icache.occ_percent::total 0.560540 # Average percentage of cache occupancy
119 system.cpu.icache.ReadReq_hits::cpu.inst 189857001 # number of ReadReq hits
120 system.cpu.icache.ReadReq_hits::total 189857001 # number of ReadReq hits
121 system.cpu.icache.demand_hits::cpu.inst 189857001 # number of demand (read+write) hits
122 system.cpu.icache.demand_hits::total 189857001 # number of demand (read+write) hits
123 system.cpu.icache.overall_hits::cpu.inst 189857001 # number of overall hits
124 system.cpu.icache.overall_hits::total 189857001 # number of overall hits
125 system.cpu.icache.ReadReq_misses::cpu.inst 3051 # number of ReadReq misses
126 system.cpu.icache.ReadReq_misses::total 3051 # number of ReadReq misses
127 system.cpu.icache.demand_misses::cpu.inst 3051 # number of demand (read+write) misses
128 system.cpu.icache.demand_misses::total 3051 # number of demand (read+write) misses
129 system.cpu.icache.overall_misses::cpu.inst 3051 # number of overall misses
130 system.cpu.icache.overall_misses::total 3051 # number of overall misses
131 system.cpu.icache.ReadReq_miss_latency::cpu.inst 112281000 # number of ReadReq miss cycles
132 system.cpu.icache.ReadReq_miss_latency::total 112281000 # number of ReadReq miss cycles
133 system.cpu.icache.demand_miss_latency::cpu.inst 112281000 # number of demand (read+write) miss cycles
134 system.cpu.icache.demand_miss_latency::total 112281000 # number of demand (read+write) miss cycles
135 system.cpu.icache.overall_miss_latency::cpu.inst 112281000 # number of overall miss cycles
136 system.cpu.icache.overall_miss_latency::total 112281000 # number of overall miss cycles
137 system.cpu.icache.ReadReq_accesses::cpu.inst 189860052 # number of ReadReq accesses(hits+misses)
138 system.cpu.icache.ReadReq_accesses::total 189860052 # number of ReadReq accesses(hits+misses)
139 system.cpu.icache.demand_accesses::cpu.inst 189860052 # number of demand (read+write) accesses
140 system.cpu.icache.demand_accesses::total 189860052 # number of demand (read+write) accesses
141 system.cpu.icache.overall_accesses::cpu.inst 189860052 # number of overall (read+write) accesses
142 system.cpu.icache.overall_accesses::total 189860052 # number of overall (read+write) accesses
143 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses
144 system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses
145 system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses
146 system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses
147 system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses
148 system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses
149 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36801.376598 # average ReadReq miss latency
150 system.cpu.icache.ReadReq_avg_miss_latency::total 36801.376598 # average ReadReq miss latency
151 system.cpu.icache.demand_avg_miss_latency::cpu.inst 36801.376598 # average overall miss latency
152 system.cpu.icache.demand_avg_miss_latency::total 36801.376598 # average overall miss latency
153 system.cpu.icache.overall_avg_miss_latency::cpu.inst 36801.376598 # average overall miss latency
154 system.cpu.icache.overall_avg_miss_latency::total 36801.376598 # average overall miss latency
155 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
156 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
157 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
158 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
159 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
160 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
161 system.cpu.icache.fast_writes 0 # number of fast writes performed
162 system.cpu.icache.cache_copies 0 # number of cache copies performed
163 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3051 # number of ReadReq MSHR misses
164 system.cpu.icache.ReadReq_mshr_misses::total 3051 # number of ReadReq MSHR misses
165 system.cpu.icache.demand_mshr_misses::cpu.inst 3051 # number of demand (read+write) MSHR misses
166 system.cpu.icache.demand_mshr_misses::total 3051 # number of demand (read+write) MSHR misses
167 system.cpu.icache.overall_mshr_misses::cpu.inst 3051 # number of overall MSHR misses
168 system.cpu.icache.overall_mshr_misses::total 3051 # number of overall MSHR misses
169 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 106179000 # number of ReadReq MSHR miss cycles
170 system.cpu.icache.ReadReq_mshr_miss_latency::total 106179000 # number of ReadReq MSHR miss cycles
171 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 106179000 # number of demand (read+write) MSHR miss cycles
172 system.cpu.icache.demand_mshr_miss_latency::total 106179000 # number of demand (read+write) MSHR miss cycles
173 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 106179000 # number of overall MSHR miss cycles
174 system.cpu.icache.overall_mshr_miss_latency::total 106179000 # number of overall MSHR miss cycles
175 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses
176 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses
177 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses
178 system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses
179 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses
180 system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses
181 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34801.376598 # average ReadReq mshr miss latency
182 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34801.376598 # average ReadReq mshr miss latency
183 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34801.376598 # average overall mshr miss latency
184 system.cpu.icache.demand_avg_mshr_miss_latency::total 34801.376598 # average overall mshr miss latency
185 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34801.376598 # average overall mshr miss latency
186 system.cpu.icache.overall_avg_mshr_miss_latency::total 34801.376598 # average overall mshr miss latency
187 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
188 system.cpu.l2cache.replacements 0 # number of replacements
189 system.cpu.l2cache.tagsinuse 1675.655740 # Cycle average of tags in use
190 system.cpu.l2cache.total_refs 1380 # Total number of references to valid blocks.
191 system.cpu.l2cache.sampled_refs 2369 # Sample count of references to valid blocks.
192 system.cpu.l2cache.avg_refs 0.582524 # Average number of references to valid blocks.
193 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
194 system.cpu.l2cache.occ_blocks::writebacks 3.038044 # Average occupied blocks per requestor
195 system.cpu.l2cache.occ_blocks::cpu.inst 1169.032828 # Average occupied blocks per requestor
196 system.cpu.l2cache.occ_blocks::cpu.data 503.584868 # Average occupied blocks per requestor
197 system.cpu.l2cache.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy
198 system.cpu.l2cache.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy
199 system.cpu.l2cache.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy
200 system.cpu.l2cache.occ_percent::total 0.051137 # Average percentage of cache occupancy
201 system.cpu.l2cache.ReadReq_hits::cpu.inst 1322 # number of ReadReq hits
202 system.cpu.l2cache.ReadReq_hits::cpu.data 57 # number of ReadReq hits
203 system.cpu.l2cache.ReadReq_hits::total 1379 # number of ReadReq hits
204 system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits
205 system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits
206 system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits
207 system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits
208 system.cpu.l2cache.demand_hits::cpu.inst 1322 # number of demand (read+write) hits
209 system.cpu.l2cache.demand_hits::cpu.data 65 # number of demand (read+write) hits
210 system.cpu.l2cache.demand_hits::total 1387 # number of demand (read+write) hits
211 system.cpu.l2cache.overall_hits::cpu.inst 1322 # number of overall hits
212 system.cpu.l2cache.overall_hits::cpu.data 65 # number of overall hits
213 system.cpu.l2cache.overall_hits::total 1387 # number of overall hits
214 system.cpu.l2cache.ReadReq_misses::cpu.inst 1729 # number of ReadReq misses
215 system.cpu.l2cache.ReadReq_misses::cpu.data 632 # number of ReadReq misses
216 system.cpu.l2cache.ReadReq_misses::total 2361 # number of ReadReq misses
217 system.cpu.l2cache.ReadExReq_misses::cpu.data 1092 # number of ReadExReq misses
218 system.cpu.l2cache.ReadExReq_misses::total 1092 # number of ReadExReq misses
219 system.cpu.l2cache.demand_misses::cpu.inst 1729 # number of demand (read+write) misses
220 system.cpu.l2cache.demand_misses::cpu.data 1724 # number of demand (read+write) misses
221 system.cpu.l2cache.demand_misses::total 3453 # number of demand (read+write) misses
222 system.cpu.l2cache.overall_misses::cpu.inst 1729 # number of overall misses
223 system.cpu.l2cache.overall_misses::cpu.data 1724 # number of overall misses
224 system.cpu.l2cache.overall_misses::total 3453 # number of overall misses
225 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 89908000 # number of ReadReq miss cycles
226 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32864000 # number of ReadReq miss cycles
227 system.cpu.l2cache.ReadReq_miss_latency::total 122772000 # number of ReadReq miss cycles
228 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56784000 # number of ReadExReq miss cycles
229 system.cpu.l2cache.ReadExReq_miss_latency::total 56784000 # number of ReadExReq miss cycles
230 system.cpu.l2cache.demand_miss_latency::cpu.inst 89908000 # number of demand (read+write) miss cycles
231 system.cpu.l2cache.demand_miss_latency::cpu.data 89648000 # number of demand (read+write) miss cycles
232 system.cpu.l2cache.demand_miss_latency::total 179556000 # number of demand (read+write) miss cycles
233 system.cpu.l2cache.overall_miss_latency::cpu.inst 89908000 # number of overall miss cycles
234 system.cpu.l2cache.overall_miss_latency::cpu.data 89648000 # number of overall miss cycles
235 system.cpu.l2cache.overall_miss_latency::total 179556000 # number of overall miss cycles
236 system.cpu.l2cache.ReadReq_accesses::cpu.inst 3051 # number of ReadReq accesses(hits+misses)
237 system.cpu.l2cache.ReadReq_accesses::cpu.data 689 # number of ReadReq accesses(hits+misses)
238 system.cpu.l2cache.ReadReq_accesses::total 3740 # number of ReadReq accesses(hits+misses)
239 system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses)
240 system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses)
241 system.cpu.l2cache.ReadExReq_accesses::cpu.data 1100 # number of ReadExReq accesses(hits+misses)
242 system.cpu.l2cache.ReadExReq_accesses::total 1100 # number of ReadExReq accesses(hits+misses)
243 system.cpu.l2cache.demand_accesses::cpu.inst 3051 # number of demand (read+write) accesses
244 system.cpu.l2cache.demand_accesses::cpu.data 1789 # number of demand (read+write) accesses
245 system.cpu.l2cache.demand_accesses::total 4840 # number of demand (read+write) accesses
246 system.cpu.l2cache.overall_accesses::cpu.inst 3051 # number of overall (read+write) accesses
247 system.cpu.l2cache.overall_accesses::cpu.data 1789 # number of overall (read+write) accesses
248 system.cpu.l2cache.overall_accesses::total 4840 # number of overall (read+write) accesses
249 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.566699 # miss rate for ReadReq accesses
250 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.917271 # miss rate for ReadReq accesses
251 system.cpu.l2cache.ReadReq_miss_rate::total 0.631283 # miss rate for ReadReq accesses
252 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992727 # miss rate for ReadExReq accesses
253 system.cpu.l2cache.ReadExReq_miss_rate::total 0.992727 # miss rate for ReadExReq accesses
254 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.566699 # miss rate for demand accesses
255 system.cpu.l2cache.demand_miss_rate::cpu.data 0.963667 # miss rate for demand accesses
256 system.cpu.l2cache.demand_miss_rate::total 0.713430 # miss rate for demand accesses
257 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.566699 # miss rate for overall accesses
258 system.cpu.l2cache.overall_miss_rate::cpu.data 0.963667 # miss rate for overall accesses
259 system.cpu.l2cache.overall_miss_rate::total 0.713430 # miss rate for overall accesses
260 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
261 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
262 system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
263 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
264 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
265 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
266 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
267 system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
268 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
269 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
270 system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
271 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
272 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
273 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
274 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
275 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
276 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
277 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
278 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
279 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1729 # number of ReadReq MSHR misses
280 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 632 # number of ReadReq MSHR misses
281 system.cpu.l2cache.ReadReq_mshr_misses::total 2361 # number of ReadReq MSHR misses
282 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1092 # number of ReadExReq MSHR misses
283 system.cpu.l2cache.ReadExReq_mshr_misses::total 1092 # number of ReadExReq MSHR misses
284 system.cpu.l2cache.demand_mshr_misses::cpu.inst 1729 # number of demand (read+write) MSHR misses
285 system.cpu.l2cache.demand_mshr_misses::cpu.data 1724 # number of demand (read+write) MSHR misses
286 system.cpu.l2cache.demand_mshr_misses::total 3453 # number of demand (read+write) MSHR misses
287 system.cpu.l2cache.overall_mshr_misses::cpu.inst 1729 # number of overall MSHR misses
288 system.cpu.l2cache.overall_mshr_misses::cpu.data 1724 # number of overall MSHR misses
289 system.cpu.l2cache.overall_mshr_misses::total 3453 # number of overall MSHR misses
290 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 69160000 # number of ReadReq MSHR miss cycles
291 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25280000 # number of ReadReq MSHR miss cycles
292 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 94440000 # number of ReadReq MSHR miss cycles
293 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 43680000 # number of ReadExReq MSHR miss cycles
294 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 43680000 # number of ReadExReq MSHR miss cycles
295 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 69160000 # number of demand (read+write) MSHR miss cycles
296 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 68960000 # number of demand (read+write) MSHR miss cycles
297 system.cpu.l2cache.demand_mshr_miss_latency::total 138120000 # number of demand (read+write) MSHR miss cycles
298 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 69160000 # number of overall MSHR miss cycles
299 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 68960000 # number of overall MSHR miss cycles
300 system.cpu.l2cache.overall_mshr_miss_latency::total 138120000 # number of overall MSHR miss cycles
301 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for ReadReq accesses
302 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.917271 # mshr miss rate for ReadReq accesses
303 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.631283 # mshr miss rate for ReadReq accesses
304 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992727 # mshr miss rate for ReadExReq accesses
305 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992727 # mshr miss rate for ReadExReq accesses
306 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for demand accesses
307 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for demand accesses
308 system.cpu.l2cache.demand_mshr_miss_rate::total 0.713430 # mshr miss rate for demand accesses
309 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for overall accesses
310 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for overall accesses
311 system.cpu.l2cache.overall_mshr_miss_rate::total 0.713430 # mshr miss rate for overall accesses
312 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
313 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
314 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
315 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
316 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
317 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
318 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
319 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
320 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
321 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
322 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
323 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
324 system.cpu.dcache.replacements 40 # number of replacements
325 system.cpu.dcache.tagsinuse 1363.611259 # Cycle average of tags in use
326 system.cpu.dcache.total_refs 42007358 # Total number of references to valid blocks.
327 system.cpu.dcache.sampled_refs 1789 # Sample count of references to valid blocks.
328 system.cpu.dcache.avg_refs 23480.915595 # Average number of references to valid blocks.
329 system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
330 system.cpu.dcache.occ_blocks::cpu.data 1363.611259 # Average occupied blocks per requestor
331 system.cpu.dcache.occ_percent::cpu.data 0.332913 # Average percentage of cache occupancy
332 system.cpu.dcache.occ_percent::total 0.332913 # Average percentage of cache occupancy
333 system.cpu.dcache.ReadReq_hits::cpu.data 29599357 # number of ReadReq hits
334 system.cpu.dcache.ReadReq_hits::total 29599357 # number of ReadReq hits
335 system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits
336 system.cpu.dcache.WriteReq_hits::total 12363187 # number of WriteReq hits
337 system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits
338 system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits
339 system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits
340 system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits
341 system.cpu.dcache.demand_hits::cpu.data 41962544 # number of demand (read+write) hits
342 system.cpu.dcache.demand_hits::total 41962544 # number of demand (read+write) hits
343 system.cpu.dcache.overall_hits::cpu.data 41962544 # number of overall hits
344 system.cpu.dcache.overall_hits::total 41962544 # number of overall hits
345 system.cpu.dcache.ReadReq_misses::cpu.data 689 # number of ReadReq misses
346 system.cpu.dcache.ReadReq_misses::total 689 # number of ReadReq misses
347 system.cpu.dcache.WriteReq_misses::cpu.data 1100 # number of WriteReq misses
348 system.cpu.dcache.WriteReq_misses::total 1100 # number of WriteReq misses
349 system.cpu.dcache.demand_misses::cpu.data 1789 # number of demand (read+write) misses
350 system.cpu.dcache.demand_misses::total 1789 # number of demand (read+write) misses
351 system.cpu.dcache.overall_misses::cpu.data 1789 # number of overall misses
352 system.cpu.dcache.overall_misses::total 1789 # number of overall misses
353 system.cpu.dcache.ReadReq_miss_latency::cpu.data 35501000 # number of ReadReq miss cycles
354 system.cpu.dcache.ReadReq_miss_latency::total 35501000 # number of ReadReq miss cycles
355 system.cpu.dcache.WriteReq_miss_latency::cpu.data 60164000 # number of WriteReq miss cycles
356 system.cpu.dcache.WriteReq_miss_latency::total 60164000 # number of WriteReq miss cycles
357 system.cpu.dcache.demand_miss_latency::cpu.data 95665000 # number of demand (read+write) miss cycles
358 system.cpu.dcache.demand_miss_latency::total 95665000 # number of demand (read+write) miss cycles
359 system.cpu.dcache.overall_miss_latency::cpu.data 95665000 # number of overall miss cycles
360 system.cpu.dcache.overall_miss_latency::total 95665000 # number of overall miss cycles
361 system.cpu.dcache.ReadReq_accesses::cpu.data 29600046 # number of ReadReq accesses(hits+misses)
362 system.cpu.dcache.ReadReq_accesses::total 29600046 # number of ReadReq accesses(hits+misses)
363 system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
364 system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
365 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses)
366 system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses)
367 system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses)
368 system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses)
369 system.cpu.dcache.demand_accesses::cpu.data 41964333 # number of demand (read+write) accesses
370 system.cpu.dcache.demand_accesses::total 41964333 # number of demand (read+write) accesses
371 system.cpu.dcache.overall_accesses::cpu.data 41964333 # number of overall (read+write) accesses
372 system.cpu.dcache.overall_accesses::total 41964333 # number of overall (read+write) accesses
373 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000023 # miss rate for ReadReq accesses
374 system.cpu.dcache.ReadReq_miss_rate::total 0.000023 # miss rate for ReadReq accesses
375 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses
376 system.cpu.dcache.WriteReq_miss_rate::total 0.000089 # miss rate for WriteReq accesses
377 system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses
378 system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses
379 system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses
380 system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses
381 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51525.399129 # average ReadReq miss latency
382 system.cpu.dcache.ReadReq_avg_miss_latency::total 51525.399129 # average ReadReq miss latency
383 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54694.545455 # average WriteReq miss latency
384 system.cpu.dcache.WriteReq_avg_miss_latency::total 54694.545455 # average WriteReq miss latency
385 system.cpu.dcache.demand_avg_miss_latency::cpu.data 53474.007826 # average overall miss latency
386 system.cpu.dcache.demand_avg_miss_latency::total 53474.007826 # average overall miss latency
387 system.cpu.dcache.overall_avg_miss_latency::cpu.data 53474.007826 # average overall miss latency
388 system.cpu.dcache.overall_avg_miss_latency::total 53474.007826 # average overall miss latency
389 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
390 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
391 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
392 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
393 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
394 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
395 system.cpu.dcache.fast_writes 0 # number of fast writes performed
396 system.cpu.dcache.cache_copies 0 # number of cache copies performed
397 system.cpu.dcache.writebacks::writebacks 16 # number of writebacks
398 system.cpu.dcache.writebacks::total 16 # number of writebacks
399 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 689 # number of ReadReq MSHR misses
400 system.cpu.dcache.ReadReq_mshr_misses::total 689 # number of ReadReq MSHR misses
401 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1100 # number of WriteReq MSHR misses
402 system.cpu.dcache.WriteReq_mshr_misses::total 1100 # number of WriteReq MSHR misses
403 system.cpu.dcache.demand_mshr_misses::cpu.data 1789 # number of demand (read+write) MSHR misses
404 system.cpu.dcache.demand_mshr_misses::total 1789 # number of demand (read+write) MSHR misses
405 system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses
406 system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses
407 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34123000 # number of ReadReq MSHR miss cycles
408 system.cpu.dcache.ReadReq_mshr_miss_latency::total 34123000 # number of ReadReq MSHR miss cycles
409 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57964000 # number of WriteReq MSHR miss cycles
410 system.cpu.dcache.WriteReq_mshr_miss_latency::total 57964000 # number of WriteReq MSHR miss cycles
411 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92087000 # number of demand (read+write) MSHR miss cycles
412 system.cpu.dcache.demand_mshr_miss_latency::total 92087000 # number of demand (read+write) MSHR miss cycles
413 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 92087000 # number of overall MSHR miss cycles
414 system.cpu.dcache.overall_mshr_miss_latency::total 92087000 # number of overall MSHR miss cycles
415 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses
416 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses
417 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses
418 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses
419 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for demand accesses
420 system.cpu.dcache.demand_mshr_miss_rate::total 0.000043 # mshr miss rate for demand accesses
421 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for overall accesses
422 system.cpu.dcache.overall_mshr_miss_rate::total 0.000043 # mshr miss rate for overall accesses
423 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49525.399129 # average ReadReq mshr miss latency
424 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49525.399129 # average ReadReq mshr miss latency
425 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52694.545455 # average WriteReq mshr miss latency
426 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52694.545455 # average WriteReq mshr miss latency
427 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51474.007826 # average overall mshr miss latency
428 system.cpu.dcache.demand_avg_mshr_miss_latency::total 51474.007826 # average overall mshr miss latency
429 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51474.007826 # average overall mshr miss latency
430 system.cpu.dcache.overall_avg_mshr_miss_latency::total 51474.007826 # average overall mshr miss latency
431 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
432 system.cpu.toL2Bus.throughput 1339169 # Throughput (bytes/s)
433 system.cpu.toL2Bus.trans_dist::ReadReq 3740 # Transaction distribution
434 system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution
435 system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution
436 system.cpu.toL2Bus.trans_dist::ReadExReq 1100 # Transaction distribution
437 system.cpu.toL2Bus.trans_dist::ReadExResp 1100 # Transaction distribution
438 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 6102 # Packet count per connected master and slave (bytes)
439 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3594 # Packet count per connected master and slave (bytes)
440 system.cpu.toL2Bus.pkt_count 9696 # Packet count per connected master and slave (bytes)
441 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 195264 # Cumulative packet size per connected master and slave (bytes)
442 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 115520 # Cumulative packet size per connected master and slave (bytes)
443 system.cpu.toL2Bus.tot_pkt_size 310784 # Cumulative packet size per connected master and slave (bytes)
444 system.cpu.toL2Bus.data_through_bus 310784 # Total data (bytes)
445 system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
446 system.cpu.toL2Bus.reqLayer0.occupancy 2444000 # Layer occupancy (ticks)
447 system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
448 system.cpu.toL2Bus.respLayer0.occupancy 4576500 # Layer occupancy (ticks)
449 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
450 system.cpu.toL2Bus.respLayer1.occupancy 2683500 # Layer occupancy (ticks)
451 system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
453 ---------- End Simulation Statistics ----------
projects / gem5.git / blob