2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.230173 # Number of seconds simulated
4 sim_ticks 230173357000 # Number of ticks simulated
5 final_tick 230173357000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 1246866 # Simulator instruction rate (inst/s)
8 host_op_rate 1314511 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 1670106565 # Simulator tick rate (ticks/s)
10 host_mem_usage 319316 # Number of bytes of host memory used
11 host_seconds 137.82 # Real time elapsed on the host
12 sim_insts 171842483 # Number of instructions simulated
13 sim_ops 181165370 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 110336 # Number of bytes read from this memory
18 system.physmem.bytes_read::total 220992 # Number of bytes read from this memory
19 system.physmem.bytes_inst_read::cpu.inst 110656 # Number of instructions bytes read from this memory
20 system.physmem.bytes_inst_read::total 110656 # Number of instructions bytes read from this memory
21 system.physmem.num_reads::cpu.inst 1729 # Number of read requests responded to by this memory
22 system.physmem.num_reads::cpu.data 1724 # Number of read requests responded to by this memory
23 system.physmem.num_reads::total 3453 # Number of read requests responded to by this memory
24 system.physmem.bw_read::cpu.inst 480751 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_read::cpu.data 479360 # Total read bandwidth from this memory (bytes/s)
26 system.physmem.bw_read::total 960111 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_inst_read::cpu.inst 480751 # Instruction read bandwidth from this memory (bytes/s)
28 system.physmem.bw_inst_read::total 480751 # Instruction read bandwidth from this memory (bytes/s)
29 system.physmem.bw_total::cpu.inst 480751 # Total bandwidth to/from this memory (bytes/s)
30 system.physmem.bw_total::cpu.data 479360 # Total bandwidth to/from this memory (bytes/s)
31 system.physmem.bw_total::total 960111 # Total bandwidth to/from this memory (bytes/s)
32 system.membus.throughput 960111 # Throughput (bytes/s)
33 system.membus.trans_dist::ReadReq 2361 # Transaction distribution
34 system.membus.trans_dist::ReadResp 2361 # Transaction distribution
35 system.membus.trans_dist::ReadExReq 1092 # Transaction distribution
36 system.membus.trans_dist::ReadExResp 1092 # Transaction distribution
37 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6906 # Packet count per connected master and slave (bytes)
38 system.membus.pkt_count::total 6906 # Packet count per connected master and slave (bytes)
39 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 220992 # Cumulative packet size per connected master and slave (bytes)
40 system.membus.tot_pkt_size::total 220992 # Cumulative packet size per connected master and slave (bytes)
41 system.membus.data_through_bus 220992 # Total data (bytes)
42 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
43 system.membus.reqLayer0.occupancy 3596000 # Layer occupancy (ticks)
44 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
45 system.membus.respLayer1.occupancy 31220000 # Layer occupancy (ticks)
46 system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
47 system.cpu_clk_domain.clock 500 # Clock period in ticks
48 system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
49 system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
50 system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
51 system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
52 system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
53 system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
54 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
55 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
56 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
57 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
58 system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
59 system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
60 system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
61 system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
62 system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
63 system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
64 system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
65 system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
66 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
67 system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
68 system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
69 system.cpu.dtb.inst_hits 0 # ITB inst hits
70 system.cpu.dtb.inst_misses 0 # ITB inst misses
71 system.cpu.dtb.read_hits 0 # DTB read hits
72 system.cpu.dtb.read_misses 0 # DTB read misses
73 system.cpu.dtb.write_hits 0 # DTB write hits
74 system.cpu.dtb.write_misses 0 # DTB write misses
75 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
76 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
77 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
78 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
79 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
80 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
81 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
82 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
83 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
84 system.cpu.dtb.read_accesses 0 # DTB read accesses
85 system.cpu.dtb.write_accesses 0 # DTB write accesses
86 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
87 system.cpu.dtb.hits 0 # DTB hits
88 system.cpu.dtb.misses 0 # DTB misses
89 system.cpu.dtb.accesses 0 # DTB accesses
90 system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
91 system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
92 system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
93 system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
94 system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
95 system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
96 system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
97 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
98 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
99 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
100 system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
101 system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
102 system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
103 system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
104 system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
105 system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
106 system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
107 system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
108 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
109 system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
110 system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
111 system.cpu.itb.inst_hits 0 # ITB inst hits
112 system.cpu.itb.inst_misses 0 # ITB inst misses
113 system.cpu.itb.read_hits 0 # DTB read hits
114 system.cpu.itb.read_misses 0 # DTB read misses
115 system.cpu.itb.write_hits 0 # DTB write hits
116 system.cpu.itb.write_misses 0 # DTB write misses
117 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
118 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
119 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
120 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
121 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
122 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
123 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
124 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
125 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
126 system.cpu.itb.read_accesses 0 # DTB read accesses
127 system.cpu.itb.write_accesses 0 # DTB write accesses
128 system.cpu.itb.inst_accesses 0 # ITB inst accesses
129 system.cpu.itb.hits 0 # DTB hits
130 system.cpu.itb.misses 0 # DTB misses
131 system.cpu.itb.accesses 0 # DTB accesses
132 system.cpu.workload.num_syscalls 400 # Number of system calls
133 system.cpu.numCycles 460346714 # number of cpu cycles simulated
134 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
135 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
136 system.cpu.committedInsts 171842483 # Number of instructions committed
137 system.cpu.committedOps 181165370 # Number of ops (including micro ops) committed
138 system.cpu.num_int_alu_accesses 143085668 # Number of integer alu accesses
139 system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses
140 system.cpu.num_func_calls 3545028 # number of times a function call or return occured
141 system.cpu.num_conditional_control_insts 32201008 # number of instructions that are conditional controls
142 system.cpu.num_int_insts 143085668 # number of integer instructions
143 system.cpu.num_fp_insts 1752310 # number of float instructions
144 system.cpu.num_int_register_reads 242291225 # number of times the integer registers were read
145 system.cpu.num_int_register_writes 98192342 # number of times the integer registers were written
146 system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read
147 system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written
148 system.cpu.num_cc_register_reads 626384527 # number of times the CC registers were read
149 system.cpu.num_cc_register_writes 190815535 # number of times the CC registers were written
150 system.cpu.num_mem_refs 40540779 # number of memory refs
151 system.cpu.num_load_insts 27896144 # Number of load instructions
152 system.cpu.num_store_insts 12644635 # Number of store instructions
153 system.cpu.num_idle_cycles 0 # Number of idle cycles
154 system.cpu.num_busy_cycles 460346714 # Number of busy cycles
155 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
156 system.cpu.idle_fraction 0 # Percentage of idle cycles
157 system.cpu.Branches 40300311 # Number of branches fetched
158 system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
159 system.cpu.op_class::IntAlu 138988212 76.51% 76.51% # Class of executed instruction
160 system.cpu.op_class::IntMult 908940 0.50% 77.01% # Class of executed instruction
161 system.cpu.op_class::IntDiv 0 0.00% 77.01% # Class of executed instruction
162 system.cpu.op_class::FloatAdd 0 0.00% 77.01% # Class of executed instruction
163 system.cpu.op_class::FloatCmp 0 0.00% 77.01% # Class of executed instruction
164 system.cpu.op_class::FloatCvt 0 0.00% 77.01% # Class of executed instruction
165 system.cpu.op_class::FloatMult 0 0.00% 77.01% # Class of executed instruction
166 system.cpu.op_class::FloatDiv 0 0.00% 77.01% # Class of executed instruction
167 system.cpu.op_class::FloatSqrt 0 0.00% 77.01% # Class of executed instruction
168 system.cpu.op_class::SimdAdd 0 0.00% 77.01% # Class of executed instruction
169 system.cpu.op_class::SimdAddAcc 0 0.00% 77.01% # Class of executed instruction
170 system.cpu.op_class::SimdAlu 0 0.00% 77.01% # Class of executed instruction
171 system.cpu.op_class::SimdCmp 0 0.00% 77.01% # Class of executed instruction
172 system.cpu.op_class::SimdCvt 0 0.00% 77.01% # Class of executed instruction
173 system.cpu.op_class::SimdMisc 0 0.00% 77.01% # Class of executed instruction
174 system.cpu.op_class::SimdMult 0 0.00% 77.01% # Class of executed instruction
175 system.cpu.op_class::SimdMultAcc 0 0.00% 77.01% # Class of executed instruction
176 system.cpu.op_class::SimdShift 0 0.00% 77.01% # Class of executed instruction
177 system.cpu.op_class::SimdShiftAcc 0 0.00% 77.01% # Class of executed instruction
178 system.cpu.op_class::SimdSqrt 0 0.00% 77.01% # Class of executed instruction
179 system.cpu.op_class::SimdFloatAdd 32754 0.02% 77.03% # Class of executed instruction
180 system.cpu.op_class::SimdFloatAlu 0 0.00% 77.03% # Class of executed instruction
181 system.cpu.op_class::SimdFloatCmp 154829 0.09% 77.12% # Class of executed instruction
182 system.cpu.op_class::SimdFloatCvt 238880 0.13% 77.25% # Class of executed instruction
183 system.cpu.op_class::SimdFloatDiv 76016 0.04% 77.29% # Class of executed instruction
184 system.cpu.op_class::SimdFloatMisc 437591 0.24% 77.53% # Class of executed instruction
185 system.cpu.op_class::SimdFloatMult 200806 0.11% 77.64% # Class of executed instruction
186 system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.68% # Class of executed instruction
187 system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.68% # Class of executed instruction
188 system.cpu.op_class::MemRead 27896144 15.36% 93.04% # Class of executed instruction
189 system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Class of executed instruction
190 system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
191 system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
192 system.cpu.op_class::total 181650742 # Class of executed instruction
193 system.cpu.icache.tags.replacements 1506 # number of replacements
194 system.cpu.icache.tags.tagsinuse 1147.992604 # Cycle average of tags in use
195 system.cpu.icache.tags.total_refs 189857001 # Total number of references to valid blocks.
196 system.cpu.icache.tags.sampled_refs 3051 # Sample count of references to valid blocks.
197 system.cpu.icache.tags.avg_refs 62227.794494 # Average number of references to valid blocks.
198 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
199 system.cpu.icache.tags.occ_blocks::cpu.inst 1147.992604 # Average occupied blocks per requestor
200 system.cpu.icache.tags.occ_percent::cpu.inst 0.560543 # Average percentage of cache occupancy
201 system.cpu.icache.tags.occ_percent::total 0.560543 # Average percentage of cache occupancy
202 system.cpu.icache.tags.occ_task_id_blocks::1024 1545 # Occupied blocks per task id
203 system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id
204 system.cpu.icache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id
205 system.cpu.icache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id
206 system.cpu.icache.tags.age_task_id_blocks_1024::3 270 # Occupied blocks per task id
207 system.cpu.icache.tags.age_task_id_blocks_1024::4 942 # Occupied blocks per task id
208 system.cpu.icache.tags.occ_task_id_percent::1024 0.754395 # Percentage of cache occupancy per task id
209 system.cpu.icache.tags.tag_accesses 379723155 # Number of tag accesses
210 system.cpu.icache.tags.data_accesses 379723155 # Number of data accesses
211 system.cpu.icache.ReadReq_hits::cpu.inst 189857001 # number of ReadReq hits
212 system.cpu.icache.ReadReq_hits::total 189857001 # number of ReadReq hits
213 system.cpu.icache.demand_hits::cpu.inst 189857001 # number of demand (read+write) hits
214 system.cpu.icache.demand_hits::total 189857001 # number of demand (read+write) hits
215 system.cpu.icache.overall_hits::cpu.inst 189857001 # number of overall hits
216 system.cpu.icache.overall_hits::total 189857001 # number of overall hits
217 system.cpu.icache.ReadReq_misses::cpu.inst 3051 # number of ReadReq misses
218 system.cpu.icache.ReadReq_misses::total 3051 # number of ReadReq misses
219 system.cpu.icache.demand_misses::cpu.inst 3051 # number of demand (read+write) misses
220 system.cpu.icache.demand_misses::total 3051 # number of demand (read+write) misses
221 system.cpu.icache.overall_misses::cpu.inst 3051 # number of overall misses
222 system.cpu.icache.overall_misses::total 3051 # number of overall misses
223 system.cpu.icache.ReadReq_miss_latency::cpu.inst 112370500 # number of ReadReq miss cycles
224 system.cpu.icache.ReadReq_miss_latency::total 112370500 # number of ReadReq miss cycles
225 system.cpu.icache.demand_miss_latency::cpu.inst 112370500 # number of demand (read+write) miss cycles
226 system.cpu.icache.demand_miss_latency::total 112370500 # number of demand (read+write) miss cycles
227 system.cpu.icache.overall_miss_latency::cpu.inst 112370500 # number of overall miss cycles
228 system.cpu.icache.overall_miss_latency::total 112370500 # number of overall miss cycles
229 system.cpu.icache.ReadReq_accesses::cpu.inst 189860052 # number of ReadReq accesses(hits+misses)
230 system.cpu.icache.ReadReq_accesses::total 189860052 # number of ReadReq accesses(hits+misses)
231 system.cpu.icache.demand_accesses::cpu.inst 189860052 # number of demand (read+write) accesses
232 system.cpu.icache.demand_accesses::total 189860052 # number of demand (read+write) accesses
233 system.cpu.icache.overall_accesses::cpu.inst 189860052 # number of overall (read+write) accesses
234 system.cpu.icache.overall_accesses::total 189860052 # number of overall (read+write) accesses
235 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses
236 system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses
237 system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses
238 system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses
239 system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses
240 system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses
241 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36830.711242 # average ReadReq miss latency
242 system.cpu.icache.ReadReq_avg_miss_latency::total 36830.711242 # average ReadReq miss latency
243 system.cpu.icache.demand_avg_miss_latency::cpu.inst 36830.711242 # average overall miss latency
244 system.cpu.icache.demand_avg_miss_latency::total 36830.711242 # average overall miss latency
245 system.cpu.icache.overall_avg_miss_latency::cpu.inst 36830.711242 # average overall miss latency
246 system.cpu.icache.overall_avg_miss_latency::total 36830.711242 # average overall miss latency
247 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
248 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
249 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
250 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
251 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
252 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
253 system.cpu.icache.fast_writes 0 # number of fast writes performed
254 system.cpu.icache.cache_copies 0 # number of cache copies performed
255 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3051 # number of ReadReq MSHR misses
256 system.cpu.icache.ReadReq_mshr_misses::total 3051 # number of ReadReq MSHR misses
257 system.cpu.icache.demand_mshr_misses::cpu.inst 3051 # number of demand (read+write) MSHR misses
258 system.cpu.icache.demand_mshr_misses::total 3051 # number of demand (read+write) MSHR misses
259 system.cpu.icache.overall_mshr_misses::cpu.inst 3051 # number of overall MSHR misses
260 system.cpu.icache.overall_mshr_misses::total 3051 # number of overall MSHR misses
261 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 106268500 # number of ReadReq MSHR miss cycles
262 system.cpu.icache.ReadReq_mshr_miss_latency::total 106268500 # number of ReadReq MSHR miss cycles
263 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 106268500 # number of demand (read+write) MSHR miss cycles
264 system.cpu.icache.demand_mshr_miss_latency::total 106268500 # number of demand (read+write) MSHR miss cycles
265 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 106268500 # number of overall MSHR miss cycles
266 system.cpu.icache.overall_mshr_miss_latency::total 106268500 # number of overall MSHR miss cycles
267 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses
268 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses
269 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses
270 system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses
271 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses
272 system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses
273 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34830.711242 # average ReadReq mshr miss latency
274 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34830.711242 # average ReadReq mshr miss latency
275 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34830.711242 # average overall mshr miss latency
276 system.cpu.icache.demand_avg_mshr_miss_latency::total 34830.711242 # average overall mshr miss latency
277 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34830.711242 # average overall mshr miss latency
278 system.cpu.icache.overall_avg_mshr_miss_latency::total 34830.711242 # average overall mshr miss latency
279 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
280 system.cpu.l2cache.tags.replacements 0 # number of replacements
281 system.cpu.l2cache.tags.tagsinuse 1675.663358 # Cycle average of tags in use
282 system.cpu.l2cache.tags.total_refs 1380 # Total number of references to valid blocks.
283 system.cpu.l2cache.tags.sampled_refs 2369 # Sample count of references to valid blocks.
284 system.cpu.l2cache.tags.avg_refs 0.582524 # Average number of references to valid blocks.
285 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
286 system.cpu.l2cache.tags.occ_blocks::writebacks 3.037779 # Average occupied blocks per requestor
287 system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.036759 # Average occupied blocks per requestor
288 system.cpu.l2cache.tags.occ_blocks::cpu.data 503.588821 # Average occupied blocks per requestor
289 system.cpu.l2cache.tags.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy
290 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy
291 system.cpu.l2cache.tags.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy
292 system.cpu.l2cache.tags.occ_percent::total 0.051137 # Average percentage of cache occupancy
293 system.cpu.l2cache.tags.occ_task_id_blocks::1024 2369 # Occupied blocks per task id
294 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
295 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id
296 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id
297 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 322 # Occupied blocks per task id
298 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1679 # Occupied blocks per task id
299 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.072296 # Percentage of cache occupancy per task id
300 system.cpu.l2cache.tags.tag_accesses 42317 # Number of tag accesses
301 system.cpu.l2cache.tags.data_accesses 42317 # Number of data accesses
302 system.cpu.l2cache.ReadReq_hits::cpu.inst 1322 # number of ReadReq hits
303 system.cpu.l2cache.ReadReq_hits::cpu.data 57 # number of ReadReq hits
304 system.cpu.l2cache.ReadReq_hits::total 1379 # number of ReadReq hits
305 system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits
306 system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits
307 system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits
308 system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits
309 system.cpu.l2cache.demand_hits::cpu.inst 1322 # number of demand (read+write) hits
310 system.cpu.l2cache.demand_hits::cpu.data 65 # number of demand (read+write) hits
311 system.cpu.l2cache.demand_hits::total 1387 # number of demand (read+write) hits
312 system.cpu.l2cache.overall_hits::cpu.inst 1322 # number of overall hits
313 system.cpu.l2cache.overall_hits::cpu.data 65 # number of overall hits
314 system.cpu.l2cache.overall_hits::total 1387 # number of overall hits
315 system.cpu.l2cache.ReadReq_misses::cpu.inst 1729 # number of ReadReq misses
316 system.cpu.l2cache.ReadReq_misses::cpu.data 632 # number of ReadReq misses
317 system.cpu.l2cache.ReadReq_misses::total 2361 # number of ReadReq misses
318 system.cpu.l2cache.ReadExReq_misses::cpu.data 1092 # number of ReadExReq misses
319 system.cpu.l2cache.ReadExReq_misses::total 1092 # number of ReadExReq misses
320 system.cpu.l2cache.demand_misses::cpu.inst 1729 # number of demand (read+write) misses
321 system.cpu.l2cache.demand_misses::cpu.data 1724 # number of demand (read+write) misses
322 system.cpu.l2cache.demand_misses::total 3453 # number of demand (read+write) misses
323 system.cpu.l2cache.overall_misses::cpu.inst 1729 # number of overall misses
324 system.cpu.l2cache.overall_misses::cpu.data 1724 # number of overall misses
325 system.cpu.l2cache.overall_misses::total 3453 # number of overall misses
326 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 89997500 # number of ReadReq miss cycles
327 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32887000 # number of ReadReq miss cycles
328 system.cpu.l2cache.ReadReq_miss_latency::total 122884500 # number of ReadReq miss cycles
329 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56814500 # number of ReadExReq miss cycles
330 system.cpu.l2cache.ReadExReq_miss_latency::total 56814500 # number of ReadExReq miss cycles
331 system.cpu.l2cache.demand_miss_latency::cpu.inst 89997500 # number of demand (read+write) miss cycles
332 system.cpu.l2cache.demand_miss_latency::cpu.data 89701500 # number of demand (read+write) miss cycles
333 system.cpu.l2cache.demand_miss_latency::total 179699000 # number of demand (read+write) miss cycles
334 system.cpu.l2cache.overall_miss_latency::cpu.inst 89997500 # number of overall miss cycles
335 system.cpu.l2cache.overall_miss_latency::cpu.data 89701500 # number of overall miss cycles
336 system.cpu.l2cache.overall_miss_latency::total 179699000 # number of overall miss cycles
337 system.cpu.l2cache.ReadReq_accesses::cpu.inst 3051 # number of ReadReq accesses(hits+misses)
338 system.cpu.l2cache.ReadReq_accesses::cpu.data 689 # number of ReadReq accesses(hits+misses)
339 system.cpu.l2cache.ReadReq_accesses::total 3740 # number of ReadReq accesses(hits+misses)
340 system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses)
341 system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses)
342 system.cpu.l2cache.ReadExReq_accesses::cpu.data 1100 # number of ReadExReq accesses(hits+misses)
343 system.cpu.l2cache.ReadExReq_accesses::total 1100 # number of ReadExReq accesses(hits+misses)
344 system.cpu.l2cache.demand_accesses::cpu.inst 3051 # number of demand (read+write) accesses
345 system.cpu.l2cache.demand_accesses::cpu.data 1789 # number of demand (read+write) accesses
346 system.cpu.l2cache.demand_accesses::total 4840 # number of demand (read+write) accesses
347 system.cpu.l2cache.overall_accesses::cpu.inst 3051 # number of overall (read+write) accesses
348 system.cpu.l2cache.overall_accesses::cpu.data 1789 # number of overall (read+write) accesses
349 system.cpu.l2cache.overall_accesses::total 4840 # number of overall (read+write) accesses
350 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.566699 # miss rate for ReadReq accesses
351 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.917271 # miss rate for ReadReq accesses
352 system.cpu.l2cache.ReadReq_miss_rate::total 0.631283 # miss rate for ReadReq accesses
353 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992727 # miss rate for ReadExReq accesses
354 system.cpu.l2cache.ReadExReq_miss_rate::total 0.992727 # miss rate for ReadExReq accesses
355 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.566699 # miss rate for demand accesses
356 system.cpu.l2cache.demand_miss_rate::cpu.data 0.963667 # miss rate for demand accesses
357 system.cpu.l2cache.demand_miss_rate::total 0.713430 # miss rate for demand accesses
358 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.566699 # miss rate for overall accesses
359 system.cpu.l2cache.overall_miss_rate::cpu.data 0.963667 # miss rate for overall accesses
360 system.cpu.l2cache.overall_miss_rate::total 0.713430 # miss rate for overall accesses
361 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52051.764025 # average ReadReq miss latency
362 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52036.392405 # average ReadReq miss latency
363 system.cpu.l2cache.ReadReq_avg_miss_latency::total 52047.649301 # average ReadReq miss latency
364 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52027.930403 # average ReadExReq miss latency
365 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52027.930403 # average ReadExReq miss latency
366 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52051.764025 # average overall miss latency
367 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52031.032483 # average overall miss latency
368 system.cpu.l2cache.demand_avg_miss_latency::total 52041.413264 # average overall miss latency
369 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52051.764025 # average overall miss latency
370 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52031.032483 # average overall miss latency
371 system.cpu.l2cache.overall_avg_miss_latency::total 52041.413264 # average overall miss latency
372 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
373 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
374 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
375 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
376 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
377 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
378 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
379 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
380 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1729 # number of ReadReq MSHR misses
381 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 632 # number of ReadReq MSHR misses
382 system.cpu.l2cache.ReadReq_mshr_misses::total 2361 # number of ReadReq MSHR misses
383 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1092 # number of ReadExReq MSHR misses
384 system.cpu.l2cache.ReadExReq_mshr_misses::total 1092 # number of ReadExReq MSHR misses
385 system.cpu.l2cache.demand_mshr_misses::cpu.inst 1729 # number of demand (read+write) MSHR misses
386 system.cpu.l2cache.demand_mshr_misses::cpu.data 1724 # number of demand (read+write) MSHR misses
387 system.cpu.l2cache.demand_mshr_misses::total 3453 # number of demand (read+write) MSHR misses
388 system.cpu.l2cache.overall_mshr_misses::cpu.inst 1729 # number of overall MSHR misses
389 system.cpu.l2cache.overall_mshr_misses::cpu.data 1724 # number of overall MSHR misses
390 system.cpu.l2cache.overall_mshr_misses::total 3453 # number of overall MSHR misses
391 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 69160000 # number of ReadReq MSHR miss cycles
392 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25280000 # number of ReadReq MSHR miss cycles
393 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 94440000 # number of ReadReq MSHR miss cycles
394 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 43680000 # number of ReadExReq MSHR miss cycles
395 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 43680000 # number of ReadExReq MSHR miss cycles
396 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 69160000 # number of demand (read+write) MSHR miss cycles
397 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 68960000 # number of demand (read+write) MSHR miss cycles
398 system.cpu.l2cache.demand_mshr_miss_latency::total 138120000 # number of demand (read+write) MSHR miss cycles
399 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 69160000 # number of overall MSHR miss cycles
400 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 68960000 # number of overall MSHR miss cycles
401 system.cpu.l2cache.overall_mshr_miss_latency::total 138120000 # number of overall MSHR miss cycles
402 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for ReadReq accesses
403 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.917271 # mshr miss rate for ReadReq accesses
404 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.631283 # mshr miss rate for ReadReq accesses
405 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992727 # mshr miss rate for ReadExReq accesses
406 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992727 # mshr miss rate for ReadExReq accesses
407 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for demand accesses
408 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for demand accesses
409 system.cpu.l2cache.demand_mshr_miss_rate::total 0.713430 # mshr miss rate for demand accesses
410 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for overall accesses
411 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for overall accesses
412 system.cpu.l2cache.overall_mshr_miss_rate::total 0.713430 # mshr miss rate for overall accesses
413 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
414 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
415 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
416 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
417 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
418 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
419 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
420 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
421 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
422 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
423 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
424 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
425 system.cpu.dcache.tags.replacements 40 # number of replacements
426 system.cpu.dcache.tags.tagsinuse 1363.619284 # Cycle average of tags in use
427 system.cpu.dcache.tags.total_refs 40162626 # Total number of references to valid blocks.
428 system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks.
429 system.cpu.dcache.tags.avg_refs 22449.762996 # Average number of references to valid blocks.
430 system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
431 system.cpu.dcache.tags.occ_blocks::cpu.data 1363.619284 # Average occupied blocks per requestor
432 system.cpu.dcache.tags.occ_percent::cpu.data 0.332915 # Average percentage of cache occupancy
433 system.cpu.dcache.tags.occ_percent::total 0.332915 # Average percentage of cache occupancy
434 system.cpu.dcache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id
435 system.cpu.dcache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id
436 system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id
437 system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id
438 system.cpu.dcache.tags.age_task_id_blocks_1024::3 302 # Occupied blocks per task id
439 system.cpu.dcache.tags.age_task_id_blocks_1024::4 1345 # Occupied blocks per task id
440 system.cpu.dcache.tags.occ_task_id_percent::1024 0.427002 # Percentage of cache occupancy per task id
441 system.cpu.dcache.tags.tag_accesses 80330619 # Number of tag accesses
442 system.cpu.dcache.tags.data_accesses 80330619 # Number of data accesses
443 system.cpu.dcache.ReadReq_hits::cpu.data 27754163 # number of ReadReq hits
444 system.cpu.dcache.ReadReq_hits::total 27754163 # number of ReadReq hits
445 system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits
446 system.cpu.dcache.WriteReq_hits::total 12363187 # number of WriteReq hits
447 system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits
448 system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits
449 system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits
450 system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits
451 system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits
452 system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits
453 system.cpu.dcache.demand_hits::cpu.data 40117350 # number of demand (read+write) hits
454 system.cpu.dcache.demand_hits::total 40117350 # number of demand (read+write) hits
455 system.cpu.dcache.overall_hits::cpu.data 40117812 # number of overall hits
456 system.cpu.dcache.overall_hits::total 40117812 # number of overall hits
457 system.cpu.dcache.ReadReq_misses::cpu.data 688 # number of ReadReq misses
458 system.cpu.dcache.ReadReq_misses::total 688 # number of ReadReq misses
459 system.cpu.dcache.WriteReq_misses::cpu.data 1100 # number of WriteReq misses
460 system.cpu.dcache.WriteReq_misses::total 1100 # number of WriteReq misses
461 system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses
462 system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses
463 system.cpu.dcache.demand_misses::cpu.data 1788 # number of demand (read+write) misses
464 system.cpu.dcache.demand_misses::total 1788 # number of demand (read+write) misses
465 system.cpu.dcache.overall_misses::cpu.data 1789 # number of overall misses
466 system.cpu.dcache.overall_misses::total 1789 # number of overall misses
467 system.cpu.dcache.ReadReq_miss_latency::cpu.data 35469000 # number of ReadReq miss cycles
468 system.cpu.dcache.ReadReq_miss_latency::total 35469000 # number of ReadReq miss cycles
469 system.cpu.dcache.WriteReq_miss_latency::cpu.data 60194500 # number of WriteReq miss cycles
470 system.cpu.dcache.WriteReq_miss_latency::total 60194500 # number of WriteReq miss cycles
471 system.cpu.dcache.demand_miss_latency::cpu.data 95663500 # number of demand (read+write) miss cycles
472 system.cpu.dcache.demand_miss_latency::total 95663500 # number of demand (read+write) miss cycles
473 system.cpu.dcache.overall_miss_latency::cpu.data 95663500 # number of overall miss cycles
474 system.cpu.dcache.overall_miss_latency::total 95663500 # number of overall miss cycles
475 system.cpu.dcache.ReadReq_accesses::cpu.data 27754851 # number of ReadReq accesses(hits+misses)
476 system.cpu.dcache.ReadReq_accesses::total 27754851 # number of ReadReq accesses(hits+misses)
477 system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
478 system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
479 system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses)
480 system.cpu.dcache.SoftPFReq_accesses::total 463 # number of SoftPFReq accesses(hits+misses)
481 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses)
482 system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses)
483 system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses)
484 system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses)
485 system.cpu.dcache.demand_accesses::cpu.data 40119138 # number of demand (read+write) accesses
486 system.cpu.dcache.demand_accesses::total 40119138 # number of demand (read+write) accesses
487 system.cpu.dcache.overall_accesses::cpu.data 40119601 # number of overall (read+write) accesses
488 system.cpu.dcache.overall_accesses::total 40119601 # number of overall (read+write) accesses
489 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000025 # miss rate for ReadReq accesses
490 system.cpu.dcache.ReadReq_miss_rate::total 0.000025 # miss rate for ReadReq accesses
491 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses
492 system.cpu.dcache.WriteReq_miss_rate::total 0.000089 # miss rate for WriteReq accesses
493 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002160 # miss rate for SoftPFReq accesses
494 system.cpu.dcache.SoftPFReq_miss_rate::total 0.002160 # miss rate for SoftPFReq accesses
495 system.cpu.dcache.demand_miss_rate::cpu.data 0.000045 # miss rate for demand accesses
496 system.cpu.dcache.demand_miss_rate::total 0.000045 # miss rate for demand accesses
497 system.cpu.dcache.overall_miss_rate::cpu.data 0.000045 # miss rate for overall accesses
498 system.cpu.dcache.overall_miss_rate::total 0.000045 # miss rate for overall accesses
499 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51553.779070 # average ReadReq miss latency
500 system.cpu.dcache.ReadReq_avg_miss_latency::total 51553.779070 # average ReadReq miss latency
501 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54722.272727 # average WriteReq miss latency
502 system.cpu.dcache.WriteReq_avg_miss_latency::total 54722.272727 # average WriteReq miss latency
503 system.cpu.dcache.demand_avg_miss_latency::cpu.data 53503.076063 # average overall miss latency
504 system.cpu.dcache.demand_avg_miss_latency::total 53503.076063 # average overall miss latency
505 system.cpu.dcache.overall_avg_miss_latency::cpu.data 53473.169368 # average overall miss latency
506 system.cpu.dcache.overall_avg_miss_latency::total 53473.169368 # average overall miss latency
507 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
508 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
509 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
510 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
511 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
512 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
513 system.cpu.dcache.fast_writes 0 # number of fast writes performed
514 system.cpu.dcache.cache_copies 0 # number of cache copies performed
515 system.cpu.dcache.writebacks::writebacks 16 # number of writebacks
516 system.cpu.dcache.writebacks::total 16 # number of writebacks
517 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 688 # number of ReadReq MSHR misses
518 system.cpu.dcache.ReadReq_mshr_misses::total 688 # number of ReadReq MSHR misses
519 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1100 # number of WriteReq MSHR misses
520 system.cpu.dcache.WriteReq_mshr_misses::total 1100 # number of WriteReq MSHR misses
521 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
522 system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
523 system.cpu.dcache.demand_mshr_misses::cpu.data 1788 # number of demand (read+write) MSHR misses
524 system.cpu.dcache.demand_mshr_misses::total 1788 # number of demand (read+write) MSHR misses
525 system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses
526 system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses
527 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34093000 # number of ReadReq MSHR miss cycles
528 system.cpu.dcache.ReadReq_mshr_miss_latency::total 34093000 # number of ReadReq MSHR miss cycles
529 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57994500 # number of WriteReq MSHR miss cycles
530 system.cpu.dcache.WriteReq_mshr_miss_latency::total 57994500 # number of WriteReq MSHR miss cycles
531 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles
532 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles
533 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92087500 # number of demand (read+write) MSHR miss cycles
534 system.cpu.dcache.demand_mshr_miss_latency::total 92087500 # number of demand (read+write) MSHR miss cycles
535 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 92140500 # number of overall MSHR miss cycles
536 system.cpu.dcache.overall_mshr_miss_latency::total 92140500 # number of overall MSHR miss cycles
537 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses
538 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses
539 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses
540 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses
541 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002160 # mshr miss rate for SoftPFReq accesses
542 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002160 # mshr miss rate for SoftPFReq accesses
543 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for demand accesses
544 system.cpu.dcache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses
545 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for overall accesses
546 system.cpu.dcache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses
547 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49553.779070 # average ReadReq mshr miss latency
548 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49553.779070 # average ReadReq mshr miss latency
549 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52722.272727 # average WriteReq mshr miss latency
550 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52722.272727 # average WriteReq mshr miss latency
551 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency
552 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency
553 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51503.076063 # average overall mshr miss latency
554 system.cpu.dcache.demand_avg_mshr_miss_latency::total 51503.076063 # average overall mshr miss latency
555 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51503.912800 # average overall mshr miss latency
556 system.cpu.dcache.overall_avg_mshr_miss_latency::total 51503.912800 # average overall mshr miss latency
557 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
558 system.cpu.toL2Bus.throughput 1350217 # Throughput (bytes/s)
559 system.cpu.toL2Bus.trans_dist::ReadReq 3740 # Transaction distribution
560 system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution
561 system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution
562 system.cpu.toL2Bus.trans_dist::ReadExReq 1100 # Transaction distribution
563 system.cpu.toL2Bus.trans_dist::ReadExResp 1100 # Transaction distribution
564 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6102 # Packet count per connected master and slave (bytes)
565 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3594 # Packet count per connected master and slave (bytes)
566 system.cpu.toL2Bus.pkt_count::total 9696 # Packet count per connected master and slave (bytes)
567 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 195264 # Cumulative packet size per connected master and slave (bytes)
568 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 115520 # Cumulative packet size per connected master and slave (bytes)
569 system.cpu.toL2Bus.tot_pkt_size::total 310784 # Cumulative packet size per connected master and slave (bytes)
570 system.cpu.toL2Bus.data_through_bus 310784 # Total data (bytes)
571 system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
572 system.cpu.toL2Bus.reqLayer0.occupancy 2444000 # Layer occupancy (ticks)
573 system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
574 system.cpu.toL2Bus.respLayer0.occupancy 4576500 # Layer occupancy (ticks)
575 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
576 system.cpu.toL2Bus.respLayer1.occupancy 2683500 # Layer occupancy (ticks)
577 system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
579 ---------- End Simulation Statistics ----------
projects / gem5.git / blob