tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 default_p_state=UNDEFINED
  18 eventq_index=0
  19 exit_on_work_items=false
  20 init_param=0
  21 kernel=
  22 kernel_addr_check=true
  23 kvm_vm=Null
  24 load_addr_mask=1099511627775
  25 load_offset=0
  26 mem_mode=timing
  27 mem_ranges=
  28 memories=system.physmem
  29 mmap_using_noreserve=false
  30 multi_thread=false
  31 num_work_ids=16
  32 p_state_clk_gate_bins=20
  33 p_state_clk_gate_max=1000000000000
  34 p_state_clk_gate_min=1000
  35 power_model=Null
  36 readfile=
  37 symbolfile=
  38 thermal_components=
  39 thermal_model=Null
  40 work_begin_ckpt_count=0
  41 work_begin_cpu_id_exit=-1
  42 work_begin_exit_count=0
  43 work_cpus_ckpt_count=0
  44 work_end_ckpt_count=0
  45 work_end_exit_count=0
  46 work_item_id=-1
  47 system_port=system.membus.slave[0]
  48
  49 [system.clk_domain]
  50 type=SrcClockDomain
  51 clock=1000
  52 domain_id=-1
  53 eventq_index=0
  54 init_perf_level=0
  55 voltage_domain=system.voltage_domain
  56
  57 [system.cpu]
  58 type=DerivO3CPU
  59 children=apic_clk_domain branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
  60 LFSTSize=1024
  61 LQEntries=32
  62 LSQCheckLoads=true
  63 LSQDepCheckShift=4
  64 SQEntries=32
  65 SSITSize=1024
  66 activity=0
  67 backComSize=5
  68 branchPred=system.cpu.branchPred
  69 cacheStorePorts=200
  70 checker=Null
  71 clk_domain=system.cpu_clk_domain
  72 commitToDecodeDelay=1
  73 commitToFetchDelay=1
  74 commitToIEWDelay=1
  75 commitToRenameDelay=1
  76 commitWidth=8
  77 cpu_id=0
  78 decodeToFetchDelay=1
  79 decodeToRenameDelay=1
  80 decodeWidth=8
  81 default_p_state=UNDEFINED
  82 dispatchWidth=8
  83 do_checkpoint_insts=true
  84 do_quiesce=true
  85 do_statistics_insts=true
  86 dtb=system.cpu.dtb
  87 eventq_index=0
  88 fetchBufferSize=64
  89 fetchQueueSize=32
  90 fetchToDecodeDelay=1
  91 fetchTrapLatency=1
  92 fetchWidth=8
  93 forwardComSize=5
  94 fuPool=system.cpu.fuPool
  95 function_trace=false
  96 function_trace_start=0
  97 iewToCommitDelay=1
  98 iewToDecodeDelay=1
  99 iewToFetchDelay=1
 100 iewToRenameDelay=1
 101 interrupts=system.cpu.interrupts
 102 isa=system.cpu.isa
 103 issueToExecuteDelay=1
 104 issueWidth=8
 105 itb=system.cpu.itb
 106 max_insts_all_threads=0
 107 max_insts_any_thread=0
 108 max_loads_all_threads=0
 109 max_loads_any_thread=0
 110 needsTSO=true
 111 numIQEntries=64
 112 numPhysCCRegs=1280
 113 numPhysFloatRegs=256
 114 numPhysIntRegs=256
 115 numROBEntries=192
 116 numRobs=1
 117 numThreads=1
 118 p_state_clk_gate_bins=20
 119 p_state_clk_gate_max=1000000000000
 120 p_state_clk_gate_min=1000
 121 power_model=Null
 122 profile=0
 123 progress_interval=0
 124 renameToDecodeDelay=1
 125 renameToFetchDelay=1
 126 renameToIEWDelay=2
 127 renameToROBDelay=1
 128 renameWidth=8
 129 simpoint_start_insts=
 130 smtCommitPolicy=RoundRobin
 131 smtFetchPolicy=SingleThread
 132 smtIQPolicy=Partitioned
 133 smtIQThreshold=100
 134 smtLSQPolicy=Partitioned
 135 smtLSQThreshold=100
 136 smtNumFetchingThreads=1
 137 smtROBPolicy=Partitioned
 138 smtROBThreshold=100
 139 socket_id=0
 140 squashWidth=8
 141 store_set_clear_period=250000
 142 switched_out=false
 143 syscallRetryLatency=10000
 144 system=system
 145 tracer=system.cpu.tracer
 146 trapLatency=13
 147 wbWidth=8
 148 workload=system.cpu.workload
 149 dcache_port=system.cpu.dcache.cpu_side
 150 icache_port=system.cpu.icache.cpu_side
 151
 152 [system.cpu.apic_clk_domain]
 153 type=DerivedClockDomain
 154 clk_divider=16
 155 clk_domain=system.cpu_clk_domain
 156 eventq_index=0
 157
 158 [system.cpu.branchPred]
 159 type=TournamentBP
 160 BTBEntries=4096
 161 BTBTagSize=16
 162 RASSize=16
 163 choiceCtrBits=2
 164 choicePredictorSize=8192
 165 eventq_index=0
 166 globalCtrBits=2
 167 globalPredictorSize=8192
 168 indirectHashGHR=true
 169 indirectHashTargets=true
 170 indirectPathLength=3
 171 indirectSets=256
 172 indirectTagSize=16
 173 indirectWays=2
 174 instShiftAmt=2
 175 localCtrBits=2
 176 localHistoryTableSize=2048
 177 localPredictorSize=2048
 178 numThreads=1
 179 useIndirect=true
 180
 181 [system.cpu.dcache]
 182 type=Cache
 183 children=tags
 184 addr_ranges=0:18446744073709551615:0:0:0:0
 185 assoc=2
 186 clk_domain=system.cpu_clk_domain
 187 clusivity=mostly_incl
 188 data_latency=2
 189 default_p_state=UNDEFINED
 190 demand_mshr_reserve=1
 191 eventq_index=0
 192 is_read_only=false
 193 max_miss_count=0
 194 mshrs=4
 195 p_state_clk_gate_bins=20
 196 p_state_clk_gate_max=1000000000000
 197 p_state_clk_gate_min=1000
 198 power_model=Null
 199 prefetch_on_access=false
 200 prefetcher=Null
 201 response_latency=2
 202 sequential_access=false
 203 size=262144
 204 system=system
 205 tag_latency=2
 206 tags=system.cpu.dcache.tags
 207 tgts_per_mshr=20
 208 write_buffers=8
 209 writeback_clean=false
 210 cpu_side=system.cpu.dcache_port
 211 mem_side=system.cpu.toL2Bus.slave[1]
 212
 213 [system.cpu.dcache.tags]
 214 type=LRU
 215 assoc=2
 216 block_size=64
 217 clk_domain=system.cpu_clk_domain
 218 data_latency=2
 219 default_p_state=UNDEFINED
 220 eventq_index=0
 221 p_state_clk_gate_bins=20
 222 p_state_clk_gate_max=1000000000000
 223 p_state_clk_gate_min=1000
 224 power_model=Null
 225 sequential_access=false
 226 size=262144
 227 tag_latency=2
 228
 229 [system.cpu.dtb]
 230 type=X86TLB
 231 children=walker
 232 eventq_index=0
 233 size=64
 234 walker=system.cpu.dtb.walker
 235
 236 [system.cpu.dtb.walker]
 237 type=X86PagetableWalker
 238 clk_domain=system.cpu_clk_domain
 239 default_p_state=UNDEFINED
 240 eventq_index=0
 241 num_squash_per_cycle=4
 242 p_state_clk_gate_bins=20
 243 p_state_clk_gate_max=1000000000000
 244 p_state_clk_gate_min=1000
 245 power_model=Null
 246 system=system
 247 port=system.cpu.toL2Bus.slave[3]
 248
 249 [system.cpu.fuPool]
 250 type=FUPool
 251 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 252 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 253 eventq_index=0
 254
 255 [system.cpu.fuPool.FUList0]
 256 type=FUDesc
 257 children=opList
 258 count=6
 259 eventq_index=0
 260 opList=system.cpu.fuPool.FUList0.opList
 261
 262 [system.cpu.fuPool.FUList0.opList]
 263 type=OpDesc
 264 eventq_index=0
 265 opClass=IntAlu
 266 opLat=1
 267 pipelined=true
 268
 269 [system.cpu.fuPool.FUList1]
 270 type=FUDesc
 271 children=opList0 opList1
 272 count=2
 273 eventq_index=0
 274 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 275
 276 [system.cpu.fuPool.FUList1.opList0]
 277 type=OpDesc
 278 eventq_index=0
 279 opClass=IntMult
 280 opLat=3
 281 pipelined=true
 282
 283 [system.cpu.fuPool.FUList1.opList1]
 284 type=OpDesc
 285 eventq_index=0
 286 opClass=IntDiv
 287 opLat=1
 288 pipelined=false
 289
 290 [system.cpu.fuPool.FUList2]
 291 type=FUDesc
 292 children=opList0 opList1 opList2
 293 count=4
 294 eventq_index=0
 295 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 296
 297 [system.cpu.fuPool.FUList2.opList0]
 298 type=OpDesc
 299 eventq_index=0
 300 opClass=FloatAdd
 301 opLat=2
 302 pipelined=true
 303
 304 [system.cpu.fuPool.FUList2.opList1]
 305 type=OpDesc
 306 eventq_index=0
 307 opClass=FloatCmp
 308 opLat=2
 309 pipelined=true
 310
 311 [system.cpu.fuPool.FUList2.opList2]
 312 type=OpDesc
 313 eventq_index=0
 314 opClass=FloatCvt
 315 opLat=2
 316 pipelined=true
 317
 318 [system.cpu.fuPool.FUList3]
 319 type=FUDesc
 320 children=opList0 opList1 opList2 opList3 opList4
 321 count=2
 322 eventq_index=0
 323 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4
 324
 325 [system.cpu.fuPool.FUList3.opList0]
 326 type=OpDesc
 327 eventq_index=0
 328 opClass=FloatMult
 329 opLat=4
 330 pipelined=true
 331
 332 [system.cpu.fuPool.FUList3.opList1]
 333 type=OpDesc
 334 eventq_index=0
 335 opClass=FloatMultAcc
 336 opLat=5
 337 pipelined=true
 338
 339 [system.cpu.fuPool.FUList3.opList2]
 340 type=OpDesc
 341 eventq_index=0
 342 opClass=FloatMisc
 343 opLat=3
 344 pipelined=true
 345
 346 [system.cpu.fuPool.FUList3.opList3]
 347 type=OpDesc
 348 eventq_index=0
 349 opClass=FloatDiv
 350 opLat=12
 351 pipelined=false
 352
 353 [system.cpu.fuPool.FUList3.opList4]
 354 type=OpDesc
 355 eventq_index=0
 356 opClass=FloatSqrt
 357 opLat=24
 358 pipelined=false
 359
 360 [system.cpu.fuPool.FUList4]
 361 type=FUDesc
 362 children=opList0 opList1
 363 count=0
 364 eventq_index=0
 365 opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1
 366
 367 [system.cpu.fuPool.FUList4.opList0]
 368 type=OpDesc
 369 eventq_index=0
 370 opClass=MemRead
 371 opLat=1
 372 pipelined=true
 373
 374 [system.cpu.fuPool.FUList4.opList1]
 375 type=OpDesc
 376 eventq_index=0
 377 opClass=FloatMemRead
 378 opLat=1
 379 pipelined=true
 380
 381 [system.cpu.fuPool.FUList5]
 382 type=FUDesc
 383 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 384 count=4
 385 eventq_index=0
 386 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 387
 388 [system.cpu.fuPool.FUList5.opList00]
 389 type=OpDesc
 390 eventq_index=0
 391 opClass=SimdAdd
 392 opLat=1
 393 pipelined=true
 394
 395 [system.cpu.fuPool.FUList5.opList01]
 396 type=OpDesc
 397 eventq_index=0
 398 opClass=SimdAddAcc
 399 opLat=1
 400 pipelined=true
 401
 402 [system.cpu.fuPool.FUList5.opList02]
 403 type=OpDesc
 404 eventq_index=0
 405 opClass=SimdAlu
 406 opLat=1
 407 pipelined=true
 408
 409 [system.cpu.fuPool.FUList5.opList03]
 410 type=OpDesc
 411 eventq_index=0
 412 opClass=SimdCmp
 413 opLat=1
 414 pipelined=true
 415
 416 [system.cpu.fuPool.FUList5.opList04]
 417 type=OpDesc
 418 eventq_index=0
 419 opClass=SimdCvt
 420 opLat=1
 421 pipelined=true
 422
 423 [system.cpu.fuPool.FUList5.opList05]
 424 type=OpDesc
 425 eventq_index=0
 426 opClass=SimdMisc
 427 opLat=1
 428 pipelined=true
 429
 430 [system.cpu.fuPool.FUList5.opList06]
 431 type=OpDesc
 432 eventq_index=0
 433 opClass=SimdMult
 434 opLat=1
 435 pipelined=true
 436
 437 [system.cpu.fuPool.FUList5.opList07]
 438 type=OpDesc
 439 eventq_index=0
 440 opClass=SimdMultAcc
 441 opLat=1
 442 pipelined=true
 443
 444 [system.cpu.fuPool.FUList5.opList08]
 445 type=OpDesc
 446 eventq_index=0
 447 opClass=SimdShift
 448 opLat=1
 449 pipelined=true
 450
 451 [system.cpu.fuPool.FUList5.opList09]
 452 type=OpDesc
 453 eventq_index=0
 454 opClass=SimdShiftAcc
 455 opLat=1
 456 pipelined=true
 457
 458 [system.cpu.fuPool.FUList5.opList10]
 459 type=OpDesc
 460 eventq_index=0
 461 opClass=SimdSqrt
 462 opLat=1
 463 pipelined=true
 464
 465 [system.cpu.fuPool.FUList5.opList11]
 466 type=OpDesc
 467 eventq_index=0
 468 opClass=SimdFloatAdd
 469 opLat=1
 470 pipelined=true
 471
 472 [system.cpu.fuPool.FUList5.opList12]
 473 type=OpDesc
 474 eventq_index=0
 475 opClass=SimdFloatAlu
 476 opLat=1
 477 pipelined=true
 478
 479 [system.cpu.fuPool.FUList5.opList13]
 480 type=OpDesc
 481 eventq_index=0
 482 opClass=SimdFloatCmp
 483 opLat=1
 484 pipelined=true
 485
 486 [system.cpu.fuPool.FUList5.opList14]
 487 type=OpDesc
 488 eventq_index=0
 489 opClass=SimdFloatCvt
 490 opLat=1
 491 pipelined=true
 492
 493 [system.cpu.fuPool.FUList5.opList15]
 494 type=OpDesc
 495 eventq_index=0
 496 opClass=SimdFloatDiv
 497 opLat=1
 498 pipelined=true
 499
 500 [system.cpu.fuPool.FUList5.opList16]
 501 type=OpDesc
 502 eventq_index=0
 503 opClass=SimdFloatMisc
 504 opLat=1
 505 pipelined=true
 506
 507 [system.cpu.fuPool.FUList5.opList17]
 508 type=OpDesc
 509 eventq_index=0
 510 opClass=SimdFloatMult
 511 opLat=1
 512 pipelined=true
 513
 514 [system.cpu.fuPool.FUList5.opList18]
 515 type=OpDesc
 516 eventq_index=0
 517 opClass=SimdFloatMultAcc
 518 opLat=1
 519 pipelined=true
 520
 521 [system.cpu.fuPool.FUList5.opList19]
 522 type=OpDesc
 523 eventq_index=0
 524 opClass=SimdFloatSqrt
 525 opLat=1
 526 pipelined=true
 527
 528 [system.cpu.fuPool.FUList6]
 529 type=FUDesc
 530 children=opList0 opList1
 531 count=0
 532 eventq_index=0
 533 opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
 534
 535 [system.cpu.fuPool.FUList6.opList0]
 536 type=OpDesc
 537 eventq_index=0
 538 opClass=MemWrite
 539 opLat=1
 540 pipelined=true
 541
 542 [system.cpu.fuPool.FUList6.opList1]
 543 type=OpDesc
 544 eventq_index=0
 545 opClass=FloatMemWrite
 546 opLat=1
 547 pipelined=true
 548
 549 [system.cpu.fuPool.FUList7]
 550 type=FUDesc
 551 children=opList0 opList1 opList2 opList3
 552 count=4
 553 eventq_index=0
 554 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3
 555
 556 [system.cpu.fuPool.FUList7.opList0]
 557 type=OpDesc
 558 eventq_index=0
 559 opClass=MemRead
 560 opLat=1
 561 pipelined=true
 562
 563 [system.cpu.fuPool.FUList7.opList1]
 564 type=OpDesc
 565 eventq_index=0
 566 opClass=MemWrite
 567 opLat=1
 568 pipelined=true
 569
 570 [system.cpu.fuPool.FUList7.opList2]
 571 type=OpDesc
 572 eventq_index=0
 573 opClass=FloatMemRead
 574 opLat=1
 575 pipelined=true
 576
 577 [system.cpu.fuPool.FUList7.opList3]
 578 type=OpDesc
 579 eventq_index=0
 580 opClass=FloatMemWrite
 581 opLat=1
 582 pipelined=true
 583
 584 [system.cpu.fuPool.FUList8]
 585 type=FUDesc
 586 children=opList
 587 count=1
 588 eventq_index=0
 589 opList=system.cpu.fuPool.FUList8.opList
 590
 591 [system.cpu.fuPool.FUList8.opList]
 592 type=OpDesc
 593 eventq_index=0
 594 opClass=IprAccess
 595 opLat=3
 596 pipelined=false
 597
 598 [system.cpu.icache]
 599 type=Cache
 600 children=tags
 601 addr_ranges=0:18446744073709551615:0:0:0:0
 602 assoc=2
 603 clk_domain=system.cpu_clk_domain
 604 clusivity=mostly_incl
 605 data_latency=2
 606 default_p_state=UNDEFINED
 607 demand_mshr_reserve=1
 608 eventq_index=0
 609 is_read_only=true
 610 max_miss_count=0
 611 mshrs=4
 612 p_state_clk_gate_bins=20
 613 p_state_clk_gate_max=1000000000000
 614 p_state_clk_gate_min=1000
 615 power_model=Null
 616 prefetch_on_access=false
 617 prefetcher=Null
 618 response_latency=2
 619 sequential_access=false
 620 size=131072
 621 system=system
 622 tag_latency=2
 623 tags=system.cpu.icache.tags
 624 tgts_per_mshr=20
 625 write_buffers=8
 626 writeback_clean=true
 627 cpu_side=system.cpu.icache_port
 628 mem_side=system.cpu.toL2Bus.slave[0]
 629
 630 [system.cpu.icache.tags]
 631 type=LRU
 632 assoc=2
 633 block_size=64
 634 clk_domain=system.cpu_clk_domain
 635 data_latency=2
 636 default_p_state=UNDEFINED
 637 eventq_index=0
 638 p_state_clk_gate_bins=20
 639 p_state_clk_gate_max=1000000000000
 640 p_state_clk_gate_min=1000
 641 power_model=Null
 642 sequential_access=false
 643 size=131072
 644 tag_latency=2
 645
 646 [system.cpu.interrupts]
 647 type=X86LocalApic
 648 clk_domain=system.cpu.apic_clk_domain
 649 default_p_state=UNDEFINED
 650 eventq_index=0
 651 int_latency=1000
 652 p_state_clk_gate_bins=20
 653 p_state_clk_gate_max=1000000000000
 654 p_state_clk_gate_min=1000
 655 pio_addr=2305843009213693952
 656 pio_latency=100000
 657 power_model=Null
 658 system=system
 659 int_master=system.membus.slave[2]
 660 int_slave=system.membus.master[2]
 661 pio=system.membus.master[1]
 662
 663 [system.cpu.isa]
 664 type=X86ISA
 665 eventq_index=0
 666
 667 [system.cpu.itb]
 668 type=X86TLB
 669 children=walker
 670 eventq_index=0
 671 size=64
 672 walker=system.cpu.itb.walker
 673
 674 [system.cpu.itb.walker]
 675 type=X86PagetableWalker
 676 clk_domain=system.cpu_clk_domain
 677 default_p_state=UNDEFINED
 678 eventq_index=0
 679 num_squash_per_cycle=4
 680 p_state_clk_gate_bins=20
 681 p_state_clk_gate_max=1000000000000
 682 p_state_clk_gate_min=1000
 683 power_model=Null
 684 system=system
 685 port=system.cpu.toL2Bus.slave[2]
 686
 687 [system.cpu.l2cache]
 688 type=Cache
 689 children=tags
 690 addr_ranges=0:18446744073709551615:0:0:0:0
 691 assoc=8
 692 clk_domain=system.cpu_clk_domain
 693 clusivity=mostly_incl
 694 data_latency=20
 695 default_p_state=UNDEFINED
 696 demand_mshr_reserve=1
 697 eventq_index=0
 698 is_read_only=false
 699 max_miss_count=0
 700 mshrs=20
 701 p_state_clk_gate_bins=20
 702 p_state_clk_gate_max=1000000000000
 703 p_state_clk_gate_min=1000
 704 power_model=Null
 705 prefetch_on_access=false
 706 prefetcher=Null
 707 response_latency=20
 708 sequential_access=false
 709 size=2097152
 710 system=system
 711 tag_latency=20
 712 tags=system.cpu.l2cache.tags
 713 tgts_per_mshr=12
 714 write_buffers=8
 715 writeback_clean=false
 716 cpu_side=system.cpu.toL2Bus.master[0]
 717 mem_side=system.membus.slave[1]
 718
 719 [system.cpu.l2cache.tags]
 720 type=LRU
 721 assoc=8
 722 block_size=64
 723 clk_domain=system.cpu_clk_domain
 724 data_latency=20
 725 default_p_state=UNDEFINED
 726 eventq_index=0
 727 p_state_clk_gate_bins=20
 728 p_state_clk_gate_max=1000000000000
 729 p_state_clk_gate_min=1000
 730 power_model=Null
 731 sequential_access=false
 732 size=2097152
 733 tag_latency=20
 734
 735 [system.cpu.toL2Bus]
 736 type=CoherentXBar
 737 children=snoop_filter
 738 clk_domain=system.cpu_clk_domain
 739 default_p_state=UNDEFINED
 740 eventq_index=0
 741 forward_latency=0
 742 frontend_latency=1
 743 p_state_clk_gate_bins=20
 744 p_state_clk_gate_max=1000000000000
 745 p_state_clk_gate_min=1000
 746 point_of_coherency=false
 747 power_model=Null
 748 response_latency=1
 749 snoop_filter=system.cpu.toL2Bus.snoop_filter
 750 snoop_response_latency=1
 751 system=system
 752 use_default_range=false
 753 width=32
 754 master=system.cpu.l2cache.cpu_side
 755 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 756
 757 [system.cpu.toL2Bus.snoop_filter]
 758 type=SnoopFilter
 759 eventq_index=0
 760 lookup_latency=0
 761 max_capacity=8388608
 762 system=system
 763
 764 [system.cpu.tracer]
 765 type=ExeTracer
 766 eventq_index=0
 767
 768 [system.cpu.workload]
 769 type=Process
 770 cmd=twolf smred
 771 cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
 772 drivers=
 773 egid=100
 774 env=
 775 errout=cerr
 776 euid=100
 777 eventq_index=0
 778 executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/twolf
 779 gid=100
 780 input=cin
 781 kvmInSE=false
 782 maxStackSize=67108864
 783 output=cout
 784 pgid=100
 785 pid=100
 786 ppid=0
 787 simpoint=0
 788 system=system
 789 uid=100
 790 useArchPT=false
 791
 792 [system.cpu_clk_domain]
 793 type=SrcClockDomain
 794 clock=500
 795 domain_id=-1
 796 eventq_index=0
 797 init_perf_level=0
 798 voltage_domain=system.voltage_domain
 799
 800 [system.dvfs_handler]
 801 type=DVFSHandler
 802 domains=
 803 enable=false
 804 eventq_index=0
 805 sys_clk_domain=system.clk_domain
 806 transition_latency=100000000
 807
 808 [system.membus]
 809 type=CoherentXBar
 810 children=snoop_filter
 811 clk_domain=system.clk_domain
 812 default_p_state=UNDEFINED
 813 eventq_index=0
 814 forward_latency=4
 815 frontend_latency=3
 816 p_state_clk_gate_bins=20
 817 p_state_clk_gate_max=1000000000000
 818 p_state_clk_gate_min=1000
 819 point_of_coherency=true
 820 power_model=Null
 821 response_latency=2
 822 snoop_filter=system.membus.snoop_filter
 823 snoop_response_latency=4
 824 system=system
 825 use_default_range=false
 826 width=16
 827 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 828 slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 829
 830 [system.membus.snoop_filter]
 831 type=SnoopFilter
 832 eventq_index=0
 833 lookup_latency=1
 834 max_capacity=8388608
 835 system=system
 836
 837 [system.physmem]
 838 type=DRAMCtrl
 839 IDD0=0.055000
 840 IDD02=0.000000
 841 IDD2N=0.032000
 842 IDD2N2=0.000000
 843 IDD2P0=0.000000
 844 IDD2P02=0.000000
 845 IDD2P1=0.032000
 846 IDD2P12=0.000000
 847 IDD3N=0.038000
 848 IDD3N2=0.000000
 849 IDD3P0=0.000000
 850 IDD3P02=0.000000
 851 IDD3P1=0.038000
 852 IDD3P12=0.000000
 853 IDD4R=0.157000
 854 IDD4R2=0.000000
 855 IDD4W=0.125000
 856 IDD4W2=0.000000
 857 IDD5=0.235000
 858 IDD52=0.000000
 859 IDD6=0.020000
 860 IDD62=0.000000
 861 VDD=1.500000
 862 VDD2=0.000000
 863 activation_limit=4
 864 addr_mapping=RoRaBaCoCh
 865 bank_groups_per_rank=0
 866 banks_per_rank=8
 867 burst_length=8
 868 channels=1
 869 clk_domain=system.clk_domain
 870 conf_table_reported=true
 871 default_p_state=UNDEFINED
 872 device_bus_width=8
 873 device_rowbuffer_size=1024
 874 device_size=536870912
 875 devices_per_rank=8
 876 dll=true
 877 eventq_index=0
 878 in_addr_map=true
 879 kvm_map=true
 880 max_accesses_per_row=16
 881 mem_sched_policy=frfcfs
 882 min_writes_per_switch=16
 883 null=false
 884 p_state_clk_gate_bins=20
 885 p_state_clk_gate_max=1000000000000
 886 p_state_clk_gate_min=1000
 887 page_policy=open_adaptive
 888 power_model=Null
 889 range=0:134217727:0:0:0:0
 890 ranks_per_channel=2
 891 read_buffer_size=32
 892 static_backend_latency=10000
 893 static_frontend_latency=10000
 894 tBURST=5000
 895 tCCD_L=0
 896 tCK=1250
 897 tCL=13750
 898 tCS=2500
 899 tRAS=35000
 900 tRCD=13750
 901 tREFI=7800000
 902 tRFC=260000
 903 tRP=13750
 904 tRRD=6000
 905 tRRD_L=0
 906 tRTP=7500
 907 tRTW=2500
 908 tWR=15000
 909 tWTR=7500
 910 tXAW=30000
 911 tXP=6000
 912 tXPDLL=0
 913 tXS=270000
 914 tXSDLL=0
 915 write_buffer_size=64
 916 write_high_thresh_perc=85
 917 write_low_thresh_perc=50
 918 port=system.membus.master[0]
 919
 920 [system.voltage_domain]
 921 type=VoltageDomain
 922 eventq_index=0
 923 voltage=1.000000
 924