tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 full_system=false
   5 time_sync_enable=false
   6 time_sync_period=100000000000
   7 time_sync_spin_threshold=100000000
   8
   9 [system]
  10 type=System
  11 children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
  12 boot_osflags=a
  13 cache_line_size=64
  14 clk_domain=system.clk_domain
  15 init_param=0
  16 kernel=
  17 load_addr_mask=1099511627775
  18 mem_mode=timing
  19 mem_ranges=
  20 memories=system.physmem
  21 num_work_ids=16
  22 readfile=
  23 symbolfile=
  24 work_begin_ckpt_count=0
  25 work_begin_cpu_id_exit=-1
  26 work_begin_exit_count=0
  27 work_cpus_ckpt_count=0
  28 work_end_ckpt_count=0
  29 work_end_exit_count=0
  30 work_item_id=-1
  31 system_port=system.membus.slave[0]
  32
  33 [system.clk_domain]
  34 type=SrcClockDomain
  35 clock=1000
  36 voltage_domain=system.voltage_domain
  37
  38 [system.cpu]
  39 type=DerivO3CPU
  40 children=apic_clk_domain branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
  41 LFSTSize=1024
  42 LQEntries=32
  43 LSQCheckLoads=true
  44 LSQDepCheckShift=4
  45 SQEntries=32
  46 SSITSize=1024
  47 activity=0
  48 backComSize=5
  49 branchPred=system.cpu.branchPred
  50 cachePorts=200
  51 checker=Null
  52 clk_domain=system.cpu_clk_domain
  53 commitToDecodeDelay=1
  54 commitToFetchDelay=1
  55 commitToIEWDelay=1
  56 commitToRenameDelay=1
  57 commitWidth=8
  58 cpu_id=0
  59 decodeToFetchDelay=1
  60 decodeToRenameDelay=1
  61 decodeWidth=8
  62 dispatchWidth=8
  63 do_checkpoint_insts=true
  64 do_quiesce=true
  65 do_statistics_insts=true
  66 dtb=system.cpu.dtb
  67 fetchToDecodeDelay=1
  68 fetchTrapLatency=1
  69 fetchWidth=8
  70 forwardComSize=5
  71 fuPool=system.cpu.fuPool
  72 function_trace=false
  73 function_trace_start=0
  74 iewToCommitDelay=1
  75 iewToDecodeDelay=1
  76 iewToFetchDelay=1
  77 iewToRenameDelay=1
  78 interrupts=system.cpu.interrupts
  79 isa=system.cpu.isa
  80 issueToExecuteDelay=1
  81 issueWidth=8
  82 itb=system.cpu.itb
  83 max_insts_all_threads=0
  84 max_insts_any_thread=0
  85 max_loads_all_threads=0
  86 max_loads_any_thread=0
  87 needsTSO=true
  88 numIQEntries=64
  89 numPhysCCRegs=1280
  90 numPhysFloatRegs=256
  91 numPhysIntRegs=256
  92 numROBEntries=192
  93 numRobs=1
  94 numThreads=1
  95 profile=0
  96 progress_interval=0
  97 renameToDecodeDelay=1
  98 renameToFetchDelay=1
  99 renameToIEWDelay=2
 100 renameToROBDelay=1
 101 renameWidth=8
 102 simpoint_start_insts=
 103 smtCommitPolicy=RoundRobin
 104 smtFetchPolicy=SingleThread
 105 smtIQPolicy=Partitioned
 106 smtIQThreshold=100
 107 smtLSQPolicy=Partitioned
 108 smtLSQThreshold=100
 109 smtNumFetchingThreads=1
 110 smtROBPolicy=Partitioned
 111 smtROBThreshold=100
 112 squashWidth=8
 113 store_set_clear_period=250000
 114 switched_out=false
 115 system=system
 116 tracer=system.cpu.tracer
 117 trapLatency=13
 118 wbDepth=1
 119 wbWidth=8
 120 workload=system.cpu.workload
 121 dcache_port=system.cpu.dcache.cpu_side
 122 icache_port=system.cpu.icache.cpu_side
 123
 124 [system.cpu.apic_clk_domain]
 125 type=DerivedClockDomain
 126 clk_divider=16
 127 clk_domain=system.cpu_clk_domain
 128
 129 [system.cpu.branchPred]
 130 type=BranchPredictor
 131 BTBEntries=4096
 132 BTBTagSize=16
 133 RASSize=16
 134 choiceCtrBits=2
 135 choicePredictorSize=8192
 136 globalCtrBits=2
 137 globalPredictorSize=8192
 138 instShiftAmt=2
 139 localCtrBits=2
 140 localHistoryTableSize=2048
 141 localPredictorSize=2048
 142 numThreads=1
 143 predType=tournament
 144
 145 [system.cpu.dcache]
 146 type=BaseCache
 147 children=tags
 148 addr_ranges=0:18446744073709551615
 149 assoc=2
 150 clk_domain=system.cpu_clk_domain
 151 forward_snoops=true
 152 hit_latency=2
 153 is_top_level=true
 154 max_miss_count=0
 155 mshrs=4
 156 prefetch_on_access=false
 157 prefetcher=Null
 158 response_latency=2
 159 size=262144
 160 system=system
 161 tags=system.cpu.dcache.tags
 162 tgts_per_mshr=20
 163 two_queue=false
 164 write_buffers=8
 165 cpu_side=system.cpu.dcache_port
 166 mem_side=system.cpu.toL2Bus.slave[1]
 167
 168 [system.cpu.dcache.tags]
 169 type=LRU
 170 assoc=2
 171 block_size=64
 172 clk_domain=system.cpu_clk_domain
 173 hit_latency=2
 174 size=262144
 175
 176 [system.cpu.dtb]
 177 type=X86TLB
 178 children=walker
 179 size=64
 180 walker=system.cpu.dtb.walker
 181
 182 [system.cpu.dtb.walker]
 183 type=X86PagetableWalker
 184 clk_domain=system.cpu_clk_domain
 185 num_squash_per_cycle=4
 186 system=system
 187 port=system.cpu.toL2Bus.slave[3]
 188
 189 [system.cpu.fuPool]
 190 type=FUPool
 191 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 192 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 193
 194 [system.cpu.fuPool.FUList0]
 195 type=FUDesc
 196 children=opList
 197 count=6
 198 opList=system.cpu.fuPool.FUList0.opList
 199
 200 [system.cpu.fuPool.FUList0.opList]
 201 type=OpDesc
 202 issueLat=1
 203 opClass=IntAlu
 204 opLat=1
 205
 206 [system.cpu.fuPool.FUList1]
 207 type=FUDesc
 208 children=opList0 opList1
 209 count=2
 210 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 211
 212 [system.cpu.fuPool.FUList1.opList0]
 213 type=OpDesc
 214 issueLat=1
 215 opClass=IntMult
 216 opLat=3
 217
 218 [system.cpu.fuPool.FUList1.opList1]
 219 type=OpDesc
 220 issueLat=19
 221 opClass=IntDiv
 222 opLat=20
 223
 224 [system.cpu.fuPool.FUList2]
 225 type=FUDesc
 226 children=opList0 opList1 opList2
 227 count=4
 228 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 229
 230 [system.cpu.fuPool.FUList2.opList0]
 231 type=OpDesc
 232 issueLat=1
 233 opClass=FloatAdd
 234 opLat=2
 235
 236 [system.cpu.fuPool.FUList2.opList1]
 237 type=OpDesc
 238 issueLat=1
 239 opClass=FloatCmp
 240 opLat=2
 241
 242 [system.cpu.fuPool.FUList2.opList2]
 243 type=OpDesc
 244 issueLat=1
 245 opClass=FloatCvt
 246 opLat=2
 247
 248 [system.cpu.fuPool.FUList3]
 249 type=FUDesc
 250 children=opList0 opList1 opList2
 251 count=2
 252 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 253
 254 [system.cpu.fuPool.FUList3.opList0]
 255 type=OpDesc
 256 issueLat=1
 257 opClass=FloatMult
 258 opLat=4
 259
 260 [system.cpu.fuPool.FUList3.opList1]
 261 type=OpDesc
 262 issueLat=12
 263 opClass=FloatDiv
 264 opLat=12
 265
 266 [system.cpu.fuPool.FUList3.opList2]
 267 type=OpDesc
 268 issueLat=24
 269 opClass=FloatSqrt
 270 opLat=24
 271
 272 [system.cpu.fuPool.FUList4]
 273 type=FUDesc
 274 children=opList
 275 count=0
 276 opList=system.cpu.fuPool.FUList4.opList
 277
 278 [system.cpu.fuPool.FUList4.opList]
 279 type=OpDesc
 280 issueLat=1
 281 opClass=MemRead
 282 opLat=1
 283
 284 [system.cpu.fuPool.FUList5]
 285 type=FUDesc
 286 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 287 count=4
 288 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 289
 290 [system.cpu.fuPool.FUList5.opList00]
 291 type=OpDesc
 292 issueLat=1
 293 opClass=SimdAdd
 294 opLat=1
 295
 296 [system.cpu.fuPool.FUList5.opList01]
 297 type=OpDesc
 298 issueLat=1
 299 opClass=SimdAddAcc
 300 opLat=1
 301
 302 [system.cpu.fuPool.FUList5.opList02]
 303 type=OpDesc
 304 issueLat=1
 305 opClass=SimdAlu
 306 opLat=1
 307
 308 [system.cpu.fuPool.FUList5.opList03]
 309 type=OpDesc
 310 issueLat=1
 311 opClass=SimdCmp
 312 opLat=1
 313
 314 [system.cpu.fuPool.FUList5.opList04]
 315 type=OpDesc
 316 issueLat=1
 317 opClass=SimdCvt
 318 opLat=1
 319
 320 [system.cpu.fuPool.FUList5.opList05]
 321 type=OpDesc
 322 issueLat=1
 323 opClass=SimdMisc
 324 opLat=1
 325
 326 [system.cpu.fuPool.FUList5.opList06]
 327 type=OpDesc
 328 issueLat=1
 329 opClass=SimdMult
 330 opLat=1
 331
 332 [system.cpu.fuPool.FUList5.opList07]
 333 type=OpDesc
 334 issueLat=1
 335 opClass=SimdMultAcc
 336 opLat=1
 337
 338 [system.cpu.fuPool.FUList5.opList08]
 339 type=OpDesc
 340 issueLat=1
 341 opClass=SimdShift
 342 opLat=1
 343
 344 [system.cpu.fuPool.FUList5.opList09]
 345 type=OpDesc
 346 issueLat=1
 347 opClass=SimdShiftAcc
 348 opLat=1
 349
 350 [system.cpu.fuPool.FUList5.opList10]
 351 type=OpDesc
 352 issueLat=1
 353 opClass=SimdSqrt
 354 opLat=1
 355
 356 [system.cpu.fuPool.FUList5.opList11]
 357 type=OpDesc
 358 issueLat=1
 359 opClass=SimdFloatAdd
 360 opLat=1
 361
 362 [system.cpu.fuPool.FUList5.opList12]
 363 type=OpDesc
 364 issueLat=1
 365 opClass=SimdFloatAlu
 366 opLat=1
 367
 368 [system.cpu.fuPool.FUList5.opList13]
 369 type=OpDesc
 370 issueLat=1
 371 opClass=SimdFloatCmp
 372 opLat=1
 373
 374 [system.cpu.fuPool.FUList5.opList14]
 375 type=OpDesc
 376 issueLat=1
 377 opClass=SimdFloatCvt
 378 opLat=1
 379
 380 [system.cpu.fuPool.FUList5.opList15]
 381 type=OpDesc
 382 issueLat=1
 383 opClass=SimdFloatDiv
 384 opLat=1
 385
 386 [system.cpu.fuPool.FUList5.opList16]
 387 type=OpDesc
 388 issueLat=1
 389 opClass=SimdFloatMisc
 390 opLat=1
 391
 392 [system.cpu.fuPool.FUList5.opList17]
 393 type=OpDesc
 394 issueLat=1
 395 opClass=SimdFloatMult
 396 opLat=1
 397
 398 [system.cpu.fuPool.FUList5.opList18]
 399 type=OpDesc
 400 issueLat=1
 401 opClass=SimdFloatMultAcc
 402 opLat=1
 403
 404 [system.cpu.fuPool.FUList5.opList19]
 405 type=OpDesc
 406 issueLat=1
 407 opClass=SimdFloatSqrt
 408 opLat=1
 409
 410 [system.cpu.fuPool.FUList6]
 411 type=FUDesc
 412 children=opList
 413 count=0
 414 opList=system.cpu.fuPool.FUList6.opList
 415
 416 [system.cpu.fuPool.FUList6.opList]
 417 type=OpDesc
 418 issueLat=1
 419 opClass=MemWrite
 420 opLat=1
 421
 422 [system.cpu.fuPool.FUList7]
 423 type=FUDesc
 424 children=opList0 opList1
 425 count=4
 426 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 427
 428 [system.cpu.fuPool.FUList7.opList0]
 429 type=OpDesc
 430 issueLat=1
 431 opClass=MemRead
 432 opLat=1
 433
 434 [system.cpu.fuPool.FUList7.opList1]
 435 type=OpDesc
 436 issueLat=1
 437 opClass=MemWrite
 438 opLat=1
 439
 440 [system.cpu.fuPool.FUList8]
 441 type=FUDesc
 442 children=opList
 443 count=1
 444 opList=system.cpu.fuPool.FUList8.opList
 445
 446 [system.cpu.fuPool.FUList8.opList]
 447 type=OpDesc
 448 issueLat=3
 449 opClass=IprAccess
 450 opLat=3
 451
 452 [system.cpu.icache]
 453 type=BaseCache
 454 children=tags
 455 addr_ranges=0:18446744073709551615
 456 assoc=2
 457 clk_domain=system.cpu_clk_domain
 458 forward_snoops=true
 459 hit_latency=2
 460 is_top_level=true
 461 max_miss_count=0
 462 mshrs=4
 463 prefetch_on_access=false
 464 prefetcher=Null
 465 response_latency=2
 466 size=131072
 467 system=system
 468 tags=system.cpu.icache.tags
 469 tgts_per_mshr=20
 470 two_queue=false
 471 write_buffers=8
 472 cpu_side=system.cpu.icache_port
 473 mem_side=system.cpu.toL2Bus.slave[0]
 474
 475 [system.cpu.icache.tags]
 476 type=LRU
 477 assoc=2
 478 block_size=64
 479 clk_domain=system.cpu_clk_domain
 480 hit_latency=2
 481 size=131072
 482
 483 [system.cpu.interrupts]
 484 type=X86LocalApic
 485 clk_domain=system.cpu.apic_clk_domain
 486 int_latency=1000
 487 pio_addr=2305843009213693952
 488 pio_latency=100000
 489 system=system
 490 int_master=system.membus.slave[2]
 491 int_slave=system.membus.master[2]
 492 pio=system.membus.master[1]
 493
 494 [system.cpu.isa]
 495 type=X86ISA
 496
 497 [system.cpu.itb]
 498 type=X86TLB
 499 children=walker
 500 size=64
 501 walker=system.cpu.itb.walker
 502
 503 [system.cpu.itb.walker]
 504 type=X86PagetableWalker
 505 clk_domain=system.cpu_clk_domain
 506 num_squash_per_cycle=4
 507 system=system
 508 port=system.cpu.toL2Bus.slave[2]
 509
 510 [system.cpu.l2cache]
 511 type=BaseCache
 512 children=tags
 513 addr_ranges=0:18446744073709551615
 514 assoc=8
 515 clk_domain=system.cpu_clk_domain
 516 forward_snoops=true
 517 hit_latency=20
 518 is_top_level=false
 519 max_miss_count=0
 520 mshrs=20
 521 prefetch_on_access=false
 522 prefetcher=Null
 523 response_latency=20
 524 size=2097152
 525 system=system
 526 tags=system.cpu.l2cache.tags
 527 tgts_per_mshr=12
 528 two_queue=false
 529 write_buffers=8
 530 cpu_side=system.cpu.toL2Bus.master[0]
 531 mem_side=system.membus.slave[1]
 532
 533 [system.cpu.l2cache.tags]
 534 type=LRU
 535 assoc=8
 536 block_size=64
 537 clk_domain=system.cpu_clk_domain
 538 hit_latency=20
 539 size=2097152
 540
 541 [system.cpu.toL2Bus]
 542 type=CoherentBus
 543 clk_domain=system.cpu_clk_domain
 544 header_cycles=1
 545 system=system
 546 use_default_range=false
 547 width=32
 548 master=system.cpu.l2cache.cpu_side
 549 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 550
 551 [system.cpu.tracer]
 552 type=ExeTracer
 553
 554 [system.cpu.workload]
 555 type=LiveProcess
 556 cmd=twolf smred
 557 cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
 558 egid=100
 559 env=
 560 errout=cerr
 561 euid=100
 562 executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
 563 gid=100
 564 input=cin
 565 max_stack_size=67108864
 566 output=cout
 567 pid=100
 568 ppid=99
 569 simpoint=0
 570 system=system
 571 uid=100
 572
 573 [system.cpu_clk_domain]
 574 type=SrcClockDomain
 575 clock=500
 576 voltage_domain=system.voltage_domain
 577
 578 [system.membus]
 579 type=CoherentBus
 580 clk_domain=system.clk_domain
 581 header_cycles=1
 582 system=system
 583 use_default_range=false
 584 width=8
 585 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 586 slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 587
 588 [system.physmem]
 589 type=SimpleDRAM
 590 activation_limit=4
 591 addr_mapping=RaBaChCo
 592 banks_per_rank=8
 593 burst_length=8
 594 channels=1
 595 clk_domain=system.clk_domain
 596 conf_table_reported=true
 597 device_bus_width=8
 598 device_rowbuffer_size=1024
 599 devices_per_rank=8
 600 in_addr_map=true
 601 mem_sched_policy=frfcfs
 602 null=false
 603 page_policy=open
 604 range=0:134217727
 605 ranks_per_channel=2
 606 read_buffer_size=32
 607 static_backend_latency=10000
 608 static_frontend_latency=10000
 609 tBURST=5000
 610 tCL=13750
 611 tRCD=13750
 612 tREFI=7800000
 613 tRFC=300000
 614 tRP=13750
 615 tWTR=7500
 616 tXAW=40000
 617 write_buffer_size=32
 618 write_thresh_perc=70
 619 port=system.membus.master[0]
 620
 621 [system.voltage_domain]
 622 type=VoltageDomain
 623 voltage=1.000000
 624