5 time_sync_period=100000000000
6 time_sync_spin_threshold=100000000
10 children=cpu membus physmem
12 memories=system.physmem
14 physmem=system.physmem
15 work_begin_ckpt_count=0
16 work_begin_cpu_id_exit=-1
17 work_begin_exit_count=0
18 work_cpus_ckpt_count=0
22 system_port=system.membus.port[0]
26 children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
41 choicePredictorSize=8192
52 defer_registration=false
54 do_checkpoint_insts=true
55 do_statistics_insts=true
61 fuPool=system.cpu.fuPool
63 function_trace_start=0
66 globalPredictorSize=8192
77 localHistoryTableSize=2048
78 localPredictorSize=2048
79 max_insts_all_threads=0
80 max_insts_any_thread=0
81 max_loads_all_threads=0
82 max_loads_any_thread=0
98 smtCommitPolicy=RoundRobin
99 smtFetchPolicy=SingleThread
100 smtIQPolicy=Partitioned
102 smtLSQPolicy=Partitioned
104 smtNumFetchingThreads=1
105 smtROBPolicy=Partitioned
108 store_set_clear_period=250000
110 tracer=system.cpu.tracer
114 workload=system.cpu.workload
115 dcache_port=system.cpu.dcache.cpu_side
116 icache_port=system.cpu.icache.cpu_side
120 addr_range=0:18446744073709551615
130 prefetch_data_accesses_only=false
132 prefetch_latency=10000
133 prefetch_on_access=false
134 prefetch_past_page=false
136 prefetch_serial_squash=false
137 prefetch_use_cpu_id=true
139 prioritizeRequests=false
147 cpu_side=system.cpu.dcache_port
148 mem_side=system.cpu.toL2Bus.port[1]
156 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
157 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
159 [system.cpu.fuPool.FUList0]
163 opList=system.cpu.fuPool.FUList0.opList
165 [system.cpu.fuPool.FUList0.opList]
171 [system.cpu.fuPool.FUList1]
173 children=opList0 opList1
175 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
177 [system.cpu.fuPool.FUList1.opList0]
183 [system.cpu.fuPool.FUList1.opList1]
189 [system.cpu.fuPool.FUList2]
191 children=opList0 opList1 opList2
193 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
195 [system.cpu.fuPool.FUList2.opList0]
201 [system.cpu.fuPool.FUList2.opList1]
207 [system.cpu.fuPool.FUList2.opList2]
213 [system.cpu.fuPool.FUList3]
215 children=opList0 opList1 opList2
217 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
219 [system.cpu.fuPool.FUList3.opList0]
225 [system.cpu.fuPool.FUList3.opList1]
231 [system.cpu.fuPool.FUList3.opList2]
237 [system.cpu.fuPool.FUList4]
241 opList=system.cpu.fuPool.FUList4.opList
243 [system.cpu.fuPool.FUList4.opList]
249 [system.cpu.fuPool.FUList5]
251 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
253 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
255 [system.cpu.fuPool.FUList5.opList00]
261 [system.cpu.fuPool.FUList5.opList01]
267 [system.cpu.fuPool.FUList5.opList02]
273 [system.cpu.fuPool.FUList5.opList03]
279 [system.cpu.fuPool.FUList5.opList04]
285 [system.cpu.fuPool.FUList5.opList05]
291 [system.cpu.fuPool.FUList5.opList06]
297 [system.cpu.fuPool.FUList5.opList07]
303 [system.cpu.fuPool.FUList5.opList08]
309 [system.cpu.fuPool.FUList5.opList09]
315 [system.cpu.fuPool.FUList5.opList10]
321 [system.cpu.fuPool.FUList5.opList11]
327 [system.cpu.fuPool.FUList5.opList12]
333 [system.cpu.fuPool.FUList5.opList13]
339 [system.cpu.fuPool.FUList5.opList14]
345 [system.cpu.fuPool.FUList5.opList15]
351 [system.cpu.fuPool.FUList5.opList16]
354 opClass=SimdFloatMisc
357 [system.cpu.fuPool.FUList5.opList17]
360 opClass=SimdFloatMult
363 [system.cpu.fuPool.FUList5.opList18]
366 opClass=SimdFloatMultAcc
369 [system.cpu.fuPool.FUList5.opList19]
372 opClass=SimdFloatSqrt
375 [system.cpu.fuPool.FUList6]
379 opList=system.cpu.fuPool.FUList6.opList
381 [system.cpu.fuPool.FUList6.opList]
387 [system.cpu.fuPool.FUList7]
389 children=opList0 opList1
391 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
393 [system.cpu.fuPool.FUList7.opList0]
399 [system.cpu.fuPool.FUList7.opList1]
405 [system.cpu.fuPool.FUList8]
409 opList=system.cpu.fuPool.FUList8.opList
411 [system.cpu.fuPool.FUList8.opList]
419 addr_range=0:18446744073709551615
429 prefetch_data_accesses_only=false
431 prefetch_latency=10000
432 prefetch_on_access=false
433 prefetch_past_page=false
435 prefetch_serial_squash=false
436 prefetch_use_cpu_id=true
438 prioritizeRequests=false
446 cpu_side=system.cpu.icache_port
447 mem_side=system.cpu.toL2Bus.port[0]
455 addr_range=0:18446744073709551615
465 prefetch_data_accesses_only=false
467 prefetch_latency=10000
468 prefetch_on_access=false
469 prefetch_past_page=false
471 prefetch_serial_squash=false
472 prefetch_use_cpu_id=true
474 prioritizeRequests=false
482 cpu_side=system.cpu.toL2Bus.port[2]
483 mem_side=system.membus.port[2]
491 use_default_range=false
493 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
498 [system.cpu.workload]
501 cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing
506 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
509 max_stack_size=67108864
523 use_default_range=false
525 port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
535 port=system.membus.port[1]