arch: Fix VecReg container alignement to 128bits view
[gem5.git] / tests / long / se / 70.twolf / ref / x86 / linux / o3-timing / simout
1 Redirecting stdout to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simout
2 Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simerr
3 gem5 Simulator System. http://gem5.org
4 gem5 is copyrighted software; use the --copyright option for details.
5
6 gem5 compiled Mar 31 2017 16:17:52
7 gem5 started Mar 31 2017 16:18:04
8 gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 50433
9 command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/70.twolf/x86/linux/o3-timing
10
11 Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav
12 Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2
13 Global frequency set at 1000000000000 ticks per second
14
15 TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
16 Standard Cell Placement and Global Routing Program
17 Authors: Carl Sechen, Bill Swartz
18 Yale University
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27 122 123 124 Exiting @ tick 102720088500 because exiting with last active thread context