2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.082877 # Number of seconds simulated
4 sim_ticks 82877188500 # Number of ticks simulated
5 final_tick 82877188500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 45467 # Simulator instruction rate (inst/s)
8 host_op_rate 76207 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 28531656 # Simulator tick rate (ticks/s)
10 host_mem_usage 321540 # Number of bytes of host memory used
11 host_seconds 2904.75 # Real time elapsed on the host
12 sim_insts 132071192 # Number of instructions simulated
13 sim_ops 221362962 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 218496 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 124544 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 343040 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 218496 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 218496 # Number of instructions bytes read from this memory
19 system.physmem.num_reads::cpu.inst 3414 # Number of read requests responded to by this memory
20 system.physmem.num_reads::cpu.data 1946 # Number of read requests responded to by this memory
21 system.physmem.num_reads::total 5360 # Number of read requests responded to by this memory
22 system.physmem.bw_read::cpu.inst 2636383 # Total read bandwidth from this memory (bytes/s)
23 system.physmem.bw_read::cpu.data 1502754 # Total read bandwidth from this memory (bytes/s)
24 system.physmem.bw_read::total 4139137 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_inst_read::cpu.inst 2636383 # Instruction read bandwidth from this memory (bytes/s)
26 system.physmem.bw_inst_read::total 2636383 # Instruction read bandwidth from this memory (bytes/s)
27 system.physmem.bw_total::cpu.inst 2636383 # Total bandwidth to/from this memory (bytes/s)
28 system.physmem.bw_total::cpu.data 1502754 # Total bandwidth to/from this memory (bytes/s)
29 system.physmem.bw_total::total 4139137 # Total bandwidth to/from this memory (bytes/s)
30 system.physmem.readReqs 5362 # Total number of read requests seen
31 system.physmem.writeReqs 0 # Total number of write requests seen
32 system.physmem.cpureqs 5519 # Reqs generatd by CPU via cache - shady
33 system.physmem.bytesRead 343040 # Total number of bytes read from memory
34 system.physmem.bytesWritten 0 # Total number of bytes written to memory
35 system.physmem.bytesConsumedRd 343040 # bytesRead derated as per pkt->getSize()
36 system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
37 system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
38 system.physmem.neitherReadNorWrite 157 # Reqs where no action is needed
39 system.physmem.perBankRdReqs::0 274 # Track reads on a per bank basis
40 system.physmem.perBankRdReqs::1 293 # Track reads on a per bank basis
41 system.physmem.perBankRdReqs::2 321 # Track reads on a per bank basis
42 system.physmem.perBankRdReqs::3 273 # Track reads on a per bank basis
43 system.physmem.perBankRdReqs::4 309 # Track reads on a per bank basis
44 system.physmem.perBankRdReqs::5 368 # Track reads on a per bank basis
45 system.physmem.perBankRdReqs::6 378 # Track reads on a per bank basis
46 system.physmem.perBankRdReqs::7 381 # Track reads on a per bank basis
47 system.physmem.perBankRdReqs::8 371 # Track reads on a per bank basis
48 system.physmem.perBankRdReqs::9 374 # Track reads on a per bank basis
49 system.physmem.perBankRdReqs::10 367 # Track reads on a per bank basis
50 system.physmem.perBankRdReqs::11 353 # Track reads on a per bank basis
51 system.physmem.perBankRdReqs::12 358 # Track reads on a per bank basis
52 system.physmem.perBankRdReqs::13 339 # Track reads on a per bank basis
53 system.physmem.perBankRdReqs::14 355 # Track reads on a per bank basis
54 system.physmem.perBankRdReqs::15 248 # Track reads on a per bank basis
55 system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
56 system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
57 system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
58 system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
59 system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
60 system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
61 system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
62 system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
63 system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
64 system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
65 system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
66 system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
67 system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
68 system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
69 system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
70 system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
71 system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
72 system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
73 system.physmem.totGap 82877158000 # Total gap between requests
74 system.physmem.readPktSize::0 0 # Categorize read packet sizes
75 system.physmem.readPktSize::1 0 # Categorize read packet sizes
76 system.physmem.readPktSize::2 0 # Categorize read packet sizes
77 system.physmem.readPktSize::3 0 # Categorize read packet sizes
78 system.physmem.readPktSize::4 0 # Categorize read packet sizes
79 system.physmem.readPktSize::5 0 # Categorize read packet sizes
80 system.physmem.readPktSize::6 5362 # Categorize read packet sizes
81 system.physmem.writePktSize::0 0 # Categorize write packet sizes
82 system.physmem.writePktSize::1 0 # Categorize write packet sizes
83 system.physmem.writePktSize::2 0 # Categorize write packet sizes
84 system.physmem.writePktSize::3 0 # Categorize write packet sizes
85 system.physmem.writePktSize::4 0 # Categorize write packet sizes
86 system.physmem.writePktSize::5 0 # Categorize write packet sizes
87 system.physmem.writePktSize::6 0 # Categorize write packet sizes
88 system.physmem.rdQLenPdf::0 4169 # What read queue length does an incoming req see
89 system.physmem.rdQLenPdf::1 940 # What read queue length does an incoming req see
90 system.physmem.rdQLenPdf::2 206 # What read queue length does an incoming req see
91 system.physmem.rdQLenPdf::3 39 # What read queue length does an incoming req see
92 system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see
93 system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
94 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
95 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
96 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
97 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
98 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
99 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
100 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
120 system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
121 system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
122 system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
123 system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
124 system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
125 system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
126 system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
127 system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
128 system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
129 system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
130 system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
131 system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
132 system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
152 system.physmem.totQLat 16751250 # Total cycles spent in queuing delays
153 system.physmem.totMemAccLat 133128750 # Sum of mem lat for all requests
154 system.physmem.totBusLat 26810000 # Total cycles spent in databus access
155 system.physmem.totBankLat 89567500 # Total cycles spent in bank access
156 system.physmem.avgQLat 3124.07 # Average queueing delay per request
157 system.physmem.avgBankLat 16704.12 # Average bank access latency per request
158 system.physmem.avgBusLat 5000.00 # Average bus latency per request
159 system.physmem.avgMemAccLat 24828.19 # Average memory access latency
160 system.physmem.avgRdBW 4.14 # Average achieved read bandwidth in MB/s
161 system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
162 system.physmem.avgConsumedRdBW 4.14 # Average consumed read bandwidth in MB/s
163 system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
164 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
165 system.physmem.busUtil 0.03 # Data bus utilization in percentage
166 system.physmem.avgRdQLen 0.00 # Average read queue length over time
167 system.physmem.avgWrQLen 0.00 # Average write queue length over time
168 system.physmem.readRowHits 4540 # Number of row buffer hits during reads
169 system.physmem.writeRowHits 0 # Number of row buffer hits during writes
170 system.physmem.readRowHitRate 84.67 # Row buffer hit rate for reads
171 system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
172 system.physmem.avgGap 15456389.03 # Average gap between requests
173 system.cpu.branchPred.lookups 19990631 # Number of BP lookups
174 system.cpu.branchPred.condPredicted 19990631 # Number of conditional branches predicted
175 system.cpu.branchPred.condIncorrect 2016236 # Number of conditional branches incorrect
176 system.cpu.branchPred.BTBLookups 13900591 # Number of BTB lookups
177 system.cpu.branchPred.BTBHits 13121041 # Number of BTB hits
178 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
179 system.cpu.branchPred.BTBHitPct 94.391965 # BTB Hit Percentage
180 system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
181 system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
182 system.cpu.workload.num_syscalls 400 # Number of system calls
183 system.cpu.numCycles 165754378 # number of cpu cycles simulated
184 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
185 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
186 system.cpu.fetch.icacheStallCycles 25900956 # Number of cycles fetch is stalled on an Icache miss
187 system.cpu.fetch.Insts 219294156 # Number of instructions fetch has processed
188 system.cpu.fetch.Branches 19990631 # Number of branches that fetch encountered
189 system.cpu.fetch.predictedBranches 13121041 # Number of branches that fetch has predicted taken
190 system.cpu.fetch.Cycles 57660261 # Number of cycles fetch has run and was not squashing or blocked
191 system.cpu.fetch.SquashCycles 17705629 # Number of cycles fetch has spent squashing
192 system.cpu.fetch.BlockedCycles 66643848 # Number of cycles fetch has spent blocked
193 system.cpu.fetch.MiscStallCycles 251 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
194 system.cpu.fetch.PendingTrapStallCycles 1767 # Number of stall cycles due to pending traps
195 system.cpu.fetch.IcacheWaitRetryStallCycles 87 # Number of stall cycles due to full MSHR
196 system.cpu.fetch.CacheLines 24505830 # Number of cache lines fetched
197 system.cpu.fetch.IcacheSquashes 429319 # Number of outstanding Icache misses that were squashed
198 system.cpu.fetch.rateDist::samples 165627301 # Number of instructions fetched each cycle (Total)
199 system.cpu.fetch.rateDist::mean 2.187204 # Number of instructions fetched each cycle (Total)
200 system.cpu.fetch.rateDist::stdev 3.326012 # Number of instructions fetched each cycle (Total)
201 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
202 system.cpu.fetch.rateDist::0 109570790 66.16% 66.16% # Number of instructions fetched each cycle (Total)
203 system.cpu.fetch.rateDist::1 3065879 1.85% 68.01% # Number of instructions fetched each cycle (Total)
204 system.cpu.fetch.rateDist::2 2385245 1.44% 69.45% # Number of instructions fetched each cycle (Total)
205 system.cpu.fetch.rateDist::3 2897287 1.75% 71.20% # Number of instructions fetched each cycle (Total)
206 system.cpu.fetch.rateDist::4 3451303 2.08% 73.28% # Number of instructions fetched each cycle (Total)
207 system.cpu.fetch.rateDist::5 3579914 2.16% 75.44% # Number of instructions fetched each cycle (Total)
208 system.cpu.fetch.rateDist::6 4327523 2.61% 78.05% # Number of instructions fetched each cycle (Total)
209 system.cpu.fetch.rateDist::7 2732307 1.65% 79.70% # Number of instructions fetched each cycle (Total)
210 system.cpu.fetch.rateDist::8 33617053 20.30% 100.00% # Number of instructions fetched each cycle (Total)
211 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
212 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
213 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
214 system.cpu.fetch.rateDist::total 165627301 # Number of instructions fetched each cycle (Total)
215 system.cpu.fetch.branchRate 0.120604 # Number of branch fetches per cycle
216 system.cpu.fetch.rate 1.323007 # Number of inst fetches per cycle
217 system.cpu.decode.IdleCycles 38796677 # Number of cycles decode is idle
218 system.cpu.decode.BlockedCycles 56675107 # Number of cycles decode is blocked
219 system.cpu.decode.RunCycles 44775430 # Number of cycles decode is running
220 system.cpu.decode.UnblockCycles 9959956 # Number of cycles decode is unblocking
221 system.cpu.decode.SquashCycles 15420131 # Number of cycles decode is squashing
222 system.cpu.decode.DecodedInsts 354106901 # Number of instructions handled by decode
223 system.cpu.rename.SquashCycles 15420131 # Number of cycles rename is squashing
224 system.cpu.rename.IdleCycles 46276497 # Number of cycles rename is idle
225 system.cpu.rename.BlockCycles 14977058 # Number of cycles rename is blocking
226 system.cpu.rename.serializeStallCycles 23177 # count of cycles rename stalled for serializing inst
227 system.cpu.rename.RunCycles 46586117 # Number of cycles rename is running
228 system.cpu.rename.UnblockCycles 42344321 # Number of cycles rename is unblocking
229 system.cpu.rename.RenamedInsts 345709417 # Number of instructions processed by rename
230 system.cpu.rename.ROBFullEvents 99 # Number of times rename has blocked due to ROB full
231 system.cpu.rename.IQFullEvents 18016892 # Number of times rename has blocked due to IQ full
232 system.cpu.rename.LSQFullEvents 22216647 # Number of times rename has blocked due to LSQ full
233 system.cpu.rename.FullRegisterEvents 104 # Number of times there has been no free registers
234 system.cpu.rename.RenamedOperands 399350509 # Number of destination operands rename has renamed
235 system.cpu.rename.RenameLookups 961743278 # Number of register rename lookups that rename has made
236 system.cpu.rename.int_rename_lookups 951847615 # Number of integer rename lookups
237 system.cpu.rename.fp_rename_lookups 9895663 # Number of floating rename lookups
238 system.cpu.rename.CommittedMaps 259428606 # Number of HB maps that are committed
239 system.cpu.rename.UndoneMaps 139921903 # Number of HB maps that are undone due to squashing
240 system.cpu.rename.serializingInsts 1677 # count of serializing insts renamed
241 system.cpu.rename.tempSerializingInsts 1668 # count of temporary serializing insts renamed
242 system.cpu.rename.skidInsts 90545817 # count of insts added to the skid buffer
243 system.cpu.memDep0.insertedLoads 86819200 # Number of loads inserted to the mem dependence unit.
244 system.cpu.memDep0.insertedStores 31825632 # Number of stores inserted to the mem dependence unit.
245 system.cpu.memDep0.conflictingLoads 57864226 # Number of conflicting loads.
246 system.cpu.memDep0.conflictingStores 18806791 # Number of conflicting stores.
247 system.cpu.iq.iqInstsAdded 334068514 # Number of instructions added to the IQ (excludes non-spec)
248 system.cpu.iq.iqNonSpecInstsAdded 3610 # Number of non-speculative instructions added to the IQ
249 system.cpu.iq.iqInstsIssued 267647923 # Number of instructions issued
250 system.cpu.iq.iqSquashedInstsIssued 253259 # Number of squashed instructions issued
251 system.cpu.iq.iqSquashedInstsExamined 112254554 # Number of squashed instructions iterated over during squash; mainly for profiling
252 system.cpu.iq.iqSquashedOperandsExamined 230842120 # Number of squashed operands that are examined and possibly removed from graph
253 system.cpu.iq.iqSquashedNonSpecRemoved 2365 # Number of squashed non-spec instructions that were removed
254 system.cpu.iq.issued_per_cycle::samples 165627301 # Number of insts issued each cycle
255 system.cpu.iq.issued_per_cycle::mean 1.615965 # Number of insts issued each cycle
256 system.cpu.iq.issued_per_cycle::stdev 1.504012 # Number of insts issued each cycle
257 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
258 system.cpu.iq.issued_per_cycle::0 45188875 27.28% 27.28% # Number of insts issued each cycle
259 system.cpu.iq.issued_per_cycle::1 46699909 28.20% 55.48% # Number of insts issued each cycle
260 system.cpu.iq.issued_per_cycle::2 32907630 19.87% 75.35% # Number of insts issued each cycle
261 system.cpu.iq.issued_per_cycle::3 19828708 11.97% 87.32% # Number of insts issued each cycle
262 system.cpu.iq.issued_per_cycle::4 13197780 7.97% 95.29% # Number of insts issued each cycle
263 system.cpu.iq.issued_per_cycle::5 4795004 2.90% 98.18% # Number of insts issued each cycle
264 system.cpu.iq.issued_per_cycle::6 2328707 1.41% 99.59% # Number of insts issued each cycle
265 system.cpu.iq.issued_per_cycle::7 537256 0.32% 99.91% # Number of insts issued each cycle
266 system.cpu.iq.issued_per_cycle::8 143432 0.09% 100.00% # Number of insts issued each cycle
267 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
268 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
269 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
270 system.cpu.iq.issued_per_cycle::total 165627301 # Number of insts issued each cycle
271 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
272 system.cpu.iq.fu_full::IntAlu 131307 4.94% 4.94% # attempts to use FU when none available
273 system.cpu.iq.fu_full::IntMult 0 0.00% 4.94% # attempts to use FU when none available
274 system.cpu.iq.fu_full::IntDiv 0 0.00% 4.94% # attempts to use FU when none available
275 system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.94% # attempts to use FU when none available
276 system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.94% # attempts to use FU when none available
277 system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.94% # attempts to use FU when none available
278 system.cpu.iq.fu_full::FloatMult 0 0.00% 4.94% # attempts to use FU when none available
279 system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.94% # attempts to use FU when none available
280 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.94% # attempts to use FU when none available
281 system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.94% # attempts to use FU when none available
282 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.94% # attempts to use FU when none available
283 system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.94% # attempts to use FU when none available
284 system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.94% # attempts to use FU when none available
285 system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.94% # attempts to use FU when none available
286 system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.94% # attempts to use FU when none available
287 system.cpu.iq.fu_full::SimdMult 0 0.00% 4.94% # attempts to use FU when none available
288 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.94% # attempts to use FU when none available
289 system.cpu.iq.fu_full::SimdShift 0 0.00% 4.94% # attempts to use FU when none available
290 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.94% # attempts to use FU when none available
291 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.94% # attempts to use FU when none available
292 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.94% # attempts to use FU when none available
293 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.94% # attempts to use FU when none available
294 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.94% # attempts to use FU when none available
295 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.94% # attempts to use FU when none available
296 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.94% # attempts to use FU when none available
297 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.94% # attempts to use FU when none available
298 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.94% # attempts to use FU when none available
299 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.94% # attempts to use FU when none available
300 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.94% # attempts to use FU when none available
301 system.cpu.iq.fu_full::MemRead 2258473 85.02% 89.96% # attempts to use FU when none available
302 system.cpu.iq.fu_full::MemWrite 266681 10.04% 100.00% # attempts to use FU when none available
303 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
304 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
305 system.cpu.iq.FU_type_0::No_OpClass 1212174 0.45% 0.45% # Type of FU issued
306 system.cpu.iq.FU_type_0::IntAlu 174292551 65.12% 65.57% # Type of FU issued
307 system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.57% # Type of FU issued
308 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.57% # Type of FU issued
309 system.cpu.iq.FU_type_0::FloatAdd 1599486 0.60% 66.17% # Type of FU issued
310 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.17% # Type of FU issued
311 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.17% # Type of FU issued
312 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.17% # Type of FU issued
313 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.17% # Type of FU issued
314 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.17% # Type of FU issued
315 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.17% # Type of FU issued
316 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.17% # Type of FU issued
317 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.17% # Type of FU issued
318 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.17% # Type of FU issued
319 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.17% # Type of FU issued
320 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.17% # Type of FU issued
321 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.17% # Type of FU issued
322 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.17% # Type of FU issued
323 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.17% # Type of FU issued
324 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.17% # Type of FU issued
325 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.17% # Type of FU issued
326 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.17% # Type of FU issued
327 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.17% # Type of FU issued
328 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.17% # Type of FU issued
329 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.17% # Type of FU issued
330 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.17% # Type of FU issued
331 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.17% # Type of FU issued
332 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.17% # Type of FU issued
333 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.17% # Type of FU issued
334 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.17% # Type of FU issued
335 system.cpu.iq.FU_type_0::MemRead 67254766 25.13% 91.30% # Type of FU issued
336 system.cpu.iq.FU_type_0::MemWrite 23288946 8.70% 100.00% # Type of FU issued
337 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
338 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
339 system.cpu.iq.FU_type_0::total 267647923 # Type of FU issued
340 system.cpu.iq.rate 1.614726 # Inst issue rate
341 system.cpu.iq.fu_busy_cnt 2656461 # FU busy when requested
342 system.cpu.iq.fu_busy_rate 0.009925 # FU busy rate (busy events/executed inst)
343 system.cpu.iq.int_inst_queue_reads 698473214 # Number of integer instruction queue reads
344 system.cpu.iq.int_inst_queue_writes 441941062 # Number of integer instruction queue writes
345 system.cpu.iq.int_inst_queue_wakeup_accesses 260395422 # Number of integer instruction queue wakeup accesses
346 system.cpu.iq.fp_inst_queue_reads 5359653 # Number of floating instruction queue reads
347 system.cpu.iq.fp_inst_queue_writes 4679108 # Number of floating instruction queue writes
348 system.cpu.iq.fp_inst_queue_wakeup_accesses 2580004 # Number of floating instruction queue wakeup accesses
349 system.cpu.iq.int_alu_accesses 266396647 # Number of integer alu accesses
350 system.cpu.iq.fp_alu_accesses 2695563 # Number of floating point alu accesses
351 system.cpu.iew.lsq.thread0.forwLoads 19008282 # Number of loads that had data forwarded from stores
352 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
353 system.cpu.iew.lsq.thread0.squashedLoads 30169613 # Number of loads squashed
354 system.cpu.iew.lsq.thread0.ignoredResponses 29317 # Number of memory responses ignored because the instruction is squashed
355 system.cpu.iew.lsq.thread0.memOrderViolation 298845 # Number of memory ordering violations
356 system.cpu.iew.lsq.thread0.squashedStores 11309915 # Number of stores squashed
357 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
358 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
359 system.cpu.iew.lsq.thread0.rescheduledLoads 49334 # Number of loads that were rescheduled
360 system.cpu.iew.lsq.thread0.cacheBlocked 12 # Number of times an access to memory failed due to the cache being blocked
361 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
362 system.cpu.iew.iewSquashCycles 15420131 # Number of cycles IEW is squashing
363 system.cpu.iew.iewBlockCycles 575337 # Number of cycles IEW is blocking
364 system.cpu.iew.iewUnblockCycles 259825 # Number of cycles IEW is unblocking
365 system.cpu.iew.iewDispatchedInsts 334072124 # Number of instructions dispatched to IQ
366 system.cpu.iew.iewDispSquashedInsts 191879 # Number of squashed instructions skipped by dispatch
367 system.cpu.iew.iewDispLoadInsts 86819200 # Number of dispatched load instructions
368 system.cpu.iew.iewDispStoreInsts 31825632 # Number of dispatched store instructions
369 system.cpu.iew.iewDispNonSpecInsts 1661 # Number of dispatched non-speculative instructions
370 system.cpu.iew.iewIQFullEvents 148151 # Number of times the IQ has become full, causing a stall
371 system.cpu.iew.iewLSQFullEvents 27876 # Number of times the LSQ has become full, causing a stall
372 system.cpu.iew.memOrderViolationEvents 298845 # Number of memory order violations
373 system.cpu.iew.predictedTakenIncorrect 1178996 # Number of branches that were predicted taken incorrectly
374 system.cpu.iew.predictedNotTakenIncorrect 920787 # Number of branches that were predicted not taken incorrectly
375 system.cpu.iew.branchMispredicts 2099783 # Number of branch mispredicts detected at execute
376 system.cpu.iew.iewExecutedInsts 264757229 # Number of executed instructions
377 system.cpu.iew.iewExecLoadInsts 66265318 # Number of load instructions executed
378 system.cpu.iew.iewExecSquashedInsts 2890694 # Number of squashed instructions skipped in execute
379 system.cpu.iew.exec_swp 0 # number of swp insts executed
380 system.cpu.iew.exec_nop 0 # number of nop insts executed
381 system.cpu.iew.exec_refs 89162320 # number of memory reference insts executed
382 system.cpu.iew.exec_branches 14609733 # Number of branches executed
383 system.cpu.iew.exec_stores 22897002 # Number of stores executed
384 system.cpu.iew.exec_rate 1.597286 # Inst execution rate
385 system.cpu.iew.wb_sent 263814551 # cumulative count of insts sent to commit
386 system.cpu.iew.wb_count 262975426 # cumulative count of insts written-back
387 system.cpu.iew.wb_producers 212208096 # num instructions producing a value
388 system.cpu.iew.wb_consumers 375332869 # num instructions consuming a value
389 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
390 system.cpu.iew.wb_rate 1.586537 # insts written-back per cycle
391 system.cpu.iew.wb_fanout 0.565386 # average fanout of values written-back
392 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
393 system.cpu.commit.commitSquashedInsts 112746099 # The number of squashed insts skipped by commit
394 system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards
395 system.cpu.commit.branchMispredicts 2016423 # The number of times a branch was mispredicted
396 system.cpu.commit.committed_per_cycle::samples 150207170 # Number of insts commited each cycle
397 system.cpu.commit.committed_per_cycle::mean 1.473718 # Number of insts commited each cycle
398 system.cpu.commit.committed_per_cycle::stdev 1.941598 # Number of insts commited each cycle
399 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
400 system.cpu.commit.committed_per_cycle::0 50947202 33.92% 33.92% # Number of insts commited each cycle
401 system.cpu.commit.committed_per_cycle::1 57273647 38.13% 72.05% # Number of insts commited each cycle
402 system.cpu.commit.committed_per_cycle::2 13797241 9.19% 81.23% # Number of insts commited each cycle
403 system.cpu.commit.committed_per_cycle::3 12067854 8.03% 89.27% # Number of insts commited each cycle
404 system.cpu.commit.committed_per_cycle::4 4154161 2.77% 92.03% # Number of insts commited each cycle
405 system.cpu.commit.committed_per_cycle::5 2974218 1.98% 94.01% # Number of insts commited each cycle
406 system.cpu.commit.committed_per_cycle::6 1064553 0.71% 94.72% # Number of insts commited each cycle
407 system.cpu.commit.committed_per_cycle::7 1010133 0.67% 95.39% # Number of insts commited each cycle
408 system.cpu.commit.committed_per_cycle::8 6918161 4.61% 100.00% # Number of insts commited each cycle
409 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
410 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
411 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
412 system.cpu.commit.committed_per_cycle::total 150207170 # Number of insts commited each cycle
413 system.cpu.commit.committedInsts 132071192 # Number of instructions committed
414 system.cpu.commit.committedOps 221362962 # Number of ops (including micro ops) committed
415 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
416 system.cpu.commit.refs 77165304 # Number of memory references committed
417 system.cpu.commit.loads 56649587 # Number of loads committed
418 system.cpu.commit.membars 0 # Number of memory barriers committed
419 system.cpu.commit.branches 12326938 # Number of branches committed
420 system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions.
421 system.cpu.commit.int_insts 220339553 # Number of committed integer instructions.
422 system.cpu.commit.function_calls 0 # Number of function calls committed.
423 system.cpu.commit.bw_lim_events 6918161 # number cycles where commit BW limit reached
424 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
425 system.cpu.rob.rob_reads 477398070 # The number of ROB reads
426 system.cpu.rob.rob_writes 683673273 # The number of ROB writes
427 system.cpu.timesIdled 2993 # Number of times that the entire CPU went into an idle state and unscheduled itself
428 system.cpu.idleCycles 127077 # Total number of cycles that the CPU has spent unscheduled due to idling
429 system.cpu.committedInsts 132071192 # Number of Instructions Simulated
430 system.cpu.committedOps 221362962 # Number of Ops (including micro ops) Simulated
431 system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated
432 system.cpu.cpi 1.255038 # CPI: Cycles Per Instruction
433 system.cpu.cpi_total 1.255038 # CPI: Total CPI of All Threads
434 system.cpu.ipc 0.796789 # IPC: Instructions Per Cycle
435 system.cpu.ipc_total 0.796789 # IPC: Total IPC of All Threads
436 system.cpu.int_regfile_reads 562793335 # number of integer regfile reads
437 system.cpu.int_regfile_writes 298868750 # number of integer regfile writes
438 system.cpu.fp_regfile_reads 3530164 # number of floating regfile reads
439 system.cpu.fp_regfile_writes 2239527 # number of floating regfile writes
440 system.cpu.misc_regfile_reads 137140339 # number of misc regfile reads
441 system.cpu.misc_regfile_writes 845 # number of misc regfile writes
442 system.cpu.icache.replacements 4944 # number of replacements
443 system.cpu.icache.tagsinuse 1623.744998 # Cycle average of tags in use
444 system.cpu.icache.total_refs 24496606 # Total number of references to valid blocks.
445 system.cpu.icache.sampled_refs 6912 # Sample count of references to valid blocks.
446 system.cpu.icache.avg_refs 3544.069155 # Average number of references to valid blocks.
447 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
448 system.cpu.icache.occ_blocks::cpu.inst 1623.744998 # Average occupied blocks per requestor
449 system.cpu.icache.occ_percent::cpu.inst 0.792844 # Average percentage of cache occupancy
450 system.cpu.icache.occ_percent::total 0.792844 # Average percentage of cache occupancy
451 system.cpu.icache.ReadReq_hits::cpu.inst 24496606 # number of ReadReq hits
452 system.cpu.icache.ReadReq_hits::total 24496606 # number of ReadReq hits
453 system.cpu.icache.demand_hits::cpu.inst 24496606 # number of demand (read+write) hits
454 system.cpu.icache.demand_hits::total 24496606 # number of demand (read+write) hits
455 system.cpu.icache.overall_hits::cpu.inst 24496606 # number of overall hits
456 system.cpu.icache.overall_hits::total 24496606 # number of overall hits
457 system.cpu.icache.ReadReq_misses::cpu.inst 9224 # number of ReadReq misses
458 system.cpu.icache.ReadReq_misses::total 9224 # number of ReadReq misses
459 system.cpu.icache.demand_misses::cpu.inst 9224 # number of demand (read+write) misses
460 system.cpu.icache.demand_misses::total 9224 # number of demand (read+write) misses
461 system.cpu.icache.overall_misses::cpu.inst 9224 # number of overall misses
462 system.cpu.icache.overall_misses::total 9224 # number of overall misses
463 system.cpu.icache.ReadReq_miss_latency::cpu.inst 273910997 # number of ReadReq miss cycles
464 system.cpu.icache.ReadReq_miss_latency::total 273910997 # number of ReadReq miss cycles
465 system.cpu.icache.demand_miss_latency::cpu.inst 273910997 # number of demand (read+write) miss cycles
466 system.cpu.icache.demand_miss_latency::total 273910997 # number of demand (read+write) miss cycles
467 system.cpu.icache.overall_miss_latency::cpu.inst 273910997 # number of overall miss cycles
468 system.cpu.icache.overall_miss_latency::total 273910997 # number of overall miss cycles
469 system.cpu.icache.ReadReq_accesses::cpu.inst 24505830 # number of ReadReq accesses(hits+misses)
470 system.cpu.icache.ReadReq_accesses::total 24505830 # number of ReadReq accesses(hits+misses)
471 system.cpu.icache.demand_accesses::cpu.inst 24505830 # number of demand (read+write) accesses
472 system.cpu.icache.demand_accesses::total 24505830 # number of demand (read+write) accesses
473 system.cpu.icache.overall_accesses::cpu.inst 24505830 # number of overall (read+write) accesses
474 system.cpu.icache.overall_accesses::total 24505830 # number of overall (read+write) accesses
475 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000376 # miss rate for ReadReq accesses
476 system.cpu.icache.ReadReq_miss_rate::total 0.000376 # miss rate for ReadReq accesses
477 system.cpu.icache.demand_miss_rate::cpu.inst 0.000376 # miss rate for demand accesses
478 system.cpu.icache.demand_miss_rate::total 0.000376 # miss rate for demand accesses
479 system.cpu.icache.overall_miss_rate::cpu.inst 0.000376 # miss rate for overall accesses
480 system.cpu.icache.overall_miss_rate::total 0.000376 # miss rate for overall accesses
481 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29695.468018 # average ReadReq miss latency
482 system.cpu.icache.ReadReq_avg_miss_latency::total 29695.468018 # average ReadReq miss latency
483 system.cpu.icache.demand_avg_miss_latency::cpu.inst 29695.468018 # average overall miss latency
484 system.cpu.icache.demand_avg_miss_latency::total 29695.468018 # average overall miss latency
485 system.cpu.icache.overall_avg_miss_latency::cpu.inst 29695.468018 # average overall miss latency
486 system.cpu.icache.overall_avg_miss_latency::total 29695.468018 # average overall miss latency
487 system.cpu.icache.blocked_cycles::no_mshrs 837 # number of cycles access was blocked
488 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
489 system.cpu.icache.blocked::no_mshrs 27 # number of cycles access was blocked
490 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
491 system.cpu.icache.avg_blocked_cycles::no_mshrs 31 # average number of cycles each access was blocked
492 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
493 system.cpu.icache.fast_writes 0 # number of fast writes performed
494 system.cpu.icache.cache_copies 0 # number of cache copies performed
495 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2153 # number of ReadReq MSHR hits
496 system.cpu.icache.ReadReq_mshr_hits::total 2153 # number of ReadReq MSHR hits
497 system.cpu.icache.demand_mshr_hits::cpu.inst 2153 # number of demand (read+write) MSHR hits
498 system.cpu.icache.demand_mshr_hits::total 2153 # number of demand (read+write) MSHR hits
499 system.cpu.icache.overall_mshr_hits::cpu.inst 2153 # number of overall MSHR hits
500 system.cpu.icache.overall_mshr_hits::total 2153 # number of overall MSHR hits
501 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7071 # number of ReadReq MSHR misses
502 system.cpu.icache.ReadReq_mshr_misses::total 7071 # number of ReadReq MSHR misses
503 system.cpu.icache.demand_mshr_misses::cpu.inst 7071 # number of demand (read+write) MSHR misses
504 system.cpu.icache.demand_mshr_misses::total 7071 # number of demand (read+write) MSHR misses
505 system.cpu.icache.overall_mshr_misses::cpu.inst 7071 # number of overall MSHR misses
506 system.cpu.icache.overall_mshr_misses::total 7071 # number of overall MSHR misses
507 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 206824497 # number of ReadReq MSHR miss cycles
508 system.cpu.icache.ReadReq_mshr_miss_latency::total 206824497 # number of ReadReq MSHR miss cycles
509 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 206824497 # number of demand (read+write) MSHR miss cycles
510 system.cpu.icache.demand_mshr_miss_latency::total 206824497 # number of demand (read+write) MSHR miss cycles
511 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 206824497 # number of overall MSHR miss cycles
512 system.cpu.icache.overall_mshr_miss_latency::total 206824497 # number of overall MSHR miss cycles
513 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000289 # mshr miss rate for ReadReq accesses
514 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000289 # mshr miss rate for ReadReq accesses
515 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000289 # mshr miss rate for demand accesses
516 system.cpu.icache.demand_mshr_miss_rate::total 0.000289 # mshr miss rate for demand accesses
517 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000289 # mshr miss rate for overall accesses
518 system.cpu.icache.overall_mshr_miss_rate::total 0.000289 # mshr miss rate for overall accesses
519 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29249.681375 # average ReadReq mshr miss latency
520 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29249.681375 # average ReadReq mshr miss latency
521 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29249.681375 # average overall mshr miss latency
522 system.cpu.icache.demand_avg_mshr_miss_latency::total 29249.681375 # average overall mshr miss latency
523 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29249.681375 # average overall mshr miss latency
524 system.cpu.icache.overall_avg_mshr_miss_latency::total 29249.681375 # average overall mshr miss latency
525 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
526 system.cpu.l2cache.replacements 0 # number of replacements
527 system.cpu.l2cache.tagsinuse 2531.083330 # Cycle average of tags in use
528 system.cpu.l2cache.total_refs 3532 # Total number of references to valid blocks.
529 system.cpu.l2cache.sampled_refs 3809 # Sample count of references to valid blocks.
530 system.cpu.l2cache.avg_refs 0.927278 # Average number of references to valid blocks.
531 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
532 system.cpu.l2cache.occ_blocks::writebacks 1.684861 # Average occupied blocks per requestor
533 system.cpu.l2cache.occ_blocks::cpu.inst 2246.789003 # Average occupied blocks per requestor
534 system.cpu.l2cache.occ_blocks::cpu.data 282.609466 # Average occupied blocks per requestor
535 system.cpu.l2cache.occ_percent::writebacks 0.000051 # Average percentage of cache occupancy
536 system.cpu.l2cache.occ_percent::cpu.inst 0.068567 # Average percentage of cache occupancy
537 system.cpu.l2cache.occ_percent::cpu.data 0.008625 # Average percentage of cache occupancy
538 system.cpu.l2cache.occ_percent::total 0.077243 # Average percentage of cache occupancy
539 system.cpu.l2cache.ReadReq_hits::cpu.inst 3499 # number of ReadReq hits
540 system.cpu.l2cache.ReadReq_hits::cpu.data 29 # number of ReadReq hits
541 system.cpu.l2cache.ReadReq_hits::total 3528 # number of ReadReq hits
542 system.cpu.l2cache.Writeback_hits::writebacks 14 # number of Writeback hits
543 system.cpu.l2cache.Writeback_hits::total 14 # number of Writeback hits
544 system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits
545 system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits
546 system.cpu.l2cache.ReadExReq_hits::cpu.data 7 # number of ReadExReq hits
547 system.cpu.l2cache.ReadExReq_hits::total 7 # number of ReadExReq hits
548 system.cpu.l2cache.demand_hits::cpu.inst 3499 # number of demand (read+write) hits
549 system.cpu.l2cache.demand_hits::cpu.data 36 # number of demand (read+write) hits
550 system.cpu.l2cache.demand_hits::total 3535 # number of demand (read+write) hits
551 system.cpu.l2cache.overall_hits::cpu.inst 3499 # number of overall hits
552 system.cpu.l2cache.overall_hits::cpu.data 36 # number of overall hits
553 system.cpu.l2cache.overall_hits::total 3535 # number of overall hits
554 system.cpu.l2cache.ReadReq_misses::cpu.inst 3414 # number of ReadReq misses
555 system.cpu.l2cache.ReadReq_misses::cpu.data 392 # number of ReadReq misses
556 system.cpu.l2cache.ReadReq_misses::total 3806 # number of ReadReq misses
557 system.cpu.l2cache.UpgradeReq_misses::cpu.data 157 # number of UpgradeReq misses
558 system.cpu.l2cache.UpgradeReq_misses::total 157 # number of UpgradeReq misses
559 system.cpu.l2cache.ReadExReq_misses::cpu.data 1556 # number of ReadExReq misses
560 system.cpu.l2cache.ReadExReq_misses::total 1556 # number of ReadExReq misses
561 system.cpu.l2cache.demand_misses::cpu.inst 3414 # number of demand (read+write) misses
562 system.cpu.l2cache.demand_misses::cpu.data 1948 # number of demand (read+write) misses
563 system.cpu.l2cache.demand_misses::total 5362 # number of demand (read+write) misses
564 system.cpu.l2cache.overall_misses::cpu.inst 3414 # number of overall misses
565 system.cpu.l2cache.overall_misses::cpu.data 1948 # number of overall misses
566 system.cpu.l2cache.overall_misses::total 5362 # number of overall misses
567 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 164604500 # number of ReadReq miss cycles
568 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 23838500 # number of ReadReq miss cycles
569 system.cpu.l2cache.ReadReq_miss_latency::total 188443000 # number of ReadReq miss cycles
570 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 68684000 # number of ReadExReq miss cycles
571 system.cpu.l2cache.ReadExReq_miss_latency::total 68684000 # number of ReadExReq miss cycles
572 system.cpu.l2cache.demand_miss_latency::cpu.inst 164604500 # number of demand (read+write) miss cycles
573 system.cpu.l2cache.demand_miss_latency::cpu.data 92522500 # number of demand (read+write) miss cycles
574 system.cpu.l2cache.demand_miss_latency::total 257127000 # number of demand (read+write) miss cycles
575 system.cpu.l2cache.overall_miss_latency::cpu.inst 164604500 # number of overall miss cycles
576 system.cpu.l2cache.overall_miss_latency::cpu.data 92522500 # number of overall miss cycles
577 system.cpu.l2cache.overall_miss_latency::total 257127000 # number of overall miss cycles
578 system.cpu.l2cache.ReadReq_accesses::cpu.inst 6913 # number of ReadReq accesses(hits+misses)
579 system.cpu.l2cache.ReadReq_accesses::cpu.data 421 # number of ReadReq accesses(hits+misses)
580 system.cpu.l2cache.ReadReq_accesses::total 7334 # number of ReadReq accesses(hits+misses)
581 system.cpu.l2cache.Writeback_accesses::writebacks 14 # number of Writeback accesses(hits+misses)
582 system.cpu.l2cache.Writeback_accesses::total 14 # number of Writeback accesses(hits+misses)
583 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 158 # number of UpgradeReq accesses(hits+misses)
584 system.cpu.l2cache.UpgradeReq_accesses::total 158 # number of UpgradeReq accesses(hits+misses)
585 system.cpu.l2cache.ReadExReq_accesses::cpu.data 1563 # number of ReadExReq accesses(hits+misses)
586 system.cpu.l2cache.ReadExReq_accesses::total 1563 # number of ReadExReq accesses(hits+misses)
587 system.cpu.l2cache.demand_accesses::cpu.inst 6913 # number of demand (read+write) accesses
588 system.cpu.l2cache.demand_accesses::cpu.data 1984 # number of demand (read+write) accesses
589 system.cpu.l2cache.demand_accesses::total 8897 # number of demand (read+write) accesses
590 system.cpu.l2cache.overall_accesses::cpu.inst 6913 # number of overall (read+write) accesses
591 system.cpu.l2cache.overall_accesses::cpu.data 1984 # number of overall (read+write) accesses
592 system.cpu.l2cache.overall_accesses::total 8897 # number of overall (read+write) accesses
593 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.493852 # miss rate for ReadReq accesses
594 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.931116 # miss rate for ReadReq accesses
595 system.cpu.l2cache.ReadReq_miss_rate::total 0.518953 # miss rate for ReadReq accesses
596 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.993671 # miss rate for UpgradeReq accesses
597 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.993671 # miss rate for UpgradeReq accesses
598 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.995521 # miss rate for ReadExReq accesses
599 system.cpu.l2cache.ReadExReq_miss_rate::total 0.995521 # miss rate for ReadExReq accesses
600 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.493852 # miss rate for demand accesses
601 system.cpu.l2cache.demand_miss_rate::cpu.data 0.981855 # miss rate for demand accesses
602 system.cpu.l2cache.demand_miss_rate::total 0.602675 # miss rate for demand accesses
603 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.493852 # miss rate for overall accesses
604 system.cpu.l2cache.overall_miss_rate::cpu.data 0.981855 # miss rate for overall accesses
605 system.cpu.l2cache.overall_miss_rate::total 0.602675 # miss rate for overall accesses
606 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48214.557704 # average ReadReq miss latency
607 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 60812.500000 # average ReadReq miss latency
608 system.cpu.l2cache.ReadReq_avg_miss_latency::total 49512.086180 # average ReadReq miss latency
609 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 44141.388175 # average ReadExReq miss latency
610 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 44141.388175 # average ReadExReq miss latency
611 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48214.557704 # average overall miss latency
612 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47496.149897 # average overall miss latency
613 system.cpu.l2cache.demand_avg_miss_latency::total 47953.562104 # average overall miss latency
614 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48214.557704 # average overall miss latency
615 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47496.149897 # average overall miss latency
616 system.cpu.l2cache.overall_avg_miss_latency::total 47953.562104 # average overall miss latency
617 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
618 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
619 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
620 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
621 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
622 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
623 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
624 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
625 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3414 # number of ReadReq MSHR misses
626 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 392 # number of ReadReq MSHR misses
627 system.cpu.l2cache.ReadReq_mshr_misses::total 3806 # number of ReadReq MSHR misses
628 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 157 # number of UpgradeReq MSHR misses
629 system.cpu.l2cache.UpgradeReq_mshr_misses::total 157 # number of UpgradeReq MSHR misses
630 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1556 # number of ReadExReq MSHR misses
631 system.cpu.l2cache.ReadExReq_mshr_misses::total 1556 # number of ReadExReq MSHR misses
632 system.cpu.l2cache.demand_mshr_misses::cpu.inst 3414 # number of demand (read+write) MSHR misses
633 system.cpu.l2cache.demand_mshr_misses::cpu.data 1948 # number of demand (read+write) MSHR misses
634 system.cpu.l2cache.demand_mshr_misses::total 5362 # number of demand (read+write) MSHR misses
635 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3414 # number of overall MSHR misses
636 system.cpu.l2cache.overall_mshr_misses::cpu.data 1948 # number of overall MSHR misses
637 system.cpu.l2cache.overall_mshr_misses::total 5362 # number of overall MSHR misses
638 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 122263536 # number of ReadReq MSHR miss cycles
639 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19005810 # number of ReadReq MSHR miss cycles
640 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 141269346 # number of ReadReq MSHR miss cycles
641 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1570157 # number of UpgradeReq MSHR miss cycles
642 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1570157 # number of UpgradeReq MSHR miss cycles
643 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 49028503 # number of ReadExReq MSHR miss cycles
644 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 49028503 # number of ReadExReq MSHR miss cycles
645 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 122263536 # number of demand (read+write) MSHR miss cycles
646 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 68034313 # number of demand (read+write) MSHR miss cycles
647 system.cpu.l2cache.demand_mshr_miss_latency::total 190297849 # number of demand (read+write) MSHR miss cycles
648 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 122263536 # number of overall MSHR miss cycles
649 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 68034313 # number of overall MSHR miss cycles
650 system.cpu.l2cache.overall_mshr_miss_latency::total 190297849 # number of overall MSHR miss cycles
651 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.493852 # mshr miss rate for ReadReq accesses
652 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.931116 # mshr miss rate for ReadReq accesses
653 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.518953 # mshr miss rate for ReadReq accesses
654 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.993671 # mshr miss rate for UpgradeReq accesses
655 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.993671 # mshr miss rate for UpgradeReq accesses
656 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995521 # mshr miss rate for ReadExReq accesses
657 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995521 # mshr miss rate for ReadExReq accesses
658 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.493852 # mshr miss rate for demand accesses
659 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.981855 # mshr miss rate for demand accesses
660 system.cpu.l2cache.demand_mshr_miss_rate::total 0.602675 # mshr miss rate for demand accesses
661 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.493852 # mshr miss rate for overall accesses
662 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.981855 # mshr miss rate for overall accesses
663 system.cpu.l2cache.overall_mshr_miss_rate::total 0.602675 # mshr miss rate for overall accesses
664 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35812.400703 # average ReadReq mshr miss latency
665 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48484.209184 # average ReadReq mshr miss latency
666 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37117.537047 # average ReadReq mshr miss latency
667 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
668 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
669 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31509.320694 # average ReadExReq mshr miss latency
670 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31509.320694 # average ReadExReq mshr miss latency
671 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35812.400703 # average overall mshr miss latency
672 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34925.212012 # average overall mshr miss latency
673 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35490.087467 # average overall mshr miss latency
674 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35812.400703 # average overall mshr miss latency
675 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34925.212012 # average overall mshr miss latency
676 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35490.087467 # average overall mshr miss latency
677 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
678 system.cpu.dcache.replacements 55 # number of replacements
679 system.cpu.dcache.tagsinuse 1413.084187 # Cycle average of tags in use
680 system.cpu.dcache.total_refs 67612398 # Total number of references to valid blocks.
681 system.cpu.dcache.sampled_refs 1982 # Sample count of references to valid blocks.
682 system.cpu.dcache.avg_refs 34113.217962 # Average number of references to valid blocks.
683 system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
684 system.cpu.dcache.occ_blocks::cpu.data 1413.084187 # Average occupied blocks per requestor
685 system.cpu.dcache.occ_percent::cpu.data 0.344991 # Average percentage of cache occupancy
686 system.cpu.dcache.occ_percent::total 0.344991 # Average percentage of cache occupancy
687 system.cpu.dcache.ReadReq_hits::cpu.data 47098181 # number of ReadReq hits
688 system.cpu.dcache.ReadReq_hits::total 47098181 # number of ReadReq hits
689 system.cpu.dcache.WriteReq_hits::cpu.data 20514009 # number of WriteReq hits
690 system.cpu.dcache.WriteReq_hits::total 20514009 # number of WriteReq hits
691 system.cpu.dcache.demand_hits::cpu.data 67612190 # number of demand (read+write) hits
692 system.cpu.dcache.demand_hits::total 67612190 # number of demand (read+write) hits
693 system.cpu.dcache.overall_hits::cpu.data 67612190 # number of overall hits
694 system.cpu.dcache.overall_hits::total 67612190 # number of overall hits
695 system.cpu.dcache.ReadReq_misses::cpu.data 831 # number of ReadReq misses
696 system.cpu.dcache.ReadReq_misses::total 831 # number of ReadReq misses
697 system.cpu.dcache.WriteReq_misses::cpu.data 1722 # number of WriteReq misses
698 system.cpu.dcache.WriteReq_misses::total 1722 # number of WriteReq misses
699 system.cpu.dcache.demand_misses::cpu.data 2553 # number of demand (read+write) misses
700 system.cpu.dcache.demand_misses::total 2553 # number of demand (read+write) misses
701 system.cpu.dcache.overall_misses::cpu.data 2553 # number of overall misses
702 system.cpu.dcache.overall_misses::total 2553 # number of overall misses
703 system.cpu.dcache.ReadReq_miss_latency::cpu.data 41843000 # number of ReadReq miss cycles
704 system.cpu.dcache.ReadReq_miss_latency::total 41843000 # number of ReadReq miss cycles
705 system.cpu.dcache.WriteReq_miss_latency::cpu.data 77380000 # number of WriteReq miss cycles
706 system.cpu.dcache.WriteReq_miss_latency::total 77380000 # number of WriteReq miss cycles
707 system.cpu.dcache.demand_miss_latency::cpu.data 119223000 # number of demand (read+write) miss cycles
708 system.cpu.dcache.demand_miss_latency::total 119223000 # number of demand (read+write) miss cycles
709 system.cpu.dcache.overall_miss_latency::cpu.data 119223000 # number of overall miss cycles
710 system.cpu.dcache.overall_miss_latency::total 119223000 # number of overall miss cycles
711 system.cpu.dcache.ReadReq_accesses::cpu.data 47099012 # number of ReadReq accesses(hits+misses)
712 system.cpu.dcache.ReadReq_accesses::total 47099012 # number of ReadReq accesses(hits+misses)
713 system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
714 system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
715 system.cpu.dcache.demand_accesses::cpu.data 67614743 # number of demand (read+write) accesses
716 system.cpu.dcache.demand_accesses::total 67614743 # number of demand (read+write) accesses
717 system.cpu.dcache.overall_accesses::cpu.data 67614743 # number of overall (read+write) accesses
718 system.cpu.dcache.overall_accesses::total 67614743 # number of overall (read+write) accesses
719 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000018 # miss rate for ReadReq accesses
720 system.cpu.dcache.ReadReq_miss_rate::total 0.000018 # miss rate for ReadReq accesses
721 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000084 # miss rate for WriteReq accesses
722 system.cpu.dcache.WriteReq_miss_rate::total 0.000084 # miss rate for WriteReq accesses
723 system.cpu.dcache.demand_miss_rate::cpu.data 0.000038 # miss rate for demand accesses
724 system.cpu.dcache.demand_miss_rate::total 0.000038 # miss rate for demand accesses
725 system.cpu.dcache.overall_miss_rate::cpu.data 0.000038 # miss rate for overall accesses
726 system.cpu.dcache.overall_miss_rate::total 0.000038 # miss rate for overall accesses
727 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50352.587244 # average ReadReq miss latency
728 system.cpu.dcache.ReadReq_avg_miss_latency::total 50352.587244 # average ReadReq miss latency
729 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44936.120790 # average WriteReq miss latency
730 system.cpu.dcache.WriteReq_avg_miss_latency::total 44936.120790 # average WriteReq miss latency
731 system.cpu.dcache.demand_avg_miss_latency::cpu.data 46699.177438 # average overall miss latency
732 system.cpu.dcache.demand_avg_miss_latency::total 46699.177438 # average overall miss latency
733 system.cpu.dcache.overall_avg_miss_latency::cpu.data 46699.177438 # average overall miss latency
734 system.cpu.dcache.overall_avg_miss_latency::total 46699.177438 # average overall miss latency
735 system.cpu.dcache.blocked_cycles::no_mshrs 70 # number of cycles access was blocked
736 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
737 system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
738 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
739 system.cpu.dcache.avg_blocked_cycles::no_mshrs 23.333333 # average number of cycles each access was blocked
740 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
741 system.cpu.dcache.fast_writes 0 # number of fast writes performed
742 system.cpu.dcache.cache_copies 0 # number of cache copies performed
743 system.cpu.dcache.writebacks::writebacks 14 # number of writebacks
744 system.cpu.dcache.writebacks::total 14 # number of writebacks
745 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 410 # number of ReadReq MSHR hits
746 system.cpu.dcache.ReadReq_mshr_hits::total 410 # number of ReadReq MSHR hits
747 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1 # number of WriteReq MSHR hits
748 system.cpu.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits
749 system.cpu.dcache.demand_mshr_hits::cpu.data 411 # number of demand (read+write) MSHR hits
750 system.cpu.dcache.demand_mshr_hits::total 411 # number of demand (read+write) MSHR hits
751 system.cpu.dcache.overall_mshr_hits::cpu.data 411 # number of overall MSHR hits
752 system.cpu.dcache.overall_mshr_hits::total 411 # number of overall MSHR hits
753 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 421 # number of ReadReq MSHR misses
754 system.cpu.dcache.ReadReq_mshr_misses::total 421 # number of ReadReq MSHR misses
755 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1721 # number of WriteReq MSHR misses
756 system.cpu.dcache.WriteReq_mshr_misses::total 1721 # number of WriteReq MSHR misses
757 system.cpu.dcache.demand_mshr_misses::cpu.data 2142 # number of demand (read+write) MSHR misses
758 system.cpu.dcache.demand_mshr_misses::total 2142 # number of demand (read+write) MSHR misses
759 system.cpu.dcache.overall_mshr_misses::cpu.data 2142 # number of overall MSHR misses
760 system.cpu.dcache.overall_mshr_misses::total 2142 # number of overall MSHR misses
761 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24554500 # number of ReadReq MSHR miss cycles
762 system.cpu.dcache.ReadReq_mshr_miss_latency::total 24554500 # number of ReadReq MSHR miss cycles
763 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73902500 # number of WriteReq MSHR miss cycles
764 system.cpu.dcache.WriteReq_mshr_miss_latency::total 73902500 # number of WriteReq MSHR miss cycles
765 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 98457000 # number of demand (read+write) MSHR miss cycles
766 system.cpu.dcache.demand_mshr_miss_latency::total 98457000 # number of demand (read+write) MSHR miss cycles
767 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 98457000 # number of overall MSHR miss cycles
768 system.cpu.dcache.overall_mshr_miss_latency::total 98457000 # number of overall MSHR miss cycles
769 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses
770 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses
771 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for WriteReq accesses
772 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000084 # mshr miss rate for WriteReq accesses
773 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses
774 system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses
775 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses
776 system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses
777 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58324.228029 # average ReadReq mshr miss latency
778 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58324.228029 # average ReadReq mshr miss latency
779 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42941.603719 # average WriteReq mshr miss latency
780 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42941.603719 # average WriteReq mshr miss latency
781 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45964.985994 # average overall mshr miss latency
782 system.cpu.dcache.demand_avg_mshr_miss_latency::total 45964.985994 # average overall mshr miss latency
783 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45964.985994 # average overall mshr miss latency
784 system.cpu.dcache.overall_avg_mshr_miss_latency::total 45964.985994 # average overall mshr miss latency
785 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
787 ---------- End Simulation Statistics ----------
projects / gem5.git / blob