2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.079141 # Number of seconds simulated
4 sim_ticks 79140979500 # Number of ticks simulated
5 final_tick 79140979500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 48369 # Simulator instruction rate (inst/s)
8 host_op_rate 81071 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 28984226 # Simulator tick rate (ticks/s)
10 host_mem_usage 336892 # Number of bytes of host memory used
11 host_seconds 2730.48 # Real time elapsed on the host
12 sim_insts 132071192 # Number of instructions simulated
13 sim_ops 221363384 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 221376 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 125056 # Number of bytes read from this memory
18 system.physmem.bytes_read::total 346432 # Number of bytes read from this memory
19 system.physmem.bytes_inst_read::cpu.inst 221376 # Number of instructions bytes read from this memory
20 system.physmem.bytes_inst_read::total 221376 # Number of instructions bytes read from this memory
21 system.physmem.num_reads::cpu.inst 3459 # Number of read requests responded to by this memory
22 system.physmem.num_reads::cpu.data 1954 # Number of read requests responded to by this memory
23 system.physmem.num_reads::total 5413 # Number of read requests responded to by this memory
24 system.physmem.bw_read::cpu.inst 2797236 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_read::cpu.data 1580167 # Total read bandwidth from this memory (bytes/s)
26 system.physmem.bw_read::total 4377403 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_inst_read::cpu.inst 2797236 # Instruction read bandwidth from this memory (bytes/s)
28 system.physmem.bw_inst_read::total 2797236 # Instruction read bandwidth from this memory (bytes/s)
29 system.physmem.bw_total::cpu.inst 2797236 # Total bandwidth to/from this memory (bytes/s)
30 system.physmem.bw_total::cpu.data 1580167 # Total bandwidth to/from this memory (bytes/s)
31 system.physmem.bw_total::total 4377403 # Total bandwidth to/from this memory (bytes/s)
32 system.physmem.readReqs 5413 # Number of read requests accepted
33 system.physmem.writeReqs 0 # Number of write requests accepted
34 system.physmem.readBursts 5413 # Number of DRAM read bursts, including those serviced by the write queue
35 system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
36 system.physmem.bytesReadDRAM 346432 # Total number of bytes read from DRAM
37 system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
38 system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
39 system.physmem.bytesReadSys 346432 # Total read bytes from the system interface side
40 system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
41 system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
42 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
43 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
44 system.physmem.perBankRdBursts::0 298 # Per bank write bursts
45 system.physmem.perBankRdBursts::1 346 # Per bank write bursts
46 system.physmem.perBankRdBursts::2 461 # Per bank write bursts
47 system.physmem.perBankRdBursts::3 349 # Per bank write bursts
48 system.physmem.perBankRdBursts::4 340 # Per bank write bursts
49 system.physmem.perBankRdBursts::5 326 # Per bank write bursts
50 system.physmem.perBankRdBursts::6 402 # Per bank write bursts
51 system.physmem.perBankRdBursts::7 384 # Per bank write bursts
52 system.physmem.perBankRdBursts::8 341 # Per bank write bursts
53 system.physmem.perBankRdBursts::9 281 # Per bank write bursts
54 system.physmem.perBankRdBursts::10 239 # Per bank write bursts
55 system.physmem.perBankRdBursts::11 285 # Per bank write bursts
56 system.physmem.perBankRdBursts::12 220 # Per bank write bursts
57 system.physmem.perBankRdBursts::13 466 # Per bank write bursts
58 system.physmem.perBankRdBursts::14 389 # Per bank write bursts
59 system.physmem.perBankRdBursts::15 286 # Per bank write bursts
60 system.physmem.perBankWrBursts::0 0 # Per bank write bursts
61 system.physmem.perBankWrBursts::1 0 # Per bank write bursts
62 system.physmem.perBankWrBursts::2 0 # Per bank write bursts
63 system.physmem.perBankWrBursts::3 0 # Per bank write bursts
64 system.physmem.perBankWrBursts::4 0 # Per bank write bursts
65 system.physmem.perBankWrBursts::5 0 # Per bank write bursts
66 system.physmem.perBankWrBursts::6 0 # Per bank write bursts
67 system.physmem.perBankWrBursts::7 0 # Per bank write bursts
68 system.physmem.perBankWrBursts::8 0 # Per bank write bursts
69 system.physmem.perBankWrBursts::9 0 # Per bank write bursts
70 system.physmem.perBankWrBursts::10 0 # Per bank write bursts
71 system.physmem.perBankWrBursts::11 0 # Per bank write bursts
72 system.physmem.perBankWrBursts::12 0 # Per bank write bursts
73 system.physmem.perBankWrBursts::13 0 # Per bank write bursts
74 system.physmem.perBankWrBursts::14 0 # Per bank write bursts
75 system.physmem.perBankWrBursts::15 0 # Per bank write bursts
76 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
77 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
78 system.physmem.totGap 79140890500 # Total gap between requests
79 system.physmem.readPktSize::0 0 # Read request sizes (log2)
80 system.physmem.readPktSize::1 0 # Read request sizes (log2)
81 system.physmem.readPktSize::2 0 # Read request sizes (log2)
82 system.physmem.readPktSize::3 0 # Read request sizes (log2)
83 system.physmem.readPktSize::4 0 # Read request sizes (log2)
84 system.physmem.readPktSize::5 0 # Read request sizes (log2)
85 system.physmem.readPktSize::6 5413 # Read request sizes (log2)
86 system.physmem.writePktSize::0 0 # Write request sizes (log2)
87 system.physmem.writePktSize::1 0 # Write request sizes (log2)
88 system.physmem.writePktSize::2 0 # Write request sizes (log2)
89 system.physmem.writePktSize::3 0 # Write request sizes (log2)
90 system.physmem.writePktSize::4 0 # Write request sizes (log2)
91 system.physmem.writePktSize::5 0 # Write request sizes (log2)
92 system.physmem.writePktSize::6 0 # Write request sizes (log2)
93 system.physmem.rdQLenPdf::0 4301 # What read queue length does an incoming req see
94 system.physmem.rdQLenPdf::1 904 # What read queue length does an incoming req see
95 system.physmem.rdQLenPdf::2 176 # What read queue length does an incoming req see
96 system.physmem.rdQLenPdf::3 27 # What read queue length does an incoming req see
97 system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
98 system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
99 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
100 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
125 system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
126 system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
127 system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
128 system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
129 system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
130 system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
131 system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
132 system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
189 system.physmem.bytesPerActivate::samples 1107 # Bytes accessed per row activation
190 system.physmem.bytesPerActivate::mean 311.790425 # Bytes accessed per row activation
191 system.physmem.bytesPerActivate::gmean 180.924163 # Bytes accessed per row activation
192 system.physmem.bytesPerActivate::stdev 329.273428 # Bytes accessed per row activation
193 system.physmem.bytesPerActivate::0-127 441 39.84% 39.84% # Bytes accessed per row activation
194 system.physmem.bytesPerActivate::128-255 229 20.69% 60.52% # Bytes accessed per row activation
195 system.physmem.bytesPerActivate::256-383 106 9.58% 70.10% # Bytes accessed per row activation
196 system.physmem.bytesPerActivate::384-511 59 5.33% 75.43% # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::512-639 51 4.61% 80.04% # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::640-767 54 4.88% 84.91% # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::768-895 23 2.08% 86.99% # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::896-1023 18 1.63% 88.62% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::1024-1151 126 11.38% 100.00% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::total 1107 # Bytes accessed per row activation
203 system.physmem.totQLat 40702000 # Total ticks spent queuing
204 system.physmem.totMemAccLat 142195750 # Total ticks spent from burst creation until serviced by the DRAM
205 system.physmem.totBusLat 27065000 # Total ticks spent in databus transfers
206 system.physmem.avgQLat 7519.31 # Average queueing delay per DRAM burst
207 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
208 system.physmem.avgMemAccLat 26269.31 # Average memory access latency per DRAM burst
209 system.physmem.avgRdBW 4.38 # Average DRAM read bandwidth in MiByte/s
210 system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
211 system.physmem.avgRdBWSys 4.38 # Average system read bandwidth in MiByte/s
212 system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
213 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
214 system.physmem.busUtil 0.03 # Data bus utilization in percentage
215 system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
216 system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
217 system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing
218 system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
219 system.physmem.readRowHits 4302 # Number of row buffer hits during reads
220 system.physmem.writeRowHits 0 # Number of row buffer hits during writes
221 system.physmem.readRowHitRate 79.48 # Row buffer hit rate for reads
222 system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
223 system.physmem.avgGap 14620522.91 # Average gap between requests
224 system.physmem.pageHitRate 79.48 # Row buffer hit rate, read and write combined
225 system.physmem_0.actEnergy 4898880 # Energy for activate commands per rank (pJ)
226 system.physmem_0.preEnergy 2673000 # Energy for precharge commands per rank (pJ)
227 system.physmem_0.readEnergy 22659000 # Energy for read commands per rank (pJ)
228 system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
229 system.physmem_0.refreshEnergy 5169003840 # Energy for refresh commands per rank (pJ)
230 system.physmem_0.actBackEnergy 2477527515 # Energy for active background per rank (pJ)
231 system.physmem_0.preBackEnergy 45310553250 # Energy for precharge background per rank (pJ)
232 system.physmem_0.totalEnergy 52987315485 # Total energy per rank (pJ)
233 system.physmem_0.averagePower 669.541483 # Core power per rank (mW)
234 system.physmem_0.memoryStateTime::IDLE 75375284500 # Time in different power states
235 system.physmem_0.memoryStateTime::REF 2642640000 # Time in different power states
236 system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
237 system.physmem_0.memoryStateTime::ACT 1122707500 # Time in different power states
238 system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
239 system.physmem_1.actEnergy 3470040 # Energy for activate commands per rank (pJ)
240 system.physmem_1.preEnergy 1893375 # Energy for precharge commands per rank (pJ)
241 system.physmem_1.readEnergy 19406400 # Energy for read commands per rank (pJ)
242 system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
243 system.physmem_1.refreshEnergy 5169003840 # Energy for refresh commands per rank (pJ)
244 system.physmem_1.actBackEnergy 2315256210 # Energy for active background per rank (pJ)
245 system.physmem_1.preBackEnergy 45452899500 # Energy for precharge background per rank (pJ)
246 system.physmem_1.totalEnergy 52961929365 # Total energy per rank (pJ)
247 system.physmem_1.averagePower 669.220665 # Core power per rank (mW)
248 system.physmem_1.memoryStateTime::IDLE 75612477000 # Time in different power states
249 system.physmem_1.memoryStateTime::REF 2642640000 # Time in different power states
250 system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
251 system.physmem_1.memoryStateTime::ACT 884606250 # Time in different power states
252 system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
253 system.cpu.branchPred.lookups 20604097 # Number of BP lookups
254 system.cpu.branchPred.condPredicted 20604097 # Number of conditional branches predicted
255 system.cpu.branchPred.condIncorrect 1328804 # Number of conditional branches incorrect
256 system.cpu.branchPred.BTBLookups 12707128 # Number of BTB lookups
257 system.cpu.branchPred.BTBHits 12016947 # Number of BTB hits
258 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
259 system.cpu.branchPred.BTBHitPct 94.568552 # BTB Hit Percentage
260 system.cpu.branchPred.usedRAS 1442846 # Number of times the RAS was used to get a target.
261 system.cpu.branchPred.RASInCorrect 16873 # Number of incorrect RAS predictions.
262 system.cpu_clk_domain.clock 500 # Clock period in ticks
263 system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
264 system.cpu.workload.num_syscalls 400 # Number of system calls
265 system.cpu.numCycles 158281960 # number of cpu cycles simulated
266 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
267 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
268 system.cpu.fetch.icacheStallCycles 25261186 # Number of cycles fetch is stalled on an Icache miss
269 system.cpu.fetch.Insts 227540228 # Number of instructions fetch has processed
270 system.cpu.fetch.Branches 20604097 # Number of branches that fetch encountered
271 system.cpu.fetch.predictedBranches 13459793 # Number of branches that fetch has predicted taken
272 system.cpu.fetch.Cycles 131194120 # Number of cycles fetch has run and was not squashing or blocked
273 system.cpu.fetch.SquashCycles 3196201 # Number of cycles fetch has spent squashing
274 system.cpu.fetch.TlbCycles 20 # Number of cycles fetch has spent waiting for tlb
275 system.cpu.fetch.MiscStallCycles 1974 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
276 system.cpu.fetch.PendingTrapStallCycles 21216 # Number of stall cycles due to pending traps
277 system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions
278 system.cpu.fetch.IcacheWaitRetryStallCycles 47 # Number of stall cycles due to full MSHR
279 system.cpu.fetch.CacheLines 24267792 # Number of cache lines fetched
280 system.cpu.fetch.IcacheSquashes 266999 # Number of outstanding Icache misses that were squashed
281 system.cpu.fetch.rateDist::samples 158076676 # Number of instructions fetched each cycle (Total)
282 system.cpu.fetch.rateDist::mean 2.380152 # Number of instructions fetched each cycle (Total)
283 system.cpu.fetch.rateDist::stdev 3.324971 # Number of instructions fetched each cycle (Total)
284 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
285 system.cpu.fetch.rateDist::0 95737539 60.56% 60.56% # Number of instructions fetched each cycle (Total)
286 system.cpu.fetch.rateDist::1 4758449 3.01% 63.57% # Number of instructions fetched each cycle (Total)
287 system.cpu.fetch.rateDist::2 3804663 2.41% 65.98% # Number of instructions fetched each cycle (Total)
288 system.cpu.fetch.rateDist::3 4365114 2.76% 68.74% # Number of instructions fetched each cycle (Total)
289 system.cpu.fetch.rateDist::4 4234763 2.68% 71.42% # Number of instructions fetched each cycle (Total)
290 system.cpu.fetch.rateDist::5 4816061 3.05% 74.47% # Number of instructions fetched each cycle (Total)
291 system.cpu.fetch.rateDist::6 4706874 2.98% 77.45% # Number of instructions fetched each cycle (Total)
292 system.cpu.fetch.rateDist::7 3702906 2.34% 79.79% # Number of instructions fetched each cycle (Total)
293 system.cpu.fetch.rateDist::8 31950307 20.21% 100.00% # Number of instructions fetched each cycle (Total)
294 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
295 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
296 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
297 system.cpu.fetch.rateDist::total 158076676 # Number of instructions fetched each cycle (Total)
298 system.cpu.fetch.branchRate 0.130173 # Number of branch fetches per cycle
299 system.cpu.fetch.rate 1.437563 # Number of inst fetches per cycle
300 system.cpu.decode.IdleCycles 15410588 # Number of cycles decode is idle
301 system.cpu.decode.BlockedCycles 96165479 # Number of cycles decode is blocked
302 system.cpu.decode.RunCycles 23286259 # Number of cycles decode is running
303 system.cpu.decode.UnblockCycles 21616250 # Number of cycles decode is unblocking
304 system.cpu.decode.SquashCycles 1598100 # Number of cycles decode is squashing
305 system.cpu.decode.DecodedInsts 336629364 # Number of instructions handled by decode
306 system.cpu.rename.SquashCycles 1598100 # Number of cycles rename is squashing
307 system.cpu.rename.IdleCycles 23294905 # Number of cycles rename is idle
308 system.cpu.rename.BlockCycles 31785654 # Number of cycles rename is blocking
309 system.cpu.rename.serializeStallCycles 30420 # count of cycles rename stalled for serializing inst
310 system.cpu.rename.RunCycles 36005072 # Number of cycles rename is running
311 system.cpu.rename.UnblockCycles 65362525 # Number of cycles rename is unblocking
312 system.cpu.rename.RenamedInsts 328266719 # Number of instructions processed by rename
313 system.cpu.rename.ROBFullEvents 1575 # Number of times rename has blocked due to ROB full
314 system.cpu.rename.IQFullEvents 57713162 # Number of times rename has blocked due to IQ full
315 system.cpu.rename.LQFullEvents 7745606 # Number of times rename has blocked due to LQ full
316 system.cpu.rename.SQFullEvents 167786 # Number of times rename has blocked due to SQ full
317 system.cpu.rename.RenamedOperands 380441368 # Number of destination operands rename has renamed
318 system.cpu.rename.RenameLookups 910027762 # Number of register rename lookups that rename has made
319 system.cpu.rename.int_rename_lookups 600617825 # Number of integer rename lookups
320 system.cpu.rename.fp_rename_lookups 4182134 # Number of floating rename lookups
321 system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed
322 system.cpu.rename.UndoneMaps 121011918 # Number of HB maps that are undone due to squashing
323 system.cpu.rename.serializingInsts 1942 # count of serializing insts renamed
324 system.cpu.rename.tempSerializingInsts 1920 # count of temporary serializing insts renamed
325 system.cpu.rename.skidInsts 120996232 # count of insts added to the skid buffer
326 system.cpu.memDep0.insertedLoads 82787391 # Number of loads inserted to the mem dependence unit.
327 system.cpu.memDep0.insertedStores 29790688 # Number of stores inserted to the mem dependence unit.
328 system.cpu.memDep0.conflictingLoads 59618216 # Number of conflicting loads.
329 system.cpu.memDep0.conflictingStores 20385329 # Number of conflicting stores.
330 system.cpu.iq.iqInstsAdded 317847109 # Number of instructions added to the IQ (excludes non-spec)
331 system.cpu.iq.iqNonSpecInstsAdded 5129 # Number of non-speculative instructions added to the IQ
332 system.cpu.iq.iqInstsIssued 259397692 # Number of instructions issued
333 system.cpu.iq.iqSquashedInstsIssued 74444 # Number of squashed instructions issued
334 system.cpu.iq.iqSquashedInstsExamined 96488854 # Number of squashed instructions iterated over during squash; mainly for profiling
335 system.cpu.iq.iqSquashedOperandsExamined 197170724 # Number of squashed operands that are examined and possibly removed from graph
336 system.cpu.iq.iqSquashedNonSpecRemoved 3884 # Number of squashed non-spec instructions that were removed
337 system.cpu.iq.issued_per_cycle::samples 158076676 # Number of insts issued each cycle
338 system.cpu.iq.issued_per_cycle::mean 1.640961 # Number of insts issued each cycle
339 system.cpu.iq.issued_per_cycle::stdev 1.524821 # Number of insts issued each cycle
340 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
341 system.cpu.iq.issued_per_cycle::0 40037944 25.33% 25.33% # Number of insts issued each cycle
342 system.cpu.iq.issued_per_cycle::1 47502917 30.05% 55.38% # Number of insts issued each cycle
343 system.cpu.iq.issued_per_cycle::2 33077309 20.92% 76.30% # Number of insts issued each cycle
344 system.cpu.iq.issued_per_cycle::3 17993681 11.38% 87.69% # Number of insts issued each cycle
345 system.cpu.iq.issued_per_cycle::4 10964078 6.94% 94.62% # Number of insts issued each cycle
346 system.cpu.iq.issued_per_cycle::5 4766946 3.02% 97.64% # Number of insts issued each cycle
347 system.cpu.iq.issued_per_cycle::6 2459939 1.56% 99.19% # Number of insts issued each cycle
348 system.cpu.iq.issued_per_cycle::7 882458 0.56% 99.75% # Number of insts issued each cycle
349 system.cpu.iq.issued_per_cycle::8 391404 0.25% 100.00% # Number of insts issued each cycle
350 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
351 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
352 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
353 system.cpu.iq.issued_per_cycle::total 158076676 # Number of insts issued each cycle
354 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
355 system.cpu.iq.fu_full::IntAlu 232299 7.31% 7.31% # attempts to use FU when none available
356 system.cpu.iq.fu_full::IntMult 0 0.00% 7.31% # attempts to use FU when none available
357 system.cpu.iq.fu_full::IntDiv 0 0.00% 7.31% # attempts to use FU when none available
358 system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.31% # attempts to use FU when none available
359 system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.31% # attempts to use FU when none available
360 system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.31% # attempts to use FU when none available
361 system.cpu.iq.fu_full::FloatMult 0 0.00% 7.31% # attempts to use FU when none available
362 system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.31% # attempts to use FU when none available
363 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.31% # attempts to use FU when none available
364 system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.31% # attempts to use FU when none available
365 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.31% # attempts to use FU when none available
366 system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.31% # attempts to use FU when none available
367 system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.31% # attempts to use FU when none available
368 system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.31% # attempts to use FU when none available
369 system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.31% # attempts to use FU when none available
370 system.cpu.iq.fu_full::SimdMult 0 0.00% 7.31% # attempts to use FU when none available
371 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.31% # attempts to use FU when none available
372 system.cpu.iq.fu_full::SimdShift 0 0.00% 7.31% # attempts to use FU when none available
373 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.31% # attempts to use FU when none available
374 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.31% # attempts to use FU when none available
375 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.31% # attempts to use FU when none available
376 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.31% # attempts to use FU when none available
377 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.31% # attempts to use FU when none available
378 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.31% # attempts to use FU when none available
379 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.31% # attempts to use FU when none available
380 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.31% # attempts to use FU when none available
381 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.31% # attempts to use FU when none available
382 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.31% # attempts to use FU when none available
383 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.31% # attempts to use FU when none available
384 system.cpu.iq.fu_full::MemRead 2560752 80.62% 87.93% # attempts to use FU when none available
385 system.cpu.iq.fu_full::MemWrite 383461 12.07% 100.00% # attempts to use FU when none available
386 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
387 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
388 system.cpu.iq.FU_type_0::No_OpClass 1212757 0.47% 0.47% # Type of FU issued
389 system.cpu.iq.FU_type_0::IntAlu 161810982 62.38% 62.85% # Type of FU issued
390 system.cpu.iq.FU_type_0::IntMult 789695 0.30% 63.15% # Type of FU issued
391 system.cpu.iq.FU_type_0::IntDiv 7037932 2.71% 65.86% # Type of FU issued
392 system.cpu.iq.FU_type_0::FloatAdd 1186383 0.46% 66.32% # Type of FU issued
393 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.32% # Type of FU issued
394 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.32% # Type of FU issued
395 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.32% # Type of FU issued
396 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.32% # Type of FU issued
397 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.32% # Type of FU issued
398 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.32% # Type of FU issued
399 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.32% # Type of FU issued
400 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.32% # Type of FU issued
401 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.32% # Type of FU issued
402 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.32% # Type of FU issued
403 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.32% # Type of FU issued
404 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.32% # Type of FU issued
405 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.32% # Type of FU issued
406 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.32% # Type of FU issued
407 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.32% # Type of FU issued
408 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.32% # Type of FU issued
409 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.32% # Type of FU issued
410 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.32% # Type of FU issued
411 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.32% # Type of FU issued
412 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.32% # Type of FU issued
413 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.32% # Type of FU issued
414 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.32% # Type of FU issued
415 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.32% # Type of FU issued
416 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.32% # Type of FU issued
417 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.32% # Type of FU issued
418 system.cpu.iq.FU_type_0::MemRead 64896242 25.02% 91.34% # Type of FU issued
419 system.cpu.iq.FU_type_0::MemWrite 22463701 8.66% 100.00% # Type of FU issued
420 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
421 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
422 system.cpu.iq.FU_type_0::total 259397692 # Type of FU issued
423 system.cpu.iq.rate 1.638833 # Inst issue rate
424 system.cpu.iq.fu_busy_cnt 3176512 # FU busy when requested
425 system.cpu.iq.fu_busy_rate 0.012246 # FU busy rate (busy events/executed inst)
426 system.cpu.iq.int_inst_queue_reads 675268347 # Number of integer instruction queue reads
427 system.cpu.iq.int_inst_queue_writes 410944123 # Number of integer instruction queue writes
428 system.cpu.iq.int_inst_queue_wakeup_accesses 253662320 # Number of integer instruction queue wakeup accesses
429 system.cpu.iq.fp_inst_queue_reads 4854669 # Number of floating instruction queue reads
430 system.cpu.iq.fp_inst_queue_writes 3693735 # Number of floating instruction queue writes
431 system.cpu.iq.fp_inst_queue_wakeup_accesses 2339703 # Number of floating instruction queue wakeup accesses
432 system.cpu.iq.int_alu_accesses 258916836 # Number of integer alu accesses
433 system.cpu.iq.fp_alu_accesses 2444611 # Number of floating point alu accesses
434 system.cpu.iew.lsq.thread0.forwLoads 18724074 # Number of loads that had data forwarded from stores
435 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
436 system.cpu.iew.lsq.thread0.squashedLoads 26137804 # Number of loads squashed
437 system.cpu.iew.lsq.thread0.ignoredResponses 13130 # Number of memory responses ignored because the instruction is squashed
438 system.cpu.iew.lsq.thread0.memOrderViolation 303242 # Number of memory ordering violations
439 system.cpu.iew.lsq.thread0.squashedStores 9274971 # Number of stores squashed
440 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
441 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
442 system.cpu.iew.lsq.thread0.rescheduledLoads 49888 # Number of loads that were rescheduled
443 system.cpu.iew.lsq.thread0.cacheBlocked 39 # Number of times an access to memory failed due to the cache being blocked
444 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
445 system.cpu.iew.iewSquashCycles 1598100 # Number of cycles IEW is squashing
446 system.cpu.iew.iewBlockCycles 12496396 # Number of cycles IEW is blocking
447 system.cpu.iew.iewUnblockCycles 489060 # Number of cycles IEW is unblocking
448 system.cpu.iew.iewDispatchedInsts 317852238 # Number of instructions dispatched to IQ
449 system.cpu.iew.iewDispSquashedInsts 92568 # Number of squashed instructions skipped by dispatch
450 system.cpu.iew.iewDispLoadInsts 82787391 # Number of dispatched load instructions
451 system.cpu.iew.iewDispStoreInsts 29790688 # Number of dispatched store instructions
452 system.cpu.iew.iewDispNonSpecInsts 2962 # Number of dispatched non-speculative instructions
453 system.cpu.iew.iewIQFullEvents 383739 # Number of times the IQ has become full, causing a stall
454 system.cpu.iew.iewLSQFullEvents 63074 # Number of times the LSQ has become full, causing a stall
455 system.cpu.iew.memOrderViolationEvents 303242 # Number of memory order violations
456 system.cpu.iew.predictedTakenIncorrect 551670 # Number of branches that were predicted taken incorrectly
457 system.cpu.iew.predictedNotTakenIncorrect 826736 # Number of branches that were predicted not taken incorrectly
458 system.cpu.iew.branchMispredicts 1378406 # Number of branch mispredicts detected at execute
459 system.cpu.iew.iewExecutedInsts 257339863 # Number of executed instructions
460 system.cpu.iew.iewExecLoadInsts 64084690 # Number of load instructions executed
461 system.cpu.iew.iewExecSquashedInsts 2057829 # Number of squashed instructions skipped in execute
462 system.cpu.iew.exec_swp 0 # number of swp insts executed
463 system.cpu.iew.exec_nop 0 # number of nop insts executed
464 system.cpu.iew.exec_refs 86369702 # number of memory reference insts executed
465 system.cpu.iew.exec_branches 14330688 # Number of branches executed
466 system.cpu.iew.exec_stores 22285012 # Number of stores executed
467 system.cpu.iew.exec_rate 1.625832 # Inst execution rate
468 system.cpu.iew.wb_sent 256690837 # cumulative count of insts sent to commit
469 system.cpu.iew.wb_count 256002023 # cumulative count of insts written-back
470 system.cpu.iew.wb_producers 204396158 # num instructions producing a value
471 system.cpu.iew.wb_consumers 369708068 # num instructions consuming a value
472 system.cpu.iew.wb_rate 1.617380 # insts written-back per cycle
473 system.cpu.iew.wb_fanout 0.552858 # average fanout of values written-back
474 system.cpu.commit.commitSquashedInsts 96496531 # The number of squashed insts skipped by commit
475 system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards
476 system.cpu.commit.branchMispredicts 1330625 # The number of times a branch was mispredicted
477 system.cpu.commit.committed_per_cycle::samples 144920748 # Number of insts commited each cycle
478 system.cpu.commit.committed_per_cycle::mean 1.527479 # Number of insts commited each cycle
479 system.cpu.commit.committed_per_cycle::stdev 1.956907 # Number of insts commited each cycle
480 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
481 system.cpu.commit.committed_per_cycle::0 45508636 31.40% 31.40% # Number of insts commited each cycle
482 system.cpu.commit.committed_per_cycle::1 57312376 39.55% 70.95% # Number of insts commited each cycle
483 system.cpu.commit.committed_per_cycle::2 14158342 9.77% 80.72% # Number of insts commited each cycle
484 system.cpu.commit.committed_per_cycle::3 11991162 8.27% 88.99% # Number of insts commited each cycle
485 system.cpu.commit.committed_per_cycle::4 4086517 2.82% 91.81% # Number of insts commited each cycle
486 system.cpu.commit.committed_per_cycle::5 2858053 1.97% 93.79% # Number of insts commited each cycle
487 system.cpu.commit.committed_per_cycle::6 923800 0.64% 94.42% # Number of insts commited each cycle
488 system.cpu.commit.committed_per_cycle::7 1073191 0.74% 95.16% # Number of insts commited each cycle
489 system.cpu.commit.committed_per_cycle::8 7008671 4.84% 100.00% # Number of insts commited each cycle
490 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
491 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
492 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
493 system.cpu.commit.committed_per_cycle::total 144920748 # Number of insts commited each cycle
494 system.cpu.commit.committedInsts 132071192 # Number of instructions committed
495 system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed
496 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
497 system.cpu.commit.refs 77165304 # Number of memory references committed
498 system.cpu.commit.loads 56649587 # Number of loads committed
499 system.cpu.commit.membars 0 # Number of memory barriers committed
500 system.cpu.commit.branches 12326938 # Number of branches committed
501 system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions.
502 system.cpu.commit.int_insts 219019985 # Number of committed integer instructions.
503 system.cpu.commit.function_calls 797818 # Number of function calls committed.
504 system.cpu.commit.op_class_0::No_OpClass 1176721 0.53% 0.53% # Class of committed instruction
505 system.cpu.commit.op_class_0::IntAlu 134111832 60.58% 61.12% # Class of committed instruction
506 system.cpu.commit.op_class_0::IntMult 772953 0.35% 61.47% # Class of committed instruction
507 system.cpu.commit.op_class_0::IntDiv 7031501 3.18% 64.64% # Class of committed instruction
508 system.cpu.commit.op_class_0::FloatAdd 1105073 0.50% 65.14% # Class of committed instruction
509 system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.14% # Class of committed instruction
510 system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.14% # Class of committed instruction
511 system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.14% # Class of committed instruction
512 system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.14% # Class of committed instruction
513 system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.14% # Class of committed instruction
514 system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.14% # Class of committed instruction
515 system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.14% # Class of committed instruction
516 system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.14% # Class of committed instruction
517 system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.14% # Class of committed instruction
518 system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.14% # Class of committed instruction
519 system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.14% # Class of committed instruction
520 system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.14% # Class of committed instruction
521 system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.14% # Class of committed instruction
522 system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.14% # Class of committed instruction
523 system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.14% # Class of committed instruction
524 system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.14% # Class of committed instruction
525 system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.14% # Class of committed instruction
526 system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.14% # Class of committed instruction
527 system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.14% # Class of committed instruction
528 system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.14% # Class of committed instruction
529 system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.14% # Class of committed instruction
530 system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.14% # Class of committed instruction
531 system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.14% # Class of committed instruction
532 system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.14% # Class of committed instruction
533 system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.14% # Class of committed instruction
534 system.cpu.commit.op_class_0::MemRead 56649587 25.59% 90.73% # Class of committed instruction
535 system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Class of committed instruction
536 system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
537 system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
538 system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction
539 system.cpu.commit.bw_lim_events 7008671 # number cycles where commit BW limit reached
540 system.cpu.rob.rob_reads 455771992 # The number of ROB reads
541 system.cpu.rob.rob_writes 648913303 # The number of ROB writes
542 system.cpu.timesIdled 2665 # Number of times that the entire CPU went into an idle state and unscheduled itself
543 system.cpu.idleCycles 205284 # Total number of cycles that the CPU has spent unscheduled due to idling
544 system.cpu.committedInsts 132071192 # Number of Instructions Simulated
545 system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated
546 system.cpu.cpi 1.198459 # CPI: Cycles Per Instruction
547 system.cpu.cpi_total 1.198459 # CPI: Total CPI of All Threads
548 system.cpu.ipc 0.834405 # IPC: Instructions Per Cycle
549 system.cpu.ipc_total 0.834405 # IPC: Total IPC of All Threads
550 system.cpu.int_regfile_reads 448575238 # number of integer regfile reads
551 system.cpu.int_regfile_writes 232602901 # number of integer regfile writes
552 system.cpu.fp_regfile_reads 3212636 # number of floating regfile reads
553 system.cpu.fp_regfile_writes 1997796 # number of floating regfile writes
554 system.cpu.cc_regfile_reads 102540240 # number of cc regfile reads
555 system.cpu.cc_regfile_writes 59516414 # number of cc regfile writes
556 system.cpu.misc_regfile_reads 132474845 # number of misc regfile reads
557 system.cpu.misc_regfile_writes 1689 # number of misc regfile writes
558 system.cpu.dcache.tags.replacements 51 # number of replacements
559 system.cpu.dcache.tags.tagsinuse 1429.115986 # Cycle average of tags in use
560 system.cpu.dcache.tags.total_refs 65747317 # Total number of references to valid blocks.
561 system.cpu.dcache.tags.sampled_refs 1995 # Sample count of references to valid blocks.
562 system.cpu.dcache.tags.avg_refs 32956.048622 # Average number of references to valid blocks.
563 system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
564 system.cpu.dcache.tags.occ_blocks::cpu.data 1429.115986 # Average occupied blocks per requestor
565 system.cpu.dcache.tags.occ_percent::cpu.data 0.348905 # Average percentage of cache occupancy
566 system.cpu.dcache.tags.occ_percent::total 0.348905 # Average percentage of cache occupancy
567 system.cpu.dcache.tags.occ_task_id_blocks::1024 1944 # Occupied blocks per task id
568 system.cpu.dcache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id
569 system.cpu.dcache.tags.age_task_id_blocks_1024::1 34 # Occupied blocks per task id
570 system.cpu.dcache.tags.age_task_id_blocks_1024::2 498 # Occupied blocks per task id
571 system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
572 system.cpu.dcache.tags.age_task_id_blocks_1024::4 1394 # Occupied blocks per task id
573 system.cpu.dcache.tags.occ_task_id_percent::1024 0.474609 # Percentage of cache occupancy per task id
574 system.cpu.dcache.tags.tag_accesses 131501473 # Number of tag accesses
575 system.cpu.dcache.tags.data_accesses 131501473 # Number of data accesses
576 system.cpu.dcache.ReadReq_hits::cpu.data 45233028 # number of ReadReq hits
577 system.cpu.dcache.ReadReq_hits::total 45233028 # number of ReadReq hits
578 system.cpu.dcache.WriteReq_hits::cpu.data 20513911 # number of WriteReq hits
579 system.cpu.dcache.WriteReq_hits::total 20513911 # number of WriteReq hits
580 system.cpu.dcache.demand_hits::cpu.data 65746939 # number of demand (read+write) hits
581 system.cpu.dcache.demand_hits::total 65746939 # number of demand (read+write) hits
582 system.cpu.dcache.overall_hits::cpu.data 65746939 # number of overall hits
583 system.cpu.dcache.overall_hits::total 65746939 # number of overall hits
584 system.cpu.dcache.ReadReq_misses::cpu.data 980 # number of ReadReq misses
585 system.cpu.dcache.ReadReq_misses::total 980 # number of ReadReq misses
586 system.cpu.dcache.WriteReq_misses::cpu.data 1820 # number of WriteReq misses
587 system.cpu.dcache.WriteReq_misses::total 1820 # number of WriteReq misses
588 system.cpu.dcache.demand_misses::cpu.data 2800 # number of demand (read+write) misses
589 system.cpu.dcache.demand_misses::total 2800 # number of demand (read+write) misses
590 system.cpu.dcache.overall_misses::cpu.data 2800 # number of overall misses
591 system.cpu.dcache.overall_misses::total 2800 # number of overall misses
592 system.cpu.dcache.ReadReq_miss_latency::cpu.data 65148000 # number of ReadReq miss cycles
593 system.cpu.dcache.ReadReq_miss_latency::total 65148000 # number of ReadReq miss cycles
594 system.cpu.dcache.WriteReq_miss_latency::cpu.data 128547000 # number of WriteReq miss cycles
595 system.cpu.dcache.WriteReq_miss_latency::total 128547000 # number of WriteReq miss cycles
596 system.cpu.dcache.demand_miss_latency::cpu.data 193695000 # number of demand (read+write) miss cycles
597 system.cpu.dcache.demand_miss_latency::total 193695000 # number of demand (read+write) miss cycles
598 system.cpu.dcache.overall_miss_latency::cpu.data 193695000 # number of overall miss cycles
599 system.cpu.dcache.overall_miss_latency::total 193695000 # number of overall miss cycles
600 system.cpu.dcache.ReadReq_accesses::cpu.data 45234008 # number of ReadReq accesses(hits+misses)
601 system.cpu.dcache.ReadReq_accesses::total 45234008 # number of ReadReq accesses(hits+misses)
602 system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
603 system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
604 system.cpu.dcache.demand_accesses::cpu.data 65749739 # number of demand (read+write) accesses
605 system.cpu.dcache.demand_accesses::total 65749739 # number of demand (read+write) accesses
606 system.cpu.dcache.overall_accesses::cpu.data 65749739 # number of overall (read+write) accesses
607 system.cpu.dcache.overall_accesses::total 65749739 # number of overall (read+write) accesses
608 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000022 # miss rate for ReadReq accesses
609 system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses
610 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses
611 system.cpu.dcache.WriteReq_miss_rate::total 0.000089 # miss rate for WriteReq accesses
612 system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses
613 system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses
614 system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses
615 system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses
616 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66477.551020 # average ReadReq miss latency
617 system.cpu.dcache.ReadReq_avg_miss_latency::total 66477.551020 # average ReadReq miss latency
618 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70630.219780 # average WriteReq miss latency
619 system.cpu.dcache.WriteReq_avg_miss_latency::total 70630.219780 # average WriteReq miss latency
620 system.cpu.dcache.demand_avg_miss_latency::cpu.data 69176.785714 # average overall miss latency
621 system.cpu.dcache.demand_avg_miss_latency::total 69176.785714 # average overall miss latency
622 system.cpu.dcache.overall_avg_miss_latency::cpu.data 69176.785714 # average overall miss latency
623 system.cpu.dcache.overall_avg_miss_latency::total 69176.785714 # average overall miss latency
624 system.cpu.dcache.blocked_cycles::no_mshrs 656 # number of cycles access was blocked
625 system.cpu.dcache.blocked_cycles::no_targets 70 # number of cycles access was blocked
626 system.cpu.dcache.blocked::no_mshrs 7 # number of cycles access was blocked
627 system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
628 system.cpu.dcache.avg_blocked_cycles::no_mshrs 93.714286 # average number of cycles each access was blocked
629 system.cpu.dcache.avg_blocked_cycles::no_targets 70 # average number of cycles each access was blocked
630 system.cpu.dcache.fast_writes 0 # number of fast writes performed
631 system.cpu.dcache.cache_copies 0 # number of cache copies performed
632 system.cpu.dcache.writebacks::writebacks 10 # number of writebacks
633 system.cpu.dcache.writebacks::total 10 # number of writebacks
634 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 526 # number of ReadReq MSHR hits
635 system.cpu.dcache.ReadReq_mshr_hits::total 526 # number of ReadReq MSHR hits
636 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits
637 system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits
638 system.cpu.dcache.demand_mshr_hits::cpu.data 528 # number of demand (read+write) MSHR hits
639 system.cpu.dcache.demand_mshr_hits::total 528 # number of demand (read+write) MSHR hits
640 system.cpu.dcache.overall_mshr_hits::cpu.data 528 # number of overall MSHR hits
641 system.cpu.dcache.overall_mshr_hits::total 528 # number of overall MSHR hits
642 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 454 # number of ReadReq MSHR misses
643 system.cpu.dcache.ReadReq_mshr_misses::total 454 # number of ReadReq MSHR misses
644 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1818 # number of WriteReq MSHR misses
645 system.cpu.dcache.WriteReq_mshr_misses::total 1818 # number of WriteReq MSHR misses
646 system.cpu.dcache.demand_mshr_misses::cpu.data 2272 # number of demand (read+write) MSHR misses
647 system.cpu.dcache.demand_mshr_misses::total 2272 # number of demand (read+write) MSHR misses
648 system.cpu.dcache.overall_mshr_misses::cpu.data 2272 # number of overall MSHR misses
649 system.cpu.dcache.overall_mshr_misses::total 2272 # number of overall MSHR misses
650 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36063000 # number of ReadReq MSHR miss cycles
651 system.cpu.dcache.ReadReq_mshr_miss_latency::total 36063000 # number of ReadReq MSHR miss cycles
652 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 126583000 # number of WriteReq MSHR miss cycles
653 system.cpu.dcache.WriteReq_mshr_miss_latency::total 126583000 # number of WriteReq MSHR miss cycles
654 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 162646000 # number of demand (read+write) MSHR miss cycles
655 system.cpu.dcache.demand_mshr_miss_latency::total 162646000 # number of demand (read+write) MSHR miss cycles
656 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 162646000 # number of overall MSHR miss cycles
657 system.cpu.dcache.overall_mshr_miss_latency::total 162646000 # number of overall MSHR miss cycles
658 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
659 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
660 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses
661 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses
662 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for demand accesses
663 system.cpu.dcache.demand_mshr_miss_rate::total 0.000035 # mshr miss rate for demand accesses
664 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for overall accesses
665 system.cpu.dcache.overall_mshr_miss_rate::total 0.000035 # mshr miss rate for overall accesses
666 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79433.920705 # average ReadReq mshr miss latency
667 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79433.920705 # average ReadReq mshr miss latency
668 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69627.612761 # average WriteReq mshr miss latency
669 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69627.612761 # average WriteReq mshr miss latency
670 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71587.147887 # average overall mshr miss latency
671 system.cpu.dcache.demand_avg_mshr_miss_latency::total 71587.147887 # average overall mshr miss latency
672 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71587.147887 # average overall mshr miss latency
673 system.cpu.dcache.overall_avg_mshr_miss_latency::total 71587.147887 # average overall mshr miss latency
674 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
675 system.cpu.icache.tags.replacements 5017 # number of replacements
676 system.cpu.icache.tags.tagsinuse 1636.801929 # Cycle average of tags in use
677 system.cpu.icache.tags.total_refs 24258361 # Total number of references to valid blocks.
678 system.cpu.icache.tags.sampled_refs 6993 # Sample count of references to valid blocks.
679 system.cpu.icache.tags.avg_refs 3468.949092 # Average number of references to valid blocks.
680 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
681 system.cpu.icache.tags.occ_blocks::cpu.inst 1636.801929 # Average occupied blocks per requestor
682 system.cpu.icache.tags.occ_percent::cpu.inst 0.799220 # Average percentage of cache occupancy
683 system.cpu.icache.tags.occ_percent::total 0.799220 # Average percentage of cache occupancy
684 system.cpu.icache.tags.occ_task_id_blocks::1024 1976 # Occupied blocks per task id
685 system.cpu.icache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id
686 system.cpu.icache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id
687 system.cpu.icache.tags.age_task_id_blocks_1024::2 869 # Occupied blocks per task id
688 system.cpu.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id
689 system.cpu.icache.tags.age_task_id_blocks_1024::4 788 # Occupied blocks per task id
690 system.cpu.icache.tags.occ_task_id_percent::1024 0.964844 # Percentage of cache occupancy per task id
691 system.cpu.icache.tags.tag_accesses 48542851 # Number of tag accesses
692 system.cpu.icache.tags.data_accesses 48542851 # Number of data accesses
693 system.cpu.icache.ReadReq_hits::cpu.inst 24258362 # number of ReadReq hits
694 system.cpu.icache.ReadReq_hits::total 24258362 # number of ReadReq hits
695 system.cpu.icache.demand_hits::cpu.inst 24258362 # number of demand (read+write) hits
696 system.cpu.icache.demand_hits::total 24258362 # number of demand (read+write) hits
697 system.cpu.icache.overall_hits::cpu.inst 24258362 # number of overall hits
698 system.cpu.icache.overall_hits::total 24258362 # number of overall hits
699 system.cpu.icache.ReadReq_misses::cpu.inst 9429 # number of ReadReq misses
700 system.cpu.icache.ReadReq_misses::total 9429 # number of ReadReq misses
701 system.cpu.icache.demand_misses::cpu.inst 9429 # number of demand (read+write) misses
702 system.cpu.icache.demand_misses::total 9429 # number of demand (read+write) misses
703 system.cpu.icache.overall_misses::cpu.inst 9429 # number of overall misses
704 system.cpu.icache.overall_misses::total 9429 # number of overall misses
705 system.cpu.icache.ReadReq_miss_latency::cpu.inst 409019999 # number of ReadReq miss cycles
706 system.cpu.icache.ReadReq_miss_latency::total 409019999 # number of ReadReq miss cycles
707 system.cpu.icache.demand_miss_latency::cpu.inst 409019999 # number of demand (read+write) miss cycles
708 system.cpu.icache.demand_miss_latency::total 409019999 # number of demand (read+write) miss cycles
709 system.cpu.icache.overall_miss_latency::cpu.inst 409019999 # number of overall miss cycles
710 system.cpu.icache.overall_miss_latency::total 409019999 # number of overall miss cycles
711 system.cpu.icache.ReadReq_accesses::cpu.inst 24267791 # number of ReadReq accesses(hits+misses)
712 system.cpu.icache.ReadReq_accesses::total 24267791 # number of ReadReq accesses(hits+misses)
713 system.cpu.icache.demand_accesses::cpu.inst 24267791 # number of demand (read+write) accesses
714 system.cpu.icache.demand_accesses::total 24267791 # number of demand (read+write) accesses
715 system.cpu.icache.overall_accesses::cpu.inst 24267791 # number of overall (read+write) accesses
716 system.cpu.icache.overall_accesses::total 24267791 # number of overall (read+write) accesses
717 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000389 # miss rate for ReadReq accesses
718 system.cpu.icache.ReadReq_miss_rate::total 0.000389 # miss rate for ReadReq accesses
719 system.cpu.icache.demand_miss_rate::cpu.inst 0.000389 # miss rate for demand accesses
720 system.cpu.icache.demand_miss_rate::total 0.000389 # miss rate for demand accesses
721 system.cpu.icache.overall_miss_rate::cpu.inst 0.000389 # miss rate for overall accesses
722 system.cpu.icache.overall_miss_rate::total 0.000389 # miss rate for overall accesses
723 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43378.937215 # average ReadReq miss latency
724 system.cpu.icache.ReadReq_avg_miss_latency::total 43378.937215 # average ReadReq miss latency
725 system.cpu.icache.demand_avg_miss_latency::cpu.inst 43378.937215 # average overall miss latency
726 system.cpu.icache.demand_avg_miss_latency::total 43378.937215 # average overall miss latency
727 system.cpu.icache.overall_avg_miss_latency::cpu.inst 43378.937215 # average overall miss latency
728 system.cpu.icache.overall_avg_miss_latency::total 43378.937215 # average overall miss latency
729 system.cpu.icache.blocked_cycles::no_mshrs 793 # number of cycles access was blocked
730 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
731 system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked
732 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
733 system.cpu.icache.avg_blocked_cycles::no_mshrs 61 # average number of cycles each access was blocked
734 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
735 system.cpu.icache.fast_writes 0 # number of fast writes performed
736 system.cpu.icache.cache_copies 0 # number of cache copies performed
737 system.cpu.icache.writebacks::writebacks 5017 # number of writebacks
738 system.cpu.icache.writebacks::total 5017 # number of writebacks
739 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2159 # number of ReadReq MSHR hits
740 system.cpu.icache.ReadReq_mshr_hits::total 2159 # number of ReadReq MSHR hits
741 system.cpu.icache.demand_mshr_hits::cpu.inst 2159 # number of demand (read+write) MSHR hits
742 system.cpu.icache.demand_mshr_hits::total 2159 # number of demand (read+write) MSHR hits
743 system.cpu.icache.overall_mshr_hits::cpu.inst 2159 # number of overall MSHR hits
744 system.cpu.icache.overall_mshr_hits::total 2159 # number of overall MSHR hits
745 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7270 # number of ReadReq MSHR misses
746 system.cpu.icache.ReadReq_mshr_misses::total 7270 # number of ReadReq MSHR misses
747 system.cpu.icache.demand_mshr_misses::cpu.inst 7270 # number of demand (read+write) MSHR misses
748 system.cpu.icache.demand_mshr_misses::total 7270 # number of demand (read+write) MSHR misses
749 system.cpu.icache.overall_mshr_misses::cpu.inst 7270 # number of overall MSHR misses
750 system.cpu.icache.overall_mshr_misses::total 7270 # number of overall MSHR misses
751 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 311109999 # number of ReadReq MSHR miss cycles
752 system.cpu.icache.ReadReq_mshr_miss_latency::total 311109999 # number of ReadReq MSHR miss cycles
753 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 311109999 # number of demand (read+write) MSHR miss cycles
754 system.cpu.icache.demand_mshr_miss_latency::total 311109999 # number of demand (read+write) MSHR miss cycles
755 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 311109999 # number of overall MSHR miss cycles
756 system.cpu.icache.overall_mshr_miss_latency::total 311109999 # number of overall MSHR miss cycles
757 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000300 # mshr miss rate for ReadReq accesses
758 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000300 # mshr miss rate for ReadReq accesses
759 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000300 # mshr miss rate for demand accesses
760 system.cpu.icache.demand_mshr_miss_rate::total 0.000300 # mshr miss rate for demand accesses
761 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000300 # mshr miss rate for overall accesses
762 system.cpu.icache.overall_mshr_miss_rate::total 0.000300 # mshr miss rate for overall accesses
763 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42793.672490 # average ReadReq mshr miss latency
764 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42793.672490 # average ReadReq mshr miss latency
765 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42793.672490 # average overall mshr miss latency
766 system.cpu.icache.demand_avg_mshr_miss_latency::total 42793.672490 # average overall mshr miss latency
767 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42793.672490 # average overall mshr miss latency
768 system.cpu.icache.overall_avg_mshr_miss_latency::total 42793.672490 # average overall mshr miss latency
769 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
770 system.cpu.l2cache.tags.replacements 0 # number of replacements
771 system.cpu.l2cache.tags.tagsinuse 2581.252539 # Cycle average of tags in use
772 system.cpu.l2cache.tags.total_refs 8528 # Total number of references to valid blocks.
773 system.cpu.l2cache.tags.sampled_refs 3879 # Sample count of references to valid blocks.
774 system.cpu.l2cache.tags.avg_refs 2.198505 # Average number of references to valid blocks.
775 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
776 system.cpu.l2cache.tags.occ_blocks::writebacks 1.770890 # Average occupied blocks per requestor
777 system.cpu.l2cache.tags.occ_blocks::cpu.inst 2276.984589 # Average occupied blocks per requestor
778 system.cpu.l2cache.tags.occ_blocks::cpu.data 302.497060 # Average occupied blocks per requestor
779 system.cpu.l2cache.tags.occ_percent::writebacks 0.000054 # Average percentage of cache occupancy
780 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069488 # Average percentage of cache occupancy
781 system.cpu.l2cache.tags.occ_percent::cpu.data 0.009231 # Average percentage of cache occupancy
782 system.cpu.l2cache.tags.occ_percent::total 0.078774 # Average percentage of cache occupancy
783 system.cpu.l2cache.tags.occ_task_id_blocks::1024 3879 # Occupied blocks per task id
784 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
785 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id
786 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 999 # Occupied blocks per task id
787 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 41 # Occupied blocks per task id
788 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2611 # Occupied blocks per task id
789 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.118378 # Percentage of cache occupancy per task id
790 system.cpu.l2cache.tags.tag_accesses 119261 # Number of tag accesses
791 system.cpu.l2cache.tags.data_accesses 119261 # Number of data accesses
792 system.cpu.l2cache.WritebackDirty_hits::writebacks 10 # number of WritebackDirty hits
793 system.cpu.l2cache.WritebackDirty_hits::total 10 # number of WritebackDirty hits
794 system.cpu.l2cache.WritebackClean_hits::writebacks 4917 # number of WritebackClean hits
795 system.cpu.l2cache.WritebackClean_hits::total 4917 # number of WritebackClean hits
796 system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits
797 system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits
798 system.cpu.l2cache.ReadExReq_hits::cpu.data 6 # number of ReadExReq hits
799 system.cpu.l2cache.ReadExReq_hits::total 6 # number of ReadExReq hits
800 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3531 # number of ReadCleanReq hits
801 system.cpu.l2cache.ReadCleanReq_hits::total 3531 # number of ReadCleanReq hits
802 system.cpu.l2cache.ReadSharedReq_hits::cpu.data 35 # number of ReadSharedReq hits
803 system.cpu.l2cache.ReadSharedReq_hits::total 35 # number of ReadSharedReq hits
804 system.cpu.l2cache.demand_hits::cpu.inst 3531 # number of demand (read+write) hits
805 system.cpu.l2cache.demand_hits::cpu.data 41 # number of demand (read+write) hits
806 system.cpu.l2cache.demand_hits::total 3572 # number of demand (read+write) hits
807 system.cpu.l2cache.overall_hits::cpu.inst 3531 # number of overall hits
808 system.cpu.l2cache.overall_hits::cpu.data 41 # number of overall hits
809 system.cpu.l2cache.overall_hits::total 3572 # number of overall hits
810 system.cpu.l2cache.UpgradeReq_misses::cpu.data 276 # number of UpgradeReq misses
811 system.cpu.l2cache.UpgradeReq_misses::total 276 # number of UpgradeReq misses
812 system.cpu.l2cache.ReadExReq_misses::cpu.data 1535 # number of ReadExReq misses
813 system.cpu.l2cache.ReadExReq_misses::total 1535 # number of ReadExReq misses
814 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3460 # number of ReadCleanReq misses
815 system.cpu.l2cache.ReadCleanReq_misses::total 3460 # number of ReadCleanReq misses
816 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 419 # number of ReadSharedReq misses
817 system.cpu.l2cache.ReadSharedReq_misses::total 419 # number of ReadSharedReq misses
818 system.cpu.l2cache.demand_misses::cpu.inst 3460 # number of demand (read+write) misses
819 system.cpu.l2cache.demand_misses::cpu.data 1954 # number of demand (read+write) misses
820 system.cpu.l2cache.demand_misses::total 5414 # number of demand (read+write) misses
821 system.cpu.l2cache.overall_misses::cpu.inst 3460 # number of overall misses
822 system.cpu.l2cache.overall_misses::cpu.data 1954 # number of overall misses
823 system.cpu.l2cache.overall_misses::total 5414 # number of overall misses
824 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 115784500 # number of ReadExReq miss cycles
825 system.cpu.l2cache.ReadExReq_miss_latency::total 115784500 # number of ReadExReq miss cycles
826 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 262406500 # number of ReadCleanReq miss cycles
827 system.cpu.l2cache.ReadCleanReq_miss_latency::total 262406500 # number of ReadCleanReq miss cycles
828 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 34977000 # number of ReadSharedReq miss cycles
829 system.cpu.l2cache.ReadSharedReq_miss_latency::total 34977000 # number of ReadSharedReq miss cycles
830 system.cpu.l2cache.demand_miss_latency::cpu.inst 262406500 # number of demand (read+write) miss cycles
831 system.cpu.l2cache.demand_miss_latency::cpu.data 150761500 # number of demand (read+write) miss cycles
832 system.cpu.l2cache.demand_miss_latency::total 413168000 # number of demand (read+write) miss cycles
833 system.cpu.l2cache.overall_miss_latency::cpu.inst 262406500 # number of overall miss cycles
834 system.cpu.l2cache.overall_miss_latency::cpu.data 150761500 # number of overall miss cycles
835 system.cpu.l2cache.overall_miss_latency::total 413168000 # number of overall miss cycles
836 system.cpu.l2cache.WritebackDirty_accesses::writebacks 10 # number of WritebackDirty accesses(hits+misses)
837 system.cpu.l2cache.WritebackDirty_accesses::total 10 # number of WritebackDirty accesses(hits+misses)
838 system.cpu.l2cache.WritebackClean_accesses::writebacks 4917 # number of WritebackClean accesses(hits+misses)
839 system.cpu.l2cache.WritebackClean_accesses::total 4917 # number of WritebackClean accesses(hits+misses)
840 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 277 # number of UpgradeReq accesses(hits+misses)
841 system.cpu.l2cache.UpgradeReq_accesses::total 277 # number of UpgradeReq accesses(hits+misses)
842 system.cpu.l2cache.ReadExReq_accesses::cpu.data 1541 # number of ReadExReq accesses(hits+misses)
843 system.cpu.l2cache.ReadExReq_accesses::total 1541 # number of ReadExReq accesses(hits+misses)
844 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 6991 # number of ReadCleanReq accesses(hits+misses)
845 system.cpu.l2cache.ReadCleanReq_accesses::total 6991 # number of ReadCleanReq accesses(hits+misses)
846 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 454 # number of ReadSharedReq accesses(hits+misses)
847 system.cpu.l2cache.ReadSharedReq_accesses::total 454 # number of ReadSharedReq accesses(hits+misses)
848 system.cpu.l2cache.demand_accesses::cpu.inst 6991 # number of demand (read+write) accesses
849 system.cpu.l2cache.demand_accesses::cpu.data 1995 # number of demand (read+write) accesses
850 system.cpu.l2cache.demand_accesses::total 8986 # number of demand (read+write) accesses
851 system.cpu.l2cache.overall_accesses::cpu.inst 6991 # number of overall (read+write) accesses
852 system.cpu.l2cache.overall_accesses::cpu.data 1995 # number of overall (read+write) accesses
853 system.cpu.l2cache.overall_accesses::total 8986 # number of overall (read+write) accesses
854 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.996390 # miss rate for UpgradeReq accesses
855 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.996390 # miss rate for UpgradeReq accesses
856 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.996106 # miss rate for ReadExReq accesses
857 system.cpu.l2cache.ReadExReq_miss_rate::total 0.996106 # miss rate for ReadExReq accesses
858 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.494922 # miss rate for ReadCleanReq accesses
859 system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.494922 # miss rate for ReadCleanReq accesses
860 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.922907 # miss rate for ReadSharedReq accesses
861 system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.922907 # miss rate for ReadSharedReq accesses
862 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.494922 # miss rate for demand accesses
863 system.cpu.l2cache.demand_miss_rate::cpu.data 0.979449 # miss rate for demand accesses
864 system.cpu.l2cache.demand_miss_rate::total 0.602493 # miss rate for demand accesses
865 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.494922 # miss rate for overall accesses
866 system.cpu.l2cache.overall_miss_rate::cpu.data 0.979449 # miss rate for overall accesses
867 system.cpu.l2cache.overall_miss_rate::total 0.602493 # miss rate for overall accesses
868 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75429.641694 # average ReadExReq miss latency
869 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75429.641694 # average ReadExReq miss latency
870 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75840.028902 # average ReadCleanReq miss latency
871 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75840.028902 # average ReadCleanReq miss latency
872 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83477.326969 # average ReadSharedReq miss latency
873 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83477.326969 # average ReadSharedReq miss latency
874 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75840.028902 # average overall miss latency
875 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77155.322416 # average overall miss latency
876 system.cpu.l2cache.demand_avg_miss_latency::total 76314.739564 # average overall miss latency
877 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75840.028902 # average overall miss latency
878 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77155.322416 # average overall miss latency
879 system.cpu.l2cache.overall_avg_miss_latency::total 76314.739564 # average overall miss latency
880 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
881 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
882 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
883 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
884 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
885 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
886 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
887 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
888 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 276 # number of UpgradeReq MSHR misses
889 system.cpu.l2cache.UpgradeReq_mshr_misses::total 276 # number of UpgradeReq MSHR misses
890 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1535 # number of ReadExReq MSHR misses
891 system.cpu.l2cache.ReadExReq_mshr_misses::total 1535 # number of ReadExReq MSHR misses
892 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3460 # number of ReadCleanReq MSHR misses
893 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3460 # number of ReadCleanReq MSHR misses
894 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 419 # number of ReadSharedReq MSHR misses
895 system.cpu.l2cache.ReadSharedReq_mshr_misses::total 419 # number of ReadSharedReq MSHR misses
896 system.cpu.l2cache.demand_mshr_misses::cpu.inst 3460 # number of demand (read+write) MSHR misses
897 system.cpu.l2cache.demand_mshr_misses::cpu.data 1954 # number of demand (read+write) MSHR misses
898 system.cpu.l2cache.demand_mshr_misses::total 5414 # number of demand (read+write) MSHR misses
899 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3460 # number of overall MSHR misses
900 system.cpu.l2cache.overall_mshr_misses::cpu.data 1954 # number of overall MSHR misses
901 system.cpu.l2cache.overall_mshr_misses::total 5414 # number of overall MSHR misses
902 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5237000 # number of UpgradeReq MSHR miss cycles
903 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5237000 # number of UpgradeReq MSHR miss cycles
904 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 100434500 # number of ReadExReq MSHR miss cycles
905 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 100434500 # number of ReadExReq MSHR miss cycles
906 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 227816500 # number of ReadCleanReq MSHR miss cycles
907 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 227816500 # number of ReadCleanReq MSHR miss cycles
908 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30787000 # number of ReadSharedReq MSHR miss cycles
909 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30787000 # number of ReadSharedReq MSHR miss cycles
910 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 227816500 # number of demand (read+write) MSHR miss cycles
911 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 131221500 # number of demand (read+write) MSHR miss cycles
912 system.cpu.l2cache.demand_mshr_miss_latency::total 359038000 # number of demand (read+write) MSHR miss cycles
913 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 227816500 # number of overall MSHR miss cycles
914 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 131221500 # number of overall MSHR miss cycles
915 system.cpu.l2cache.overall_mshr_miss_latency::total 359038000 # number of overall MSHR miss cycles
916 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.996390 # mshr miss rate for UpgradeReq accesses
917 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.996390 # mshr miss rate for UpgradeReq accesses
918 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.996106 # mshr miss rate for ReadExReq accesses
919 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.996106 # mshr miss rate for ReadExReq accesses
920 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.494922 # mshr miss rate for ReadCleanReq accesses
921 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.494922 # mshr miss rate for ReadCleanReq accesses
922 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.922907 # mshr miss rate for ReadSharedReq accesses
923 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.922907 # mshr miss rate for ReadSharedReq accesses
924 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.494922 # mshr miss rate for demand accesses
925 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.979449 # mshr miss rate for demand accesses
926 system.cpu.l2cache.demand_mshr_miss_rate::total 0.602493 # mshr miss rate for demand accesses
927 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.494922 # mshr miss rate for overall accesses
928 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.979449 # mshr miss rate for overall accesses
929 system.cpu.l2cache.overall_mshr_miss_rate::total 0.602493 # mshr miss rate for overall accesses
930 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18974.637681 # average UpgradeReq mshr miss latency
931 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18974.637681 # average UpgradeReq mshr miss latency
932 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65429.641694 # average ReadExReq mshr miss latency
933 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65429.641694 # average ReadExReq mshr miss latency
934 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65842.919075 # average ReadCleanReq mshr miss latency
935 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65842.919075 # average ReadCleanReq mshr miss latency
936 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73477.326969 # average ReadSharedReq mshr miss latency
937 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73477.326969 # average ReadSharedReq mshr miss latency
938 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65842.919075 # average overall mshr miss latency
939 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67155.322416 # average overall mshr miss latency
940 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66316.586627 # average overall mshr miss latency
941 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65842.919075 # average overall mshr miss latency
942 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67155.322416 # average overall mshr miss latency
943 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66316.586627 # average overall mshr miss latency
944 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
945 system.cpu.toL2Bus.snoop_filter.tot_requests 14610 # Total number of requests made to the snoop filter.
946 system.cpu.toL2Bus.snoop_filter.hit_single_requests 5368 # Number of requests hitting in the snoop filter with a single holder of the requested data.
947 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 377 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
948 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
949 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
950 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
951 system.cpu.toL2Bus.trans_dist::ReadResp 7723 # Transaction distribution
952 system.cpu.toL2Bus.trans_dist::WritebackDirty 10 # Transaction distribution
953 system.cpu.toL2Bus.trans_dist::WritebackClean 5017 # Transaction distribution
954 system.cpu.toL2Bus.trans_dist::CleanEvict 41 # Transaction distribution
955 system.cpu.toL2Bus.trans_dist::UpgradeReq 277 # Transaction distribution
956 system.cpu.toL2Bus.trans_dist::UpgradeResp 277 # Transaction distribution
957 system.cpu.toL2Bus.trans_dist::ReadExReq 1541 # Transaction distribution
958 system.cpu.toL2Bus.trans_dist::ReadExResp 1541 # Transaction distribution
959 system.cpu.toL2Bus.trans_dist::ReadCleanReq 7270 # Transaction distribution
960 system.cpu.toL2Bus.trans_dist::ReadSharedReq 454 # Transaction distribution
961 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19277 # Packet count per connected master and slave (bytes)
962 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4595 # Packet count per connected master and slave (bytes)
963 system.cpu.toL2Bus.pkt_count::total 23872 # Packet count per connected master and slave (bytes)
964 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 768448 # Cumulative packet size per connected master and slave (bytes)
965 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128320 # Cumulative packet size per connected master and slave (bytes)
966 system.cpu.toL2Bus.pkt_size::total 896768 # Cumulative packet size per connected master and slave (bytes)
967 system.cpu.toL2Bus.snoops 279 # Total snoops (count)
968 system.cpu.toL2Bus.snoop_fanout::samples 9542 # Request fanout histogram
969 system.cpu.toL2Bus.snoop_fanout::mean 0.070845 # Request fanout histogram
970 system.cpu.toL2Bus.snoop_fanout::stdev 0.256579 # Request fanout histogram
971 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
972 system.cpu.toL2Bus.snoop_fanout::0 8866 92.92% 92.92% # Request fanout histogram
973 system.cpu.toL2Bus.snoop_fanout::1 676 7.08% 100.00% # Request fanout histogram
974 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
975 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
976 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
977 system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
978 system.cpu.toL2Bus.snoop_fanout::total 9542 # Request fanout histogram
979 system.cpu.toL2Bus.reqLayer0.occupancy 12332000 # Layer occupancy (ticks)
980 system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
981 system.cpu.toL2Bus.respLayer0.occupancy 10903500 # Layer occupancy (ticks)
982 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
983 system.cpu.toL2Bus.respLayer1.occupancy 3131998 # Layer occupancy (ticks)
984 system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
985 system.membus.trans_dist::ReadResp 3878 # Transaction distribution
986 system.membus.trans_dist::UpgradeReq 276 # Transaction distribution
987 system.membus.trans_dist::ReadExReq 1535 # Transaction distribution
988 system.membus.trans_dist::ReadExResp 1535 # Transaction distribution
989 system.membus.trans_dist::ReadSharedReq 3878 # Transaction distribution
990 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11102 # Packet count per connected master and slave (bytes)
991 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11102 # Packet count per connected master and slave (bytes)
992 system.membus.pkt_count::total 11102 # Packet count per connected master and slave (bytes)
993 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 346432 # Cumulative packet size per connected master and slave (bytes)
994 system.membus.pkt_size_system.cpu.l2cache.mem_side::total 346432 # Cumulative packet size per connected master and slave (bytes)
995 system.membus.pkt_size::total 346432 # Cumulative packet size per connected master and slave (bytes)
996 system.membus.snoops 0 # Total snoops (count)
997 system.membus.snoop_fanout::samples 5689 # Request fanout histogram
998 system.membus.snoop_fanout::mean 0 # Request fanout histogram
999 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1000 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1001 system.membus.snoop_fanout::0 5689 100.00% 100.00% # Request fanout histogram
1002 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
1003 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1004 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1005 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
1006 system.membus.snoop_fanout::total 5689 # Request fanout histogram
1007 system.membus.reqLayer0.occupancy 6955500 # Layer occupancy (ticks)
1008 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1009 system.membus.respLayer1.occupancy 28681250 # Layer occupancy (ticks)
1010 system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
1012 ---------- End Simulation Statistics ----------
projects / gem5.git / blob