2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.144463 # Number of seconds simulated
4 sim_ticks 144463317000 # Number of ticks simulated
5 final_tick 144463317000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 55445 # Simulator instruction rate (inst/s)
8 host_op_rate 92931 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 60647702 # Simulator tick rate (ticks/s)
10 host_mem_usage 328672 # Number of bytes of host memory used
11 host_seconds 2382.01 # Real time elapsed on the host
12 sim_insts 132071192 # Number of instructions simulated
13 sim_ops 221363384 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 217088 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 125568 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 342656 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 217088 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 217088 # Number of instructions bytes read from this memory
19 system.physmem.num_reads::cpu.inst 3392 # Number of read requests responded to by this memory
20 system.physmem.num_reads::cpu.data 1962 # Number of read requests responded to by this memory
21 system.physmem.num_reads::total 5354 # Number of read requests responded to by this memory
22 system.physmem.bw_read::cpu.inst 1502721 # Total read bandwidth from this memory (bytes/s)
23 system.physmem.bw_read::cpu.data 869203 # Total read bandwidth from this memory (bytes/s)
24 system.physmem.bw_read::total 2371924 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_inst_read::cpu.inst 1502721 # Instruction read bandwidth from this memory (bytes/s)
26 system.physmem.bw_inst_read::total 1502721 # Instruction read bandwidth from this memory (bytes/s)
27 system.physmem.bw_total::cpu.inst 1502721 # Total bandwidth to/from this memory (bytes/s)
28 system.physmem.bw_total::cpu.data 869203 # Total bandwidth to/from this memory (bytes/s)
29 system.physmem.bw_total::total 2371924 # Total bandwidth to/from this memory (bytes/s)
30 system.physmem.readReqs 5354 # Number of read requests accepted
31 system.physmem.writeReqs 0 # Number of write requests accepted
32 system.physmem.readBursts 5354 # Number of DRAM read bursts, including those serviced by the write queue
33 system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
34 system.physmem.bytesReadDRAM 342656 # Total number of bytes read from DRAM
35 system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
36 system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
37 system.physmem.bytesReadSys 342656 # Total read bytes from the system interface side
38 system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
39 system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
40 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
41 system.physmem.neitherReadNorWriteReqs 163 # Number of requests that are neither read nor write
42 system.physmem.perBankRdBursts::0 289 # Per bank write bursts
43 system.physmem.perBankRdBursts::1 357 # Per bank write bursts
44 system.physmem.perBankRdBursts::2 453 # Per bank write bursts
45 system.physmem.perBankRdBursts::3 356 # Per bank write bursts
46 system.physmem.perBankRdBursts::4 332 # Per bank write bursts
47 system.physmem.perBankRdBursts::5 326 # Per bank write bursts
48 system.physmem.perBankRdBursts::6 402 # Per bank write bursts
49 system.physmem.perBankRdBursts::7 377 # Per bank write bursts
50 system.physmem.perBankRdBursts::8 341 # Per bank write bursts
51 system.physmem.perBankRdBursts::9 276 # Per bank write bursts
52 system.physmem.perBankRdBursts::10 232 # Per bank write bursts
53 system.physmem.perBankRdBursts::11 277 # Per bank write bursts
54 system.physmem.perBankRdBursts::12 205 # Per bank write bursts
55 system.physmem.perBankRdBursts::13 465 # Per bank write bursts
56 system.physmem.perBankRdBursts::14 384 # Per bank write bursts
57 system.physmem.perBankRdBursts::15 282 # Per bank write bursts
58 system.physmem.perBankWrBursts::0 0 # Per bank write bursts
59 system.physmem.perBankWrBursts::1 0 # Per bank write bursts
60 system.physmem.perBankWrBursts::2 0 # Per bank write bursts
61 system.physmem.perBankWrBursts::3 0 # Per bank write bursts
62 system.physmem.perBankWrBursts::4 0 # Per bank write bursts
63 system.physmem.perBankWrBursts::5 0 # Per bank write bursts
64 system.physmem.perBankWrBursts::6 0 # Per bank write bursts
65 system.physmem.perBankWrBursts::7 0 # Per bank write bursts
66 system.physmem.perBankWrBursts::8 0 # Per bank write bursts
67 system.physmem.perBankWrBursts::9 0 # Per bank write bursts
68 system.physmem.perBankWrBursts::10 0 # Per bank write bursts
69 system.physmem.perBankWrBursts::11 0 # Per bank write bursts
70 system.physmem.perBankWrBursts::12 0 # Per bank write bursts
71 system.physmem.perBankWrBursts::13 0 # Per bank write bursts
72 system.physmem.perBankWrBursts::14 0 # Per bank write bursts
73 system.physmem.perBankWrBursts::15 0 # Per bank write bursts
74 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
75 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
76 system.physmem.totGap 144463266500 # Total gap between requests
77 system.physmem.readPktSize::0 0 # Read request sizes (log2)
78 system.physmem.readPktSize::1 0 # Read request sizes (log2)
79 system.physmem.readPktSize::2 0 # Read request sizes (log2)
80 system.physmem.readPktSize::3 0 # Read request sizes (log2)
81 system.physmem.readPktSize::4 0 # Read request sizes (log2)
82 system.physmem.readPktSize::5 0 # Read request sizes (log2)
83 system.physmem.readPktSize::6 5354 # Read request sizes (log2)
84 system.physmem.writePktSize::0 0 # Write request sizes (log2)
85 system.physmem.writePktSize::1 0 # Write request sizes (log2)
86 system.physmem.writePktSize::2 0 # Write request sizes (log2)
87 system.physmem.writePktSize::3 0 # Write request sizes (log2)
88 system.physmem.writePktSize::4 0 # Write request sizes (log2)
89 system.physmem.writePktSize::5 0 # Write request sizes (log2)
90 system.physmem.writePktSize::6 0 # Write request sizes (log2)
91 system.physmem.rdQLenPdf::0 4302 # What read queue length does an incoming req see
92 system.physmem.rdQLenPdf::1 874 # What read queue length does an incoming req see
93 system.physmem.rdQLenPdf::2 155 # What read queue length does an incoming req see
94 system.physmem.rdQLenPdf::3 20 # What read queue length does an incoming req see
95 system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
96 system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
97 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
98 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
99 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
100 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
123 system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
124 system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
125 system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
126 system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
127 system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
128 system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
129 system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
130 system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
131 system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
132 system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
155 system.physmem.bytesPerActivate::samples 957 # Bytes accessed per row activation
156 system.physmem.bytesPerActivate::mean 353.103448 # Bytes accessed per row activation
157 system.physmem.bytesPerActivate::gmean 172.307957 # Bytes accessed per row activation
158 system.physmem.bytesPerActivate::stdev 612.115437 # Bytes accessed per row activation
159 system.physmem.bytesPerActivate::64 385 40.23% 40.23% # Bytes accessed per row activation
160 system.physmem.bytesPerActivate::128 164 17.14% 57.37% # Bytes accessed per row activation
161 system.physmem.bytesPerActivate::192 81 8.46% 65.83% # Bytes accessed per row activation
162 system.physmem.bytesPerActivate::256 46 4.81% 70.64% # Bytes accessed per row activation
163 system.physmem.bytesPerActivate::320 43 4.49% 75.13% # Bytes accessed per row activation
164 system.physmem.bytesPerActivate::384 20 2.09% 77.22% # Bytes accessed per row activation
165 system.physmem.bytesPerActivate::448 26 2.72% 79.94% # Bytes accessed per row activation
166 system.physmem.bytesPerActivate::512 19 1.99% 81.92% # Bytes accessed per row activation
167 system.physmem.bytesPerActivate::576 17 1.78% 83.70% # Bytes accessed per row activation
168 system.physmem.bytesPerActivate::640 26 2.72% 86.42% # Bytes accessed per row activation
169 system.physmem.bytesPerActivate::704 27 2.82% 89.24% # Bytes accessed per row activation
170 system.physmem.bytesPerActivate::768 7 0.73% 89.97% # Bytes accessed per row activation
171 system.physmem.bytesPerActivate::832 7 0.73% 90.70% # Bytes accessed per row activation
172 system.physmem.bytesPerActivate::896 7 0.73% 91.43% # Bytes accessed per row activation
173 system.physmem.bytesPerActivate::960 3 0.31% 91.75% # Bytes accessed per row activation
174 system.physmem.bytesPerActivate::1024 5 0.52% 92.27% # Bytes accessed per row activation
175 system.physmem.bytesPerActivate::1088 6 0.63% 92.89% # Bytes accessed per row activation
176 system.physmem.bytesPerActivate::1152 6 0.63% 93.52% # Bytes accessed per row activation
177 system.physmem.bytesPerActivate::1216 4 0.42% 93.94% # Bytes accessed per row activation
178 system.physmem.bytesPerActivate::1280 2 0.21% 94.15% # Bytes accessed per row activation
179 system.physmem.bytesPerActivate::1344 2 0.21% 94.36% # Bytes accessed per row activation
180 system.physmem.bytesPerActivate::1408 3 0.31% 94.67% # Bytes accessed per row activation
181 system.physmem.bytesPerActivate::1472 7 0.73% 95.40% # Bytes accessed per row activation
182 system.physmem.bytesPerActivate::1536 1 0.10% 95.51% # Bytes accessed per row activation
183 system.physmem.bytesPerActivate::1600 5 0.52% 96.03% # Bytes accessed per row activation
184 system.physmem.bytesPerActivate::1664 4 0.42% 96.45% # Bytes accessed per row activation
185 system.physmem.bytesPerActivate::1728 2 0.21% 96.66% # Bytes accessed per row activation
186 system.physmem.bytesPerActivate::1792 2 0.21% 96.87% # Bytes accessed per row activation
187 system.physmem.bytesPerActivate::1856 2 0.21% 97.07% # Bytes accessed per row activation
188 system.physmem.bytesPerActivate::1920 3 0.31% 97.39% # Bytes accessed per row activation
189 system.physmem.bytesPerActivate::1984 2 0.21% 97.60% # Bytes accessed per row activation
190 system.physmem.bytesPerActivate::2112 1 0.10% 97.70% # Bytes accessed per row activation
191 system.physmem.bytesPerActivate::2176 1 0.10% 97.81% # Bytes accessed per row activation
192 system.physmem.bytesPerActivate::2240 1 0.10% 97.91% # Bytes accessed per row activation
193 system.physmem.bytesPerActivate::2304 1 0.10% 98.01% # Bytes accessed per row activation
194 system.physmem.bytesPerActivate::2368 1 0.10% 98.12% # Bytes accessed per row activation
195 system.physmem.bytesPerActivate::2432 2 0.21% 98.33% # Bytes accessed per row activation
196 system.physmem.bytesPerActivate::2496 1 0.10% 98.43% # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::2816 2 0.21% 98.64% # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::2880 3 0.31% 98.96% # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::3072 1 0.10% 99.06% # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::3328 1 0.10% 99.16% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::3456 1 0.10% 99.27% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::3584 1 0.10% 99.37% # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::4160 1 0.10% 99.48% # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::4352 1 0.10% 99.58% # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::4736 1 0.10% 99.69% # Bytes accessed per row activation
206 system.physmem.bytesPerActivate::5312 1 0.10% 99.79% # Bytes accessed per row activation
207 system.physmem.bytesPerActivate::5696 1 0.10% 99.90% # Bytes accessed per row activation
208 system.physmem.bytesPerActivate::5952 1 0.10% 100.00% # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::total 957 # Bytes accessed per row activation
210 system.physmem.totQLat 28783000 # Total ticks spent queuing
211 system.physmem.totMemAccLat 137846750 # Total ticks spent from burst creation until serviced by the DRAM
212 system.physmem.totBusLat 26770000 # Total ticks spent in databus transfers
213 system.physmem.totBankLat 82293750 # Total ticks spent accessing banks
214 system.physmem.avgQLat 5375.98 # Average queueing delay per DRAM burst
215 system.physmem.avgBankLat 15370.52 # Average bank access latency per DRAM burst
216 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
217 system.physmem.avgMemAccLat 25746.50 # Average memory access latency per DRAM burst
218 system.physmem.avgRdBW 2.37 # Average DRAM read bandwidth in MiByte/s
219 system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
220 system.physmem.avgRdBWSys 2.37 # Average system read bandwidth in MiByte/s
221 system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
222 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
223 system.physmem.busUtil 0.02 # Data bus utilization in percentage
224 system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
225 system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
226 system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing
227 system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
228 system.physmem.readRowHits 4397 # Number of row buffer hits during reads
229 system.physmem.writeRowHits 0 # Number of row buffer hits during writes
230 system.physmem.readRowHitRate 82.13 # Row buffer hit rate for reads
231 system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
232 system.physmem.avgGap 26982306.03 # Average gap between requests
233 system.physmem.pageHitRate 82.13 # Row buffer hit rate, read and write combined
234 system.physmem.prechargeAllPercent 0.41 # Percentage of time for which DRAM has all the banks in precharge state
235 system.membus.throughput 2371924 # Throughput (bytes/s)
236 system.membus.trans_dist::ReadReq 3822 # Transaction distribution
237 system.membus.trans_dist::ReadResp 3822 # Transaction distribution
238 system.membus.trans_dist::UpgradeReq 163 # Transaction distribution
239 system.membus.trans_dist::UpgradeResp 163 # Transaction distribution
240 system.membus.trans_dist::ReadExReq 1532 # Transaction distribution
241 system.membus.trans_dist::ReadExResp 1532 # Transaction distribution
242 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11034 # Packet count per connected master and slave (bytes)
243 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11034 # Packet count per connected master and slave (bytes)
244 system.membus.pkt_count::total 11034 # Packet count per connected master and slave (bytes)
245 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 342656 # Cumulative packet size per connected master and slave (bytes)
246 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 342656 # Cumulative packet size per connected master and slave (bytes)
247 system.membus.tot_pkt_size::total 342656 # Cumulative packet size per connected master and slave (bytes)
248 system.membus.data_through_bus 342656 # Total data (bytes)
249 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
250 system.membus.reqLayer0.occupancy 6950000 # Layer occupancy (ticks)
251 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
252 system.membus.respLayer1.occupancy 50662837 # Layer occupancy (ticks)
253 system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
254 system.cpu.branchPred.lookups 18648233 # Number of BP lookups
255 system.cpu.branchPred.condPredicted 18648233 # Number of conditional branches predicted
256 system.cpu.branchPred.condIncorrect 1490176 # Number of conditional branches incorrect
257 system.cpu.branchPred.BTBLookups 11407549 # Number of BTB lookups
258 system.cpu.branchPred.BTBHits 10790529 # Number of BTB hits
259 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
260 system.cpu.branchPred.BTBHitPct 94.591126 # BTB Hit Percentage
261 system.cpu.branchPred.usedRAS 1320367 # Number of times the RAS was used to get a target.
262 system.cpu.branchPred.RASInCorrect 22841 # Number of incorrect RAS predictions.
263 system.cpu.workload.num_syscalls 400 # Number of system calls
264 system.cpu.numCycles 289221873 # number of cpu cycles simulated
265 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
266 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
267 system.cpu.fetch.icacheStallCycles 23458043 # Number of cycles fetch is stalled on an Icache miss
268 system.cpu.fetch.Insts 206724218 # Number of instructions fetch has processed
269 system.cpu.fetch.Branches 18648233 # Number of branches that fetch encountered
270 system.cpu.fetch.predictedBranches 12110896 # Number of branches that fetch has predicted taken
271 system.cpu.fetch.Cycles 54209097 # Number of cycles fetch has run and was not squashing or blocked
272 system.cpu.fetch.SquashCycles 15518774 # Number of cycles fetch has spent squashing
273 system.cpu.fetch.BlockedCycles 178161359 # Number of cycles fetch has spent blocked
274 system.cpu.fetch.MiscStallCycles 1571 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
275 system.cpu.fetch.PendingTrapStallCycles 9111 # Number of stall cycles due to pending traps
276 system.cpu.fetch.IcacheWaitRetryStallCycles 38 # Number of stall cycles due to full MSHR
277 system.cpu.fetch.CacheLines 22353211 # Number of cache lines fetched
278 system.cpu.fetch.IcacheSquashes 224061 # Number of outstanding Icache misses that were squashed
279 system.cpu.fetch.rateDist::samples 269612469 # Number of instructions fetched each cycle (Total)
280 system.cpu.fetch.rateDist::mean 1.268180 # Number of instructions fetched each cycle (Total)
281 system.cpu.fetch.rateDist::stdev 2.756310 # Number of instructions fetched each cycle (Total)
282 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
283 system.cpu.fetch.rateDist::0 216842563 80.43% 80.43% # Number of instructions fetched each cycle (Total)
284 system.cpu.fetch.rateDist::1 2848142 1.06% 81.48% # Number of instructions fetched each cycle (Total)
285 system.cpu.fetch.rateDist::2 2312055 0.86% 82.34% # Number of instructions fetched each cycle (Total)
286 system.cpu.fetch.rateDist::3 2633842 0.98% 83.32% # Number of instructions fetched each cycle (Total)
287 system.cpu.fetch.rateDist::4 3218714 1.19% 84.51% # Number of instructions fetched each cycle (Total)
288 system.cpu.fetch.rateDist::5 3388946 1.26% 85.77% # Number of instructions fetched each cycle (Total)
289 system.cpu.fetch.rateDist::6 3831195 1.42% 87.19% # Number of instructions fetched each cycle (Total)
290 system.cpu.fetch.rateDist::7 2559437 0.95% 88.14% # Number of instructions fetched each cycle (Total)
291 system.cpu.fetch.rateDist::8 31977575 11.86% 100.00% # Number of instructions fetched each cycle (Total)
292 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
293 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
294 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
295 system.cpu.fetch.rateDist::total 269612469 # Number of instructions fetched each cycle (Total)
296 system.cpu.fetch.branchRate 0.064477 # Number of branch fetches per cycle
297 system.cpu.fetch.rate 0.714760 # Number of inst fetches per cycle
298 system.cpu.decode.IdleCycles 36899359 # Number of cycles decode is idle
299 system.cpu.decode.BlockedCycles 167130004 # Number of cycles decode is blocked
300 system.cpu.decode.RunCycles 41545229 # Number of cycles decode is running
301 system.cpu.decode.UnblockCycles 10264627 # Number of cycles decode is unblocking
302 system.cpu.decode.SquashCycles 13773250 # Number of cycles decode is squashing
303 system.cpu.decode.DecodedInsts 336001462 # Number of instructions handled by decode
304 system.cpu.rename.SquashCycles 13773250 # Number of cycles rename is squashing
305 system.cpu.rename.IdleCycles 44972487 # Number of cycles rename is idle
306 system.cpu.rename.BlockCycles 116686698 # Number of cycles rename is blocking
307 system.cpu.rename.serializeStallCycles 32545 # count of cycles rename stalled for serializing inst
308 system.cpu.rename.RunCycles 42701689 # Number of cycles rename is running
309 system.cpu.rename.UnblockCycles 51445800 # Number of cycles rename is unblocking
310 system.cpu.rename.RenamedInsts 329633775 # Number of instructions processed by rename
311 system.cpu.rename.ROBFullEvents 10827 # Number of times rename has blocked due to ROB full
312 system.cpu.rename.IQFullEvents 26123597 # Number of times rename has blocked due to IQ full
313 system.cpu.rename.LSQFullEvents 22730549 # Number of times rename has blocked due to LSQ full
314 system.cpu.rename.RenamedOperands 382342090 # Number of destination operands rename has renamed
315 system.cpu.rename.RenameLookups 917586713 # Number of register rename lookups that rename has made
316 system.cpu.rename.int_rename_lookups 605878272 # Number of integer rename lookups
317 system.cpu.rename.fp_rename_lookups 4127660 # Number of floating rename lookups
318 system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed
319 system.cpu.rename.UndoneMaps 122912640 # Number of HB maps that are undone due to squashing
320 system.cpu.rename.serializingInsts 2051 # count of serializing insts renamed
321 system.cpu.rename.tempSerializingInsts 2042 # count of temporary serializing insts renamed
322 system.cpu.rename.skidInsts 105140052 # count of insts added to the skid buffer
323 system.cpu.memDep0.insertedLoads 84507276 # Number of loads inserted to the mem dependence unit.
324 system.cpu.memDep0.insertedStores 30107186 # Number of stores inserted to the mem dependence unit.
325 system.cpu.memDep0.conflictingLoads 58355212 # Number of conflicting loads.
326 system.cpu.memDep0.conflictingStores 18979888 # Number of conflicting stores.
327 system.cpu.iq.iqInstsAdded 322730905 # Number of instructions added to the IQ (excludes non-spec)
328 system.cpu.iq.iqNonSpecInstsAdded 4069 # Number of non-speculative instructions added to the IQ
329 system.cpu.iq.iqInstsIssued 260501994 # Number of instructions issued
330 system.cpu.iq.iqSquashedInstsIssued 116055 # Number of squashed instructions issued
331 system.cpu.iq.iqSquashedInstsExamined 100987191 # Number of squashed instructions iterated over during squash; mainly for profiling
332 system.cpu.iq.iqSquashedOperandsExamined 210203655 # Number of squashed operands that are examined and possibly removed from graph
333 system.cpu.iq.iqSquashedNonSpecRemoved 2824 # Number of squashed non-spec instructions that were removed
334 system.cpu.iq.issued_per_cycle::samples 269612469 # Number of insts issued each cycle
335 system.cpu.iq.issued_per_cycle::mean 0.966209 # Number of insts issued each cycle
336 system.cpu.iq.issued_per_cycle::stdev 1.343680 # Number of insts issued each cycle
337 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
338 system.cpu.iq.issued_per_cycle::0 143429912 53.20% 53.20% # Number of insts issued each cycle
339 system.cpu.iq.issued_per_cycle::1 55567346 20.61% 73.81% # Number of insts issued each cycle
340 system.cpu.iq.issued_per_cycle::2 34108148 12.65% 86.46% # Number of insts issued each cycle
341 system.cpu.iq.issued_per_cycle::3 19044980 7.06% 93.52% # Number of insts issued each cycle
342 system.cpu.iq.issued_per_cycle::4 10887634 4.04% 97.56% # Number of insts issued each cycle
343 system.cpu.iq.issued_per_cycle::5 4152283 1.54% 99.10% # Number of insts issued each cycle
344 system.cpu.iq.issued_per_cycle::6 1816697 0.67% 99.78% # Number of insts issued each cycle
345 system.cpu.iq.issued_per_cycle::7 472473 0.18% 99.95% # Number of insts issued each cycle
346 system.cpu.iq.issued_per_cycle::8 132996 0.05% 100.00% # Number of insts issued each cycle
347 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
348 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
349 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
350 system.cpu.iq.issued_per_cycle::total 269612469 # Number of insts issued each cycle
351 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
352 system.cpu.iq.fu_full::IntAlu 130605 4.82% 4.82% # attempts to use FU when none available
353 system.cpu.iq.fu_full::IntMult 0 0.00% 4.82% # attempts to use FU when none available
354 system.cpu.iq.fu_full::IntDiv 0 0.00% 4.82% # attempts to use FU when none available
355 system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.82% # attempts to use FU when none available
356 system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.82% # attempts to use FU when none available
357 system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.82% # attempts to use FU when none available
358 system.cpu.iq.fu_full::FloatMult 0 0.00% 4.82% # attempts to use FU when none available
359 system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.82% # attempts to use FU when none available
360 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.82% # attempts to use FU when none available
361 system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.82% # attempts to use FU when none available
362 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.82% # attempts to use FU when none available
363 system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.82% # attempts to use FU when none available
364 system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.82% # attempts to use FU when none available
365 system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.82% # attempts to use FU when none available
366 system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.82% # attempts to use FU when none available
367 system.cpu.iq.fu_full::SimdMult 0 0.00% 4.82% # attempts to use FU when none available
368 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.82% # attempts to use FU when none available
369 system.cpu.iq.fu_full::SimdShift 0 0.00% 4.82% # attempts to use FU when none available
370 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.82% # attempts to use FU when none available
371 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.82% # attempts to use FU when none available
372 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.82% # attempts to use FU when none available
373 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.82% # attempts to use FU when none available
374 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.82% # attempts to use FU when none available
375 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.82% # attempts to use FU when none available
376 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.82% # attempts to use FU when none available
377 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.82% # attempts to use FU when none available
378 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.82% # attempts to use FU when none available
379 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.82% # attempts to use FU when none available
380 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.82% # attempts to use FU when none available
381 system.cpu.iq.fu_full::MemRead 2279077 84.03% 88.85% # attempts to use FU when none available
382 system.cpu.iq.fu_full::MemWrite 302412 11.15% 100.00% # attempts to use FU when none available
383 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
384 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
385 system.cpu.iq.FU_type_0::No_OpClass 1210810 0.46% 0.46% # Type of FU issued
386 system.cpu.iq.FU_type_0::IntAlu 162055944 62.21% 62.67% # Type of FU issued
387 system.cpu.iq.FU_type_0::IntMult 789191 0.30% 62.98% # Type of FU issued
388 system.cpu.iq.FU_type_0::IntDiv 7035649 2.70% 65.68% # Type of FU issued
389 system.cpu.iq.FU_type_0::FloatAdd 1445882 0.56% 66.23% # Type of FU issued
390 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.23% # Type of FU issued
391 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.23% # Type of FU issued
392 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.23% # Type of FU issued
393 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.23% # Type of FU issued
394 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.23% # Type of FU issued
395 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.23% # Type of FU issued
396 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.23% # Type of FU issued
397 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.23% # Type of FU issued
398 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.23% # Type of FU issued
399 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.23% # Type of FU issued
400 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.23% # Type of FU issued
401 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.23% # Type of FU issued
402 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.23% # Type of FU issued
403 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.23% # Type of FU issued
404 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.23% # Type of FU issued
405 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.23% # Type of FU issued
406 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.23% # Type of FU issued
407 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.23% # Type of FU issued
408 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.23% # Type of FU issued
409 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.23% # Type of FU issued
410 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.23% # Type of FU issued
411 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.23% # Type of FU issued
412 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.23% # Type of FU issued
413 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.23% # Type of FU issued
414 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.23% # Type of FU issued
415 system.cpu.iq.FU_type_0::MemRead 65414513 25.11% 91.34% # Type of FU issued
416 system.cpu.iq.FU_type_0::MemWrite 22550005 8.66% 100.00% # Type of FU issued
417 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
418 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
419 system.cpu.iq.FU_type_0::total 260501994 # Type of FU issued
420 system.cpu.iq.rate 0.900699 # Inst issue rate
421 system.cpu.iq.fu_busy_cnt 2712094 # FU busy when requested
422 system.cpu.iq.fu_busy_rate 0.010411 # FU busy rate (busy events/executed inst)
423 system.cpu.iq.int_inst_queue_reads 788557578 # Number of integer instruction queue reads
424 system.cpu.iq.int_inst_queue_writes 420384868 # Number of integer instruction queue writes
425 system.cpu.iq.int_inst_queue_wakeup_accesses 255147075 # Number of integer instruction queue wakeup accesses
426 system.cpu.iq.fp_inst_queue_reads 4887028 # Number of floating instruction queue reads
427 system.cpu.iq.fp_inst_queue_writes 3615221 # Number of floating instruction queue writes
428 system.cpu.iq.fp_inst_queue_wakeup_accesses 2349564 # Number of floating instruction queue wakeup accesses
429 system.cpu.iq.int_alu_accesses 259544026 # Number of integer alu accesses
430 system.cpu.iq.fp_alu_accesses 2459252 # Number of floating point alu accesses
431 system.cpu.iew.lsq.thread0.forwLoads 18903382 # Number of loads that had data forwarded from stores
432 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
433 system.cpu.iew.lsq.thread0.squashedLoads 27857689 # Number of loads squashed
434 system.cpu.iew.lsq.thread0.ignoredResponses 25992 # Number of memory responses ignored because the instruction is squashed
435 system.cpu.iew.lsq.thread0.memOrderViolation 283319 # Number of memory ordering violations
436 system.cpu.iew.lsq.thread0.squashedStores 9591469 # Number of stores squashed
437 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
438 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
439 system.cpu.iew.lsq.thread0.rescheduledLoads 49752 # Number of loads that were rescheduled
440 system.cpu.iew.lsq.thread0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked
441 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
442 system.cpu.iew.iewSquashCycles 13773250 # Number of cycles IEW is squashing
443 system.cpu.iew.iewBlockCycles 85040639 # Number of cycles IEW is blocking
444 system.cpu.iew.iewUnblockCycles 5471570 # Number of cycles IEW is unblocking
445 system.cpu.iew.iewDispatchedInsts 322734974 # Number of instructions dispatched to IQ
446 system.cpu.iew.iewDispSquashedInsts 133239 # Number of squashed instructions skipped by dispatch
447 system.cpu.iew.iewDispLoadInsts 84507276 # Number of dispatched load instructions
448 system.cpu.iew.iewDispStoreInsts 30107186 # Number of dispatched store instructions
449 system.cpu.iew.iewDispNonSpecInsts 1979 # Number of dispatched non-speculative instructions
450 system.cpu.iew.iewIQFullEvents 2708196 # Number of times the IQ has become full, causing a stall
451 system.cpu.iew.iewLSQFullEvents 13910 # Number of times the LSQ has become full, causing a stall
452 system.cpu.iew.memOrderViolationEvents 283319 # Number of memory order violations
453 system.cpu.iew.predictedTakenIncorrect 639398 # Number of branches that were predicted taken incorrectly
454 system.cpu.iew.predictedNotTakenIncorrect 901242 # Number of branches that were predicted not taken incorrectly
455 system.cpu.iew.branchMispredicts 1540640 # Number of branch mispredicts detected at execute
456 system.cpu.iew.iewExecutedInsts 258732431 # Number of executed instructions
457 system.cpu.iew.iewExecLoadInsts 64645019 # Number of load instructions executed
458 system.cpu.iew.iewExecSquashedInsts 1769563 # Number of squashed instructions skipped in execute
459 system.cpu.iew.exec_swp 0 # number of swp insts executed
460 system.cpu.iew.exec_nop 0 # number of nop insts executed
461 system.cpu.iew.exec_refs 86992194 # number of memory reference insts executed
462 system.cpu.iew.exec_branches 14265859 # Number of branches executed
463 system.cpu.iew.exec_stores 22347175 # Number of stores executed
464 system.cpu.iew.exec_rate 0.894581 # Inst execution rate
465 system.cpu.iew.wb_sent 258096693 # cumulative count of insts sent to commit
466 system.cpu.iew.wb_count 257496639 # cumulative count of insts written-back
467 system.cpu.iew.wb_producers 205928299 # num instructions producing a value
468 system.cpu.iew.wb_consumers 369130530 # num instructions consuming a value
469 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
470 system.cpu.iew.wb_rate 0.890308 # insts written-back per cycle
471 system.cpu.iew.wb_fanout 0.557874 # average fanout of values written-back
472 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
473 system.cpu.commit.commitSquashedInsts 101448840 # The number of squashed insts skipped by commit
474 system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards
475 system.cpu.commit.branchMispredicts 1491529 # The number of times a branch was mispredicted
476 system.cpu.commit.committed_per_cycle::samples 255839219 # Number of insts commited each cycle
477 system.cpu.commit.committed_per_cycle::mean 0.865244 # Number of insts commited each cycle
478 system.cpu.commit.committed_per_cycle::stdev 1.654327 # Number of insts commited each cycle
479 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
480 system.cpu.commit.committed_per_cycle::0 156486617 61.17% 61.17% # Number of insts commited each cycle
481 system.cpu.commit.committed_per_cycle::1 57197635 22.36% 83.52% # Number of insts commited each cycle
482 system.cpu.commit.committed_per_cycle::2 14067876 5.50% 89.02% # Number of insts commited each cycle
483 system.cpu.commit.committed_per_cycle::3 12054068 4.71% 93.73% # Number of insts commited each cycle
484 system.cpu.commit.committed_per_cycle::4 4176261 1.63% 95.37% # Number of insts commited each cycle
485 system.cpu.commit.committed_per_cycle::5 2944387 1.15% 96.52% # Number of insts commited each cycle
486 system.cpu.commit.committed_per_cycle::6 904564 0.35% 96.87% # Number of insts commited each cycle
487 system.cpu.commit.committed_per_cycle::7 1049058 0.41% 97.28% # Number of insts commited each cycle
488 system.cpu.commit.committed_per_cycle::8 6958753 2.72% 100.00% # Number of insts commited each cycle
489 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
490 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
491 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
492 system.cpu.commit.committed_per_cycle::total 255839219 # Number of insts commited each cycle
493 system.cpu.commit.committedInsts 132071192 # Number of instructions committed
494 system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed
495 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
496 system.cpu.commit.refs 77165304 # Number of memory references committed
497 system.cpu.commit.loads 56649587 # Number of loads committed
498 system.cpu.commit.membars 0 # Number of memory barriers committed
499 system.cpu.commit.branches 12326938 # Number of branches committed
500 system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions.
501 system.cpu.commit.int_insts 219019985 # Number of committed integer instructions.
502 system.cpu.commit.function_calls 797818 # Number of function calls committed.
503 system.cpu.commit.bw_lim_events 6958753 # number cycles where commit BW limit reached
504 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
505 system.cpu.rob.rob_reads 571692690 # The number of ROB reads
506 system.cpu.rob.rob_writes 659422914 # The number of ROB writes
507 system.cpu.timesIdled 5933064 # Number of times that the entire CPU went into an idle state and unscheduled itself
508 system.cpu.idleCycles 19609404 # Total number of cycles that the CPU has spent unscheduled due to idling
509 system.cpu.committedInsts 132071192 # Number of Instructions Simulated
510 system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated
511 system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated
512 system.cpu.cpi 2.189894 # CPI: Cycles Per Instruction
513 system.cpu.cpi_total 2.189894 # CPI: Total CPI of All Threads
514 system.cpu.ipc 0.456643 # IPC: Instructions Per Cycle
515 system.cpu.ipc_total 0.456643 # IPC: Total IPC of All Threads
516 system.cpu.int_regfile_reads 451224153 # number of integer regfile reads
517 system.cpu.int_regfile_writes 233957254 # number of integer regfile writes
518 system.cpu.fp_regfile_reads 3215586 # number of floating regfile reads
519 system.cpu.fp_regfile_writes 2009211 # number of floating regfile writes
520 system.cpu.cc_regfile_reads 102809513 # number of cc regfile reads
521 system.cpu.cc_regfile_writes 59799383 # number of cc regfile writes
522 system.cpu.misc_regfile_reads 133324417 # number of misc regfile reads
523 system.cpu.misc_regfile_writes 1689 # number of misc regfile writes
524 system.cpu.toL2Bus.throughput 3898568 # Throughput (bytes/s)
525 system.cpu.toL2Bus.trans_dist::ReadReq 7250 # Transaction distribution
526 system.cpu.toL2Bus.trans_dist::ReadResp 7248 # Transaction distribution
527 system.cpu.toL2Bus.trans_dist::Writeback 13 # Transaction distribution
528 system.cpu.toL2Bus.trans_dist::UpgradeReq 163 # Transaction distribution
529 system.cpu.toL2Bus.trans_dist::UpgradeResp 163 # Transaction distribution
530 system.cpu.toL2Bus.trans_dist::ReadExReq 1539 # Transaction distribution
531 system.cpu.toL2Bus.trans_dist::ReadExResp 1539 # Transaction distribution
532 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13403 # Packet count per connected master and slave (bytes)
533 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4348 # Packet count per connected master and slave (bytes)
534 system.cpu.toL2Bus.pkt_count::total 17751 # Packet count per connected master and slave (bytes)
535 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 423616 # Cumulative packet size per connected master and slave (bytes)
536 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 129088 # Cumulative packet size per connected master and slave (bytes)
537 system.cpu.toL2Bus.tot_pkt_size::total 552704 # Cumulative packet size per connected master and slave (bytes)
538 system.cpu.toL2Bus.data_through_bus 552704 # Total data (bytes)
539 system.cpu.toL2Bus.snoop_data_through_bus 10496 # Total snoop data (bytes)
540 system.cpu.toL2Bus.reqLayer0.occupancy 4495500 # Layer occupancy (ticks)
541 system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
542 system.cpu.toL2Bus.respLayer0.occupancy 10760250 # Layer occupancy (ticks)
543 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
544 system.cpu.toL2Bus.respLayer1.occupancy 3467413 # Layer occupancy (ticks)
545 system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
546 system.cpu.icache.tags.replacements 4653 # number of replacements
547 system.cpu.icache.tags.tagsinuse 1619.938452 # Cycle average of tags in use
548 system.cpu.icache.tags.total_refs 22344300 # Total number of references to valid blocks.
549 system.cpu.icache.tags.sampled_refs 6620 # Sample count of references to valid blocks.
550 system.cpu.icache.tags.avg_refs 3375.271903 # Average number of references to valid blocks.
551 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
552 system.cpu.icache.tags.occ_blocks::cpu.inst 1619.938452 # Average occupied blocks per requestor
553 system.cpu.icache.tags.occ_percent::cpu.inst 0.790986 # Average percentage of cache occupancy
554 system.cpu.icache.tags.occ_percent::total 0.790986 # Average percentage of cache occupancy
555 system.cpu.icache.ReadReq_hits::cpu.inst 22344300 # number of ReadReq hits
556 system.cpu.icache.ReadReq_hits::total 22344300 # number of ReadReq hits
557 system.cpu.icache.demand_hits::cpu.inst 22344300 # number of demand (read+write) hits
558 system.cpu.icache.demand_hits::total 22344300 # number of demand (read+write) hits
559 system.cpu.icache.overall_hits::cpu.inst 22344300 # number of overall hits
560 system.cpu.icache.overall_hits::total 22344300 # number of overall hits
561 system.cpu.icache.ReadReq_misses::cpu.inst 8910 # number of ReadReq misses
562 system.cpu.icache.ReadReq_misses::total 8910 # number of ReadReq misses
563 system.cpu.icache.demand_misses::cpu.inst 8910 # number of demand (read+write) misses
564 system.cpu.icache.demand_misses::total 8910 # number of demand (read+write) misses
565 system.cpu.icache.overall_misses::cpu.inst 8910 # number of overall misses
566 system.cpu.icache.overall_misses::total 8910 # number of overall misses
567 system.cpu.icache.ReadReq_miss_latency::cpu.inst 368144999 # number of ReadReq miss cycles
568 system.cpu.icache.ReadReq_miss_latency::total 368144999 # number of ReadReq miss cycles
569 system.cpu.icache.demand_miss_latency::cpu.inst 368144999 # number of demand (read+write) miss cycles
570 system.cpu.icache.demand_miss_latency::total 368144999 # number of demand (read+write) miss cycles
571 system.cpu.icache.overall_miss_latency::cpu.inst 368144999 # number of overall miss cycles
572 system.cpu.icache.overall_miss_latency::total 368144999 # number of overall miss cycles
573 system.cpu.icache.ReadReq_accesses::cpu.inst 22353210 # number of ReadReq accesses(hits+misses)
574 system.cpu.icache.ReadReq_accesses::total 22353210 # number of ReadReq accesses(hits+misses)
575 system.cpu.icache.demand_accesses::cpu.inst 22353210 # number of demand (read+write) accesses
576 system.cpu.icache.demand_accesses::total 22353210 # number of demand (read+write) accesses
577 system.cpu.icache.overall_accesses::cpu.inst 22353210 # number of overall (read+write) accesses
578 system.cpu.icache.overall_accesses::total 22353210 # number of overall (read+write) accesses
579 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000399 # miss rate for ReadReq accesses
580 system.cpu.icache.ReadReq_miss_rate::total 0.000399 # miss rate for ReadReq accesses
581 system.cpu.icache.demand_miss_rate::cpu.inst 0.000399 # miss rate for demand accesses
582 system.cpu.icache.demand_miss_rate::total 0.000399 # miss rate for demand accesses
583 system.cpu.icache.overall_miss_rate::cpu.inst 0.000399 # miss rate for overall accesses
584 system.cpu.icache.overall_miss_rate::total 0.000399 # miss rate for overall accesses
585 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41318.181706 # average ReadReq miss latency
586 system.cpu.icache.ReadReq_avg_miss_latency::total 41318.181706 # average ReadReq miss latency
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588 system.cpu.icache.demand_avg_miss_latency::total 41318.181706 # average overall miss latency
589 system.cpu.icache.overall_avg_miss_latency::cpu.inst 41318.181706 # average overall miss latency
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593 system.cpu.icache.blocked::no_mshrs 20 # number of cycles access was blocked
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606 system.cpu.icache.ReadReq_mshr_misses::total 6784 # number of ReadReq MSHR misses
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615 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 271638749 # number of overall MSHR miss cycles
616 system.cpu.icache.overall_mshr_miss_latency::total 271638749 # number of overall MSHR miss cycles
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618 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000303 # mshr miss rate for ReadReq accesses
619 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for demand accesses
620 system.cpu.icache.demand_mshr_miss_rate::total 0.000303 # mshr miss rate for demand accesses
621 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for overall accesses
622 system.cpu.icache.overall_mshr_miss_rate::total 0.000303 # mshr miss rate for overall accesses
623 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40041.089180 # average ReadReq mshr miss latency
624 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40041.089180 # average ReadReq mshr miss latency
625 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40041.089180 # average overall mshr miss latency
626 system.cpu.icache.demand_avg_mshr_miss_latency::total 40041.089180 # average overall mshr miss latency
627 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40041.089180 # average overall mshr miss latency
628 system.cpu.icache.overall_avg_mshr_miss_latency::total 40041.089180 # average overall mshr miss latency
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632 system.cpu.l2cache.tags.total_refs 3266 # Total number of references to valid blocks.
633 system.cpu.l2cache.tags.sampled_refs 3826 # Sample count of references to valid blocks.
634 system.cpu.l2cache.tags.avg_refs 0.853633 # Average number of references to valid blocks.
635 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
636 system.cpu.l2cache.tags.occ_blocks::writebacks 1.725256 # Average occupied blocks per requestor
637 system.cpu.l2cache.tags.occ_blocks::cpu.inst 2230.334814 # Average occupied blocks per requestor
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647 system.cpu.l2cache.Writeback_hits::total 13 # number of Writeback hits
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660 system.cpu.l2cache.UpgradeReq_misses::total 163 # number of UpgradeReq misses
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683 system.cpu.l2cache.Writeback_accesses::writebacks 13 # number of Writeback accesses(hits+misses)
684 system.cpu.l2cache.Writeback_accesses::total 13 # number of Writeback accesses(hits+misses)
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709 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76175.581395 # average ReadReq miss latency
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712 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68168.407311 # average ReadExReq miss latency
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716 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68498.968464 # average overall miss latency
717 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69923.292559 # average overall miss latency
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720 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
721 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
722 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
723 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
724 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
725 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
726 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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728 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 430 # number of ReadReq MSHR misses
729 system.cpu.l2cache.ReadReq_mshr_misses::total 3823 # number of ReadReq MSHR misses
730 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 163 # number of UpgradeReq MSHR misses
731 system.cpu.l2cache.UpgradeReq_mshr_misses::total 163 # number of UpgradeReq MSHR misses
732 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1532 # number of ReadExReq MSHR misses
733 system.cpu.l2cache.ReadExReq_mshr_misses::total 1532 # number of ReadExReq MSHR misses
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738 system.cpu.l2cache.overall_mshr_misses::cpu.data 1962 # number of overall MSHR misses
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743 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1630163 # number of UpgradeReq MSHR miss cycles
744 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1630163 # number of UpgradeReq MSHR miss cycles
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754 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.922747 # mshr miss rate for ReadReq accesses
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756 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
757 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
758 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995452 # mshr miss rate for ReadExReq accesses
759 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995452 # mshr miss rate for ReadExReq accesses
760 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.512538 # mshr miss rate for demand accesses
761 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.978554 # mshr miss rate for demand accesses
762 system.cpu.l2cache.demand_mshr_miss_rate::total 0.620870 # mshr miss rate for demand accesses
763 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.512538 # mshr miss rate for overall accesses
764 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.978554 # mshr miss rate for overall accesses
765 system.cpu.l2cache.overall_mshr_miss_rate::total 0.620870 # mshr miss rate for overall accesses
766 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55968.022399 # average ReadReq mshr miss latency
767 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63782.558140 # average ReadReq mshr miss latency
768 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56846.978812 # average ReadReq mshr miss latency
769 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
770 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
771 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55400.783290 # average ReadExReq mshr miss latency
772 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55400.783290 # average ReadExReq mshr miss latency
773 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55968.022399 # average overall mshr miss latency
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777 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57237.767584 # average overall mshr miss latency
778 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56433.239963 # average overall mshr miss latency
779 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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781 system.cpu.dcache.tags.tagsinuse 1438.861304 # Cycle average of tags in use
782 system.cpu.dcache.tags.total_refs 66102356 # Total number of references to valid blocks.
783 system.cpu.dcache.tags.sampled_refs 2004 # Sample count of references to valid blocks.
784 system.cpu.dcache.tags.avg_refs 32985.207585 # Average number of references to valid blocks.
785 system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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804 system.cpu.dcache.overall_misses::total 2637 # number of overall misses
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830 system.cpu.dcache.ReadReq_avg_miss_latency::total 67126.809626 # average ReadReq miss latency
831 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66925.477673 # average WriteReq miss latency
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833 system.cpu.dcache.demand_avg_miss_latency::cpu.data 66996.863860 # average overall miss latency
834 system.cpu.dcache.demand_avg_miss_latency::total 66996.863860 # average overall miss latency
835 system.cpu.dcache.overall_avg_miss_latency::cpu.data 66996.863860 # average overall miss latency
836 system.cpu.dcache.overall_avg_miss_latency::total 66996.863860 # average overall miss latency
837 system.cpu.dcache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked
838 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
839 system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked
840 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
841 system.cpu.dcache.avg_blocked_cycles::no_mshrs 77 # average number of cycles each access was blocked
842 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
843 system.cpu.dcache.fast_writes 0 # number of fast writes performed
844 system.cpu.dcache.cache_copies 0 # number of cache copies performed
845 system.cpu.dcache.writebacks::writebacks 13 # number of writebacks
846 system.cpu.dcache.writebacks::total 13 # number of writebacks
847 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 468 # number of ReadReq MSHR hits
848 system.cpu.dcache.ReadReq_mshr_hits::total 468 # number of ReadReq MSHR hits
849 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1 # number of WriteReq MSHR hits
850 system.cpu.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits
851 system.cpu.dcache.demand_mshr_hits::cpu.data 469 # number of demand (read+write) MSHR hits
852 system.cpu.dcache.demand_mshr_hits::total 469 # number of demand (read+write) MSHR hits
853 system.cpu.dcache.overall_mshr_hits::cpu.data 469 # number of overall MSHR hits
854 system.cpu.dcache.overall_mshr_hits::total 469 # number of overall MSHR hits
855 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 467 # number of ReadReq MSHR misses
856 system.cpu.dcache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses
857 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1701 # number of WriteReq MSHR misses
858 system.cpu.dcache.WriteReq_mshr_misses::total 1701 # number of WriteReq MSHR misses
859 system.cpu.dcache.demand_mshr_misses::cpu.data 2168 # number of demand (read+write) MSHR misses
860 system.cpu.dcache.demand_mshr_misses::total 2168 # number of demand (read+write) MSHR misses
861 system.cpu.dcache.overall_mshr_misses::cpu.data 2168 # number of overall MSHR misses
862 system.cpu.dcache.overall_mshr_misses::total 2168 # number of overall MSHR misses
863 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33590500 # number of ReadReq MSHR miss cycles
864 system.cpu.dcache.ReadReq_mshr_miss_latency::total 33590500 # number of ReadReq MSHR miss cycles
865 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 109769587 # number of WriteReq MSHR miss cycles
866 system.cpu.dcache.WriteReq_mshr_miss_latency::total 109769587 # number of WriteReq MSHR miss cycles
867 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 143360087 # number of demand (read+write) MSHR miss cycles
868 system.cpu.dcache.demand_mshr_miss_latency::total 143360087 # number of demand (read+write) MSHR miss cycles
869 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 143360087 # number of overall MSHR miss cycles
870 system.cpu.dcache.overall_mshr_miss_latency::total 143360087 # number of overall MSHR miss cycles
871 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
872 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
873 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000083 # mshr miss rate for WriteReq accesses
874 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000083 # mshr miss rate for WriteReq accesses
875 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000033 # mshr miss rate for demand accesses
876 system.cpu.dcache.demand_mshr_miss_rate::total 0.000033 # mshr miss rate for demand accesses
877 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000033 # mshr miss rate for overall accesses
878 system.cpu.dcache.overall_mshr_miss_rate::total 0.000033 # mshr miss rate for overall accesses
879 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71928.265525 # average ReadReq mshr miss latency
880 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71928.265525 # average ReadReq mshr miss latency
881 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64532.385068 # average WriteReq mshr miss latency
882 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64532.385068 # average WriteReq mshr miss latency
883 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66125.501384 # average overall mshr miss latency
884 system.cpu.dcache.demand_avg_mshr_miss_latency::total 66125.501384 # average overall mshr miss latency
885 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66125.501384 # average overall mshr miss latency
886 system.cpu.dcache.overall_avg_mshr_miss_latency::total 66125.501384 # average overall mshr miss latency
887 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
889 ---------- End Simulation Statistics ----------
projects / gem5.git / blob