2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.148669 # Number of seconds simulated
4 sim_ticks 148668850500 # Number of ticks simulated
5 final_tick 148668850500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 82634 # Simulator instruction rate (inst/s)
8 host_op_rate 138502 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 93018548 # Simulator tick rate (ticks/s)
10 host_mem_usage 346916 # Number of bytes of host memory used
11 host_seconds 1598.27 # Real time elapsed on the host
12 sim_insts 132071192 # Number of instructions simulated
13 sim_ops 221363384 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 225344 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 125504 # Number of bytes read from this memory
18 system.physmem.bytes_read::total 350848 # Number of bytes read from this memory
19 system.physmem.bytes_inst_read::cpu.inst 225344 # Number of instructions bytes read from this memory
20 system.physmem.bytes_inst_read::total 225344 # Number of instructions bytes read from this memory
21 system.physmem.num_reads::cpu.inst 3521 # Number of read requests responded to by this memory
22 system.physmem.num_reads::cpu.data 1961 # Number of read requests responded to by this memory
23 system.physmem.num_reads::total 5482 # Number of read requests responded to by this memory
24 system.physmem.bw_read::cpu.inst 1515745 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_read::cpu.data 844185 # Total read bandwidth from this memory (bytes/s)
26 system.physmem.bw_read::total 2359929 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_inst_read::cpu.inst 1515745 # Instruction read bandwidth from this memory (bytes/s)
28 system.physmem.bw_inst_read::total 1515745 # Instruction read bandwidth from this memory (bytes/s)
29 system.physmem.bw_total::cpu.inst 1515745 # Total bandwidth to/from this memory (bytes/s)
30 system.physmem.bw_total::cpu.data 844185 # Total bandwidth to/from this memory (bytes/s)
31 system.physmem.bw_total::total 2359929 # Total bandwidth to/from this memory (bytes/s)
32 system.physmem.readReqs 5482 # Number of read requests accepted
33 system.physmem.writeReqs 0 # Number of write requests accepted
34 system.physmem.readBursts 5482 # Number of DRAM read bursts, including those serviced by the write queue
35 system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
36 system.physmem.bytesReadDRAM 350848 # Total number of bytes read from DRAM
37 system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
38 system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
39 system.physmem.bytesReadSys 350848 # Total read bytes from the system interface side
40 system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
41 system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
42 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
43 system.physmem.neitherReadNorWriteReqs 345 # Number of requests that are neither read nor write
44 system.physmem.perBankRdBursts::0 294 # Per bank write bursts
45 system.physmem.perBankRdBursts::1 364 # Per bank write bursts
46 system.physmem.perBankRdBursts::2 457 # Per bank write bursts
47 system.physmem.perBankRdBursts::3 371 # Per bank write bursts
48 system.physmem.perBankRdBursts::4 339 # Per bank write bursts
49 system.physmem.perBankRdBursts::5 333 # Per bank write bursts
50 system.physmem.perBankRdBursts::6 398 # Per bank write bursts
51 system.physmem.perBankRdBursts::7 383 # Per bank write bursts
52 system.physmem.perBankRdBursts::8 344 # Per bank write bursts
53 system.physmem.perBankRdBursts::9 280 # Per bank write bursts
54 system.physmem.perBankRdBursts::10 239 # Per bank write bursts
55 system.physmem.perBankRdBursts::11 268 # Per bank write bursts
56 system.physmem.perBankRdBursts::12 225 # Per bank write bursts
57 system.physmem.perBankRdBursts::13 502 # Per bank write bursts
58 system.physmem.perBankRdBursts::14 395 # Per bank write bursts
59 system.physmem.perBankRdBursts::15 290 # Per bank write bursts
60 system.physmem.perBankWrBursts::0 0 # Per bank write bursts
61 system.physmem.perBankWrBursts::1 0 # Per bank write bursts
62 system.physmem.perBankWrBursts::2 0 # Per bank write bursts
63 system.physmem.perBankWrBursts::3 0 # Per bank write bursts
64 system.physmem.perBankWrBursts::4 0 # Per bank write bursts
65 system.physmem.perBankWrBursts::5 0 # Per bank write bursts
66 system.physmem.perBankWrBursts::6 0 # Per bank write bursts
67 system.physmem.perBankWrBursts::7 0 # Per bank write bursts
68 system.physmem.perBankWrBursts::8 0 # Per bank write bursts
69 system.physmem.perBankWrBursts::9 0 # Per bank write bursts
70 system.physmem.perBankWrBursts::10 0 # Per bank write bursts
71 system.physmem.perBankWrBursts::11 0 # Per bank write bursts
72 system.physmem.perBankWrBursts::12 0 # Per bank write bursts
73 system.physmem.perBankWrBursts::13 0 # Per bank write bursts
74 system.physmem.perBankWrBursts::14 0 # Per bank write bursts
75 system.physmem.perBankWrBursts::15 0 # Per bank write bursts
76 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
77 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
78 system.physmem.totGap 148668756000 # Total gap between requests
79 system.physmem.readPktSize::0 0 # Read request sizes (log2)
80 system.physmem.readPktSize::1 0 # Read request sizes (log2)
81 system.physmem.readPktSize::2 0 # Read request sizes (log2)
82 system.physmem.readPktSize::3 0 # Read request sizes (log2)
83 system.physmem.readPktSize::4 0 # Read request sizes (log2)
84 system.physmem.readPktSize::5 0 # Read request sizes (log2)
85 system.physmem.readPktSize::6 5482 # Read request sizes (log2)
86 system.physmem.writePktSize::0 0 # Write request sizes (log2)
87 system.physmem.writePktSize::1 0 # Write request sizes (log2)
88 system.physmem.writePktSize::2 0 # Write request sizes (log2)
89 system.physmem.writePktSize::3 0 # Write request sizes (log2)
90 system.physmem.writePktSize::4 0 # Write request sizes (log2)
91 system.physmem.writePktSize::5 0 # Write request sizes (log2)
92 system.physmem.writePktSize::6 0 # Write request sizes (log2)
93 system.physmem.rdQLenPdf::0 4368 # What read queue length does an incoming req see
94 system.physmem.rdQLenPdf::1 913 # What read queue length does an incoming req see
95 system.physmem.rdQLenPdf::2 173 # What read queue length does an incoming req see
96 system.physmem.rdQLenPdf::3 24 # What read queue length does an incoming req see
97 system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
98 system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
99 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
100 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
125 system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
126 system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
127 system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
128 system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
129 system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
130 system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
131 system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
132 system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
189 system.physmem.bytesPerActivate::samples 1140 # Bytes accessed per row activation
190 system.physmem.bytesPerActivate::mean 306.470175 # Bytes accessed per row activation
191 system.physmem.bytesPerActivate::gmean 178.641766 # Bytes accessed per row activation
192 system.physmem.bytesPerActivate::stdev 326.557853 # Bytes accessed per row activation
193 system.physmem.bytesPerActivate::0-127 448 39.30% 39.30% # Bytes accessed per row activation
194 system.physmem.bytesPerActivate::128-255 255 22.37% 61.67% # Bytes accessed per row activation
195 system.physmem.bytesPerActivate::256-383 105 9.21% 70.88% # Bytes accessed per row activation
196 system.physmem.bytesPerActivate::384-511 70 6.14% 77.02% # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::512-639 38 3.33% 80.35% # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::640-767 59 5.18% 85.53% # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::768-895 19 1.67% 87.19% # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::896-1023 18 1.58% 88.77% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::1024-1151 128 11.23% 100.00% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::total 1140 # Bytes accessed per row activation
203 system.physmem.totQLat 40930250 # Total ticks spent queuing
204 system.physmem.totMemAccLat 143717750 # Total ticks spent from burst creation until serviced by the DRAM
205 system.physmem.totBusLat 27410000 # Total ticks spent in databus transfers
206 system.physmem.avgQLat 7466.30 # Average queueing delay per DRAM burst
207 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
208 system.physmem.avgMemAccLat 26216.30 # Average memory access latency per DRAM burst
209 system.physmem.avgRdBW 2.36 # Average DRAM read bandwidth in MiByte/s
210 system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
211 system.physmem.avgRdBWSys 2.36 # Average system read bandwidth in MiByte/s
212 system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
213 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
214 system.physmem.busUtil 0.02 # Data bus utilization in percentage
215 system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
216 system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
217 system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing
218 system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
219 system.physmem.readRowHits 4334 # Number of row buffer hits during reads
220 system.physmem.writeRowHits 0 # Number of row buffer hits during writes
221 system.physmem.readRowHitRate 79.06 # Row buffer hit rate for reads
222 system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
223 system.physmem.avgGap 27119437.43 # Average gap between requests
224 system.physmem.pageHitRate 79.06 # Row buffer hit rate, read and write combined
225 system.physmem_0.actEnergy 5027400 # Energy for activate commands per rank (pJ)
226 system.physmem_0.preEnergy 2743125 # Energy for precharge commands per rank (pJ)
227 system.physmem_0.readEnergy 22776000 # Energy for read commands per rank (pJ)
228 system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
229 system.physmem_0.refreshEnergy 9709936080 # Energy for refresh commands per rank (pJ)
230 system.physmem_0.actBackEnergy 4021675470 # Energy for active background per rank (pJ)
231 system.physmem_0.preBackEnergy 85670093250 # Energy for precharge background per rank (pJ)
232 system.physmem_0.totalEnergy 99432251325 # Total energy per rank (pJ)
233 system.physmem_0.averagePower 668.842708 # Core power per rank (mW)
234 system.physmem_0.memoryStateTime::IDLE 142518159000 # Time in different power states
235 system.physmem_0.memoryStateTime::REF 4964180000 # Time in different power states
236 system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
237 system.physmem_0.memoryStateTime::ACT 1181750000 # Time in different power states
238 system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
239 system.physmem_1.actEnergy 3568320 # Energy for activate commands per rank (pJ)
240 system.physmem_1.preEnergy 1947000 # Energy for precharge commands per rank (pJ)
241 system.physmem_1.readEnergy 19648200 # Energy for read commands per rank (pJ)
242 system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
243 system.physmem_1.refreshEnergy 9709936080 # Energy for refresh commands per rank (pJ)
244 system.physmem_1.actBackEnergy 3821631120 # Energy for active background per rank (pJ)
245 system.physmem_1.preBackEnergy 85845562500 # Energy for precharge background per rank (pJ)
246 system.physmem_1.totalEnergy 99402293220 # Total energy per rank (pJ)
247 system.physmem_1.averagePower 668.641253 # Core power per rank (mW)
248 system.physmem_1.memoryStateTime::IDLE 142814554750 # Time in different power states
249 system.physmem_1.memoryStateTime::REF 4964180000 # Time in different power states
250 system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
251 system.physmem_1.memoryStateTime::ACT 888260750 # Time in different power states
252 system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
253 system.cpu.branchPred.lookups 22385702 # Number of BP lookups
254 system.cpu.branchPred.condPredicted 22385702 # Number of conditional branches predicted
255 system.cpu.branchPred.condIncorrect 1554139 # Number of conditional branches incorrect
256 system.cpu.branchPred.BTBLookups 14132286 # Number of BTB lookups
257 system.cpu.branchPred.BTBHits 13246709 # Number of BTB hits
258 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
259 system.cpu.branchPred.BTBHitPct 93.733661 # BTB Hit Percentage
260 system.cpu.branchPred.usedRAS 1526841 # Number of times the RAS was used to get a target.
261 system.cpu.branchPred.RASInCorrect 22095 # Number of incorrect RAS predictions.
262 system.cpu_clk_domain.clock 500 # Clock period in ticks
263 system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
264 system.cpu.workload.num_syscalls 400 # Number of system calls
265 system.cpu.numCycles 297337717 # number of cpu cycles simulated
266 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
267 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
268 system.cpu.fetch.icacheStallCycles 27888104 # Number of cycles fetch is stalled on an Icache miss
269 system.cpu.fetch.Insts 249064218 # Number of instructions fetch has processed
270 system.cpu.fetch.Branches 22385702 # Number of branches that fetch encountered
271 system.cpu.fetch.predictedBranches 14773550 # Number of branches that fetch has predicted taken
272 system.cpu.fetch.Cycles 267343346 # Number of cycles fetch has run and was not squashing or blocked
273 system.cpu.fetch.SquashCycles 3703385 # Number of cycles fetch has spent squashing
274 system.cpu.fetch.TlbCycles 34 # Number of cycles fetch has spent waiting for tlb
275 system.cpu.fetch.MiscStallCycles 5713 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
276 system.cpu.fetch.PendingTrapStallCycles 48972 # Number of stall cycles due to pending traps
277 system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions
278 system.cpu.fetch.IcacheWaitRetryStallCycles 83 # Number of stall cycles due to full MSHR
279 system.cpu.fetch.CacheLines 26656558 # Number of cache lines fetched
280 system.cpu.fetch.IcacheSquashes 259176 # Number of outstanding Icache misses that were squashed
281 system.cpu.fetch.rateDist::samples 297137957 # Number of instructions fetched each cycle (Total)
282 system.cpu.fetch.rateDist::mean 1.382061 # Number of instructions fetched each cycle (Total)
283 system.cpu.fetch.rateDist::stdev 2.790607 # Number of instructions fetched each cycle (Total)
284 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
285 system.cpu.fetch.rateDist::0 229077480 77.09% 77.09% # Number of instructions fetched each cycle (Total)
286 system.cpu.fetch.rateDist::1 5080600 1.71% 78.80% # Number of instructions fetched each cycle (Total)
287 system.cpu.fetch.rateDist::2 4128062 1.39% 80.19% # Number of instructions fetched each cycle (Total)
288 system.cpu.fetch.rateDist::3 4791015 1.61% 81.81% # Number of instructions fetched each cycle (Total)
289 system.cpu.fetch.rateDist::4 4884919 1.64% 83.45% # Number of instructions fetched each cycle (Total)
290 system.cpu.fetch.rateDist::5 5103681 1.72% 85.17% # Number of instructions fetched each cycle (Total)
291 system.cpu.fetch.rateDist::6 5337561 1.80% 86.96% # Number of instructions fetched each cycle (Total)
292 system.cpu.fetch.rateDist::7 4007445 1.35% 88.31% # Number of instructions fetched each cycle (Total)
293 system.cpu.fetch.rateDist::8 34727194 11.69% 100.00% # Number of instructions fetched each cycle (Total)
294 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
295 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
296 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
297 system.cpu.fetch.rateDist::total 297137957 # Number of instructions fetched each cycle (Total)
298 system.cpu.fetch.branchRate 0.075287 # Number of branch fetches per cycle
299 system.cpu.fetch.rate 0.837648 # Number of inst fetches per cycle
300 system.cpu.decode.IdleCycles 16350382 # Number of cycles decode is idle
301 system.cpu.decode.BlockedCycles 230944995 # Number of cycles decode is blocked
302 system.cpu.decode.RunCycles 26142980 # Number of cycles decode is running
303 system.cpu.decode.UnblockCycles 21847908 # Number of cycles decode is unblocking
304 system.cpu.decode.SquashCycles 1851692 # Number of cycles decode is squashing
305 system.cpu.decode.DecodedInsts 359376016 # Number of instructions handled by decode
306 system.cpu.rename.SquashCycles 1851692 # Number of cycles rename is squashing
307 system.cpu.rename.IdleCycles 24144395 # Number of cycles rename is idle
308 system.cpu.rename.BlockCycles 162574126 # Number of cycles rename is blocking
309 system.cpu.rename.serializeStallCycles 34810 # count of cycles rename stalled for serializing inst
310 system.cpu.rename.RunCycles 38280834 # Number of cycles rename is running
311 system.cpu.rename.UnblockCycles 70252100 # Number of cycles rename is unblocking
312 system.cpu.rename.RenamedInsts 350628030 # Number of instructions processed by rename
313 system.cpu.rename.ROBFullEvents 42505 # Number of times rename has blocked due to ROB full
314 system.cpu.rename.IQFullEvents 62013521 # Number of times rename has blocked due to IQ full
315 system.cpu.rename.LQFullEvents 7956456 # Number of times rename has blocked due to LQ full
316 system.cpu.rename.SQFullEvents 170486 # Number of times rename has blocked due to SQ full
317 system.cpu.rename.RenamedOperands 405834886 # Number of destination operands rename has renamed
318 system.cpu.rename.RenameLookups 972854229 # Number of register rename lookups that rename has made
319 system.cpu.rename.int_rename_lookups 642281329 # Number of integer rename lookups
320 system.cpu.rename.fp_rename_lookups 4678301 # Number of floating rename lookups
321 system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed
322 system.cpu.rename.UndoneMaps 146405436 # Number of HB maps that are undone due to squashing
323 system.cpu.rename.serializingInsts 2386 # count of serializing insts renamed
324 system.cpu.rename.tempSerializingInsts 2313 # count of temporary serializing insts renamed
325 system.cpu.rename.skidInsts 128573116 # count of insts added to the skid buffer
326 system.cpu.memDep0.insertedLoads 89639956 # Number of loads inserted to the mem dependence unit.
327 system.cpu.memDep0.insertedStores 32032649 # Number of stores inserted to the mem dependence unit.
328 system.cpu.memDep0.conflictingLoads 63973866 # Number of conflicting loads.
329 system.cpu.memDep0.conflictingStores 21576036 # Number of conflicting stores.
330 system.cpu.iq.iqInstsAdded 341334735 # Number of instructions added to the IQ (excludes non-spec)
331 system.cpu.iq.iqNonSpecInstsAdded 4899 # Number of non-speculative instructions added to the IQ
332 system.cpu.iq.iqInstsIssued 266857181 # Number of instructions issued
333 system.cpu.iq.iqSquashedInstsIssued 74594 # Number of squashed instructions issued
334 system.cpu.iq.iqSquashedInstsExamined 119571219 # Number of squashed instructions iterated over during squash; mainly for profiling
335 system.cpu.iq.iqSquashedOperandsExamined 250511173 # Number of squashed operands that are examined and possibly removed from graph
336 system.cpu.iq.iqSquashedNonSpecRemoved 3654 # Number of squashed non-spec instructions that were removed
337 system.cpu.iq.issued_per_cycle::samples 297137957 # Number of insts issued each cycle
338 system.cpu.iq.issued_per_cycle::mean 0.898092 # Number of insts issued each cycle
339 system.cpu.iq.issued_per_cycle::stdev 1.364162 # Number of insts issued each cycle
340 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
341 system.cpu.iq.issued_per_cycle::0 171399069 57.68% 57.68% # Number of insts issued each cycle
342 system.cpu.iq.issued_per_cycle::1 54278133 18.27% 75.95% # Number of insts issued each cycle
343 system.cpu.iq.issued_per_cycle::2 33575860 11.30% 87.25% # Number of insts issued each cycle
344 system.cpu.iq.issued_per_cycle::3 19165859 6.45% 93.70% # Number of insts issued each cycle
345 system.cpu.iq.issued_per_cycle::4 10861721 3.66% 97.36% # Number of insts issued each cycle
346 system.cpu.iq.issued_per_cycle::5 4344660 1.46% 98.82% # Number of insts issued each cycle
347 system.cpu.iq.issued_per_cycle::6 2227090 0.75% 99.57% # Number of insts issued each cycle
348 system.cpu.iq.issued_per_cycle::7 887493 0.30% 99.87% # Number of insts issued each cycle
349 system.cpu.iq.issued_per_cycle::8 398072 0.13% 100.00% # Number of insts issued each cycle
350 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
351 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
352 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
353 system.cpu.iq.issued_per_cycle::total 297137957 # Number of insts issued each cycle
354 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
355 system.cpu.iq.fu_full::IntAlu 235011 7.30% 7.30% # attempts to use FU when none available
356 system.cpu.iq.fu_full::IntMult 0 0.00% 7.30% # attempts to use FU when none available
357 system.cpu.iq.fu_full::IntDiv 0 0.00% 7.30% # attempts to use FU when none available
358 system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.30% # attempts to use FU when none available
359 system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.30% # attempts to use FU when none available
360 system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.30% # attempts to use FU when none available
361 system.cpu.iq.fu_full::FloatMult 0 0.00% 7.30% # attempts to use FU when none available
362 system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.30% # attempts to use FU when none available
363 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.30% # attempts to use FU when none available
364 system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.30% # attempts to use FU when none available
365 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.30% # attempts to use FU when none available
366 system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.30% # attempts to use FU when none available
367 system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.30% # attempts to use FU when none available
368 system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.30% # attempts to use FU when none available
369 system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.30% # attempts to use FU when none available
370 system.cpu.iq.fu_full::SimdMult 0 0.00% 7.30% # attempts to use FU when none available
371 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.30% # attempts to use FU when none available
372 system.cpu.iq.fu_full::SimdShift 0 0.00% 7.30% # attempts to use FU when none available
373 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.30% # attempts to use FU when none available
374 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.30% # attempts to use FU when none available
375 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.30% # attempts to use FU when none available
376 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.30% # attempts to use FU when none available
377 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.30% # attempts to use FU when none available
378 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.30% # attempts to use FU when none available
379 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.30% # attempts to use FU when none available
380 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.30% # attempts to use FU when none available
381 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.30% # attempts to use FU when none available
382 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.30% # attempts to use FU when none available
383 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.30% # attempts to use FU when none available
384 system.cpu.iq.fu_full::MemRead 2578157 80.11% 87.41% # attempts to use FU when none available
385 system.cpu.iq.fu_full::MemWrite 405217 12.59% 100.00% # attempts to use FU when none available
386 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
387 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
388 system.cpu.iq.FU_type_0::No_OpClass 1211344 0.45% 0.45% # Type of FU issued
389 system.cpu.iq.FU_type_0::IntAlu 167292419 62.69% 63.14% # Type of FU issued
390 system.cpu.iq.FU_type_0::IntMult 790150 0.30% 63.44% # Type of FU issued
391 system.cpu.iq.FU_type_0::IntDiv 7035672 2.64% 66.08% # Type of FU issued
392 system.cpu.iq.FU_type_0::FloatAdd 1215098 0.46% 66.53% # Type of FU issued
393 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.53% # Type of FU issued
394 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.53% # Type of FU issued
395 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.53% # Type of FU issued
396 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.53% # Type of FU issued
397 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.53% # Type of FU issued
398 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.53% # Type of FU issued
399 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.53% # Type of FU issued
400 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.53% # Type of FU issued
401 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.53% # Type of FU issued
402 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.53% # Type of FU issued
403 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.53% # Type of FU issued
404 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.53% # Type of FU issued
405 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.53% # Type of FU issued
406 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.53% # Type of FU issued
407 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.53% # Type of FU issued
408 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.53% # Type of FU issued
409 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.53% # Type of FU issued
410 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.53% # Type of FU issued
411 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.53% # Type of FU issued
412 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.53% # Type of FU issued
413 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.53% # Type of FU issued
414 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.53% # Type of FU issued
415 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.53% # Type of FU issued
416 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.53% # Type of FU issued
417 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.53% # Type of FU issued
418 system.cpu.iq.FU_type_0::MemRead 66512451 24.92% 91.46% # Type of FU issued
419 system.cpu.iq.FU_type_0::MemWrite 22800047 8.54% 100.00% # Type of FU issued
420 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
421 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
422 system.cpu.iq.FU_type_0::total 266857181 # Type of FU issued
423 system.cpu.iq.rate 0.897488 # Inst issue rate
424 system.cpu.iq.fu_busy_cnt 3218385 # FU busy when requested
425 system.cpu.iq.fu_busy_rate 0.012060 # FU busy rate (busy events/executed inst)
426 system.cpu.iq.int_inst_queue_reads 829150425 # Number of integer instruction queue reads
427 system.cpu.iq.int_inst_queue_writes 456900250 # Number of integer instruction queue writes
428 system.cpu.iq.int_inst_queue_wakeup_accesses 260922611 # Number of integer instruction queue wakeup accesses
429 system.cpu.iq.fp_inst_queue_reads 4994873 # Number of floating instruction queue reads
430 system.cpu.iq.fp_inst_queue_writes 4333463 # Number of floating instruction queue writes
431 system.cpu.iq.fp_inst_queue_wakeup_accesses 2397328 # Number of floating instruction queue wakeup accesses
432 system.cpu.iq.int_alu_accesses 266351243 # Number of integer alu accesses
433 system.cpu.iq.fp_alu_accesses 2512979 # Number of floating point alu accesses
434 system.cpu.iew.lsq.thread0.forwLoads 18909810 # Number of loads that had data forwarded from stores
435 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
436 system.cpu.iew.lsq.thread0.squashedLoads 32990369 # Number of loads squashed
437 system.cpu.iew.lsq.thread0.ignoredResponses 14136 # Number of memory responses ignored because the instruction is squashed
438 system.cpu.iew.lsq.thread0.memOrderViolation 328607 # Number of memory ordering violations
439 system.cpu.iew.lsq.thread0.squashedStores 11516932 # Number of stores squashed
440 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
441 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
442 system.cpu.iew.lsq.thread0.rescheduledLoads 52167 # Number of loads that were rescheduled
443 system.cpu.iew.lsq.thread0.cacheBlocked 10 # Number of times an access to memory failed due to the cache being blocked
444 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
445 system.cpu.iew.iewSquashCycles 1851692 # Number of cycles IEW is squashing
446 system.cpu.iew.iewBlockCycles 126137646 # Number of cycles IEW is blocking
447 system.cpu.iew.iewUnblockCycles 5532810 # Number of cycles IEW is unblocking
448 system.cpu.iew.iewDispatchedInsts 341339634 # Number of instructions dispatched to IQ
449 system.cpu.iew.iewDispSquashedInsts 112602 # Number of squashed instructions skipped by dispatch
450 system.cpu.iew.iewDispLoadInsts 89639956 # Number of dispatched load instructions
451 system.cpu.iew.iewDispStoreInsts 32032649 # Number of dispatched store instructions
452 system.cpu.iew.iewDispNonSpecInsts 2212 # Number of dispatched non-speculative instructions
453 system.cpu.iew.iewIQFullEvents 2223479 # Number of times the IQ has become full, causing a stall
454 system.cpu.iew.iewLSQFullEvents 382778 # Number of times the LSQ has become full, causing a stall
455 system.cpu.iew.memOrderViolationEvents 328607 # Number of memory order violations
456 system.cpu.iew.predictedTakenIncorrect 684628 # Number of branches that were predicted taken incorrectly
457 system.cpu.iew.predictedNotTakenIncorrect 928175 # Number of branches that were predicted not taken incorrectly
458 system.cpu.iew.branchMispredicts 1612803 # Number of branch mispredicts detected at execute
459 system.cpu.iew.iewExecutedInsts 264737771 # Number of executed instructions
460 system.cpu.iew.iewExecLoadInsts 65643847 # Number of load instructions executed
461 system.cpu.iew.iewExecSquashedInsts 2119410 # Number of squashed instructions skipped in execute
462 system.cpu.iew.exec_swp 0 # number of swp insts executed
463 system.cpu.iew.exec_nop 0 # number of nop insts executed
464 system.cpu.iew.exec_refs 88241442 # number of memory reference insts executed
465 system.cpu.iew.exec_branches 14589088 # Number of branches executed
466 system.cpu.iew.exec_stores 22597595 # Number of stores executed
467 system.cpu.iew.exec_rate 0.890361 # Inst execution rate
468 system.cpu.iew.wb_sent 264036391 # cumulative count of insts sent to commit
469 system.cpu.iew.wb_count 263319939 # cumulative count of insts written-back
470 system.cpu.iew.wb_producers 208896510 # num instructions producing a value
471 system.cpu.iew.wb_consumers 376872402 # num instructions consuming a value
472 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
473 system.cpu.iew.wb_rate 0.885592 # insts written-back per cycle
474 system.cpu.iew.wb_fanout 0.554290 # average fanout of values written-back
475 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
476 system.cpu.commit.commitSquashedInsts 120026923 # The number of squashed insts skipped by commit
477 system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards
478 system.cpu.commit.branchMispredicts 1559493 # The number of times a branch was mispredicted
479 system.cpu.commit.committed_per_cycle::samples 280830334 # Number of insts commited each cycle
480 system.cpu.commit.committed_per_cycle::mean 0.788246 # Number of insts commited each cycle
481 system.cpu.commit.committed_per_cycle::stdev 1.594394 # Number of insts commited each cycle
482 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
483 system.cpu.commit.committed_per_cycle::0 180946233 64.43% 64.43% # Number of insts commited each cycle
484 system.cpu.commit.committed_per_cycle::1 57795535 20.58% 85.01% # Number of insts commited each cycle
485 system.cpu.commit.committed_per_cycle::2 14201408 5.06% 90.07% # Number of insts commited each cycle
486 system.cpu.commit.committed_per_cycle::3 11929876 4.25% 94.32% # Number of insts commited each cycle
487 system.cpu.commit.committed_per_cycle::4 4188274 1.49% 95.81% # Number of insts commited each cycle
488 system.cpu.commit.committed_per_cycle::5 2885386 1.03% 96.84% # Number of insts commited each cycle
489 system.cpu.commit.committed_per_cycle::6 910038 0.32% 97.16% # Number of insts commited each cycle
490 system.cpu.commit.committed_per_cycle::7 1053521 0.38% 97.54% # Number of insts commited each cycle
491 system.cpu.commit.committed_per_cycle::8 6920063 2.46% 100.00% # Number of insts commited each cycle
492 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
493 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
494 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
495 system.cpu.commit.committed_per_cycle::total 280830334 # Number of insts commited each cycle
496 system.cpu.commit.committedInsts 132071192 # Number of instructions committed
497 system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed
498 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
499 system.cpu.commit.refs 77165304 # Number of memory references committed
500 system.cpu.commit.loads 56649587 # Number of loads committed
501 system.cpu.commit.membars 0 # Number of memory barriers committed
502 system.cpu.commit.branches 12326938 # Number of branches committed
503 system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions.
504 system.cpu.commit.int_insts 219019985 # Number of committed integer instructions.
505 system.cpu.commit.function_calls 797818 # Number of function calls committed.
506 system.cpu.commit.op_class_0::No_OpClass 1176721 0.53% 0.53% # Class of committed instruction
507 system.cpu.commit.op_class_0::IntAlu 134111832 60.58% 61.12% # Class of committed instruction
508 system.cpu.commit.op_class_0::IntMult 772953 0.35% 61.47% # Class of committed instruction
509 system.cpu.commit.op_class_0::IntDiv 7031501 3.18% 64.64% # Class of committed instruction
510 system.cpu.commit.op_class_0::FloatAdd 1105073 0.50% 65.14% # Class of committed instruction
511 system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.14% # Class of committed instruction
512 system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.14% # Class of committed instruction
513 system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.14% # Class of committed instruction
514 system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.14% # Class of committed instruction
515 system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.14% # Class of committed instruction
516 system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.14% # Class of committed instruction
517 system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.14% # Class of committed instruction
518 system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.14% # Class of committed instruction
519 system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.14% # Class of committed instruction
520 system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.14% # Class of committed instruction
521 system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.14% # Class of committed instruction
522 system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.14% # Class of committed instruction
523 system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.14% # Class of committed instruction
524 system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.14% # Class of committed instruction
525 system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.14% # Class of committed instruction
526 system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.14% # Class of committed instruction
527 system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.14% # Class of committed instruction
528 system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.14% # Class of committed instruction
529 system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.14% # Class of committed instruction
530 system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.14% # Class of committed instruction
531 system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.14% # Class of committed instruction
532 system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.14% # Class of committed instruction
533 system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.14% # Class of committed instruction
534 system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.14% # Class of committed instruction
535 system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.14% # Class of committed instruction
536 system.cpu.commit.op_class_0::MemRead 56649587 25.59% 90.73% # Class of committed instruction
537 system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Class of committed instruction
538 system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
539 system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
540 system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction
541 system.cpu.commit.bw_lim_events 6920063 # number cycles where commit BW limit reached
542 system.cpu.rob.rob_reads 615300578 # The number of ROB reads
543 system.cpu.rob.rob_writes 699132843 # The number of ROB writes
544 system.cpu.timesIdled 3156 # Number of times that the entire CPU went into an idle state and unscheduled itself
545 system.cpu.idleCycles 199760 # Total number of cycles that the CPU has spent unscheduled due to idling
546 system.cpu.committedInsts 132071192 # Number of Instructions Simulated
547 system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated
548 system.cpu.cpi 2.251344 # CPI: Cycles Per Instruction
549 system.cpu.cpi_total 2.251344 # CPI: Total CPI of All Threads
550 system.cpu.ipc 0.444179 # IPC: Instructions Per Cycle
551 system.cpu.ipc_total 0.444179 # IPC: Total IPC of All Threads
552 system.cpu.int_regfile_reads 456486870 # number of integer regfile reads
553 system.cpu.int_regfile_writes 239256029 # number of integer regfile writes
554 system.cpu.fp_regfile_reads 3277423 # number of floating regfile reads
555 system.cpu.fp_regfile_writes 2057707 # number of floating regfile writes
556 system.cpu.cc_regfile_reads 102994410 # number of cc regfile reads
557 system.cpu.cc_regfile_writes 60201710 # number of cc regfile writes
558 system.cpu.misc_regfile_reads 136869897 # number of misc regfile reads
559 system.cpu.misc_regfile_writes 1689 # number of misc regfile writes
560 system.cpu.dcache.tags.replacements 51 # number of replacements
561 system.cpu.dcache.tags.tagsinuse 1444.566400 # Cycle average of tags in use
562 system.cpu.dcache.tags.total_refs 67084714 # Total number of references to valid blocks.
563 system.cpu.dcache.tags.sampled_refs 2000 # Sample count of references to valid blocks.
564 system.cpu.dcache.tags.avg_refs 33542.357000 # Average number of references to valid blocks.
565 system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
566 system.cpu.dcache.tags.occ_blocks::cpu.data 1444.566400 # Average occupied blocks per requestor
567 system.cpu.dcache.tags.occ_percent::cpu.data 0.352677 # Average percentage of cache occupancy
568 system.cpu.dcache.tags.occ_percent::total 0.352677 # Average percentage of cache occupancy
569 system.cpu.dcache.tags.occ_task_id_blocks::1024 1949 # Occupied blocks per task id
570 system.cpu.dcache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id
571 system.cpu.dcache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id
572 system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id
573 system.cpu.dcache.tags.age_task_id_blocks_1024::3 432 # Occupied blocks per task id
574 system.cpu.dcache.tags.age_task_id_blocks_1024::4 1405 # Occupied blocks per task id
575 system.cpu.dcache.tags.occ_task_id_percent::1024 0.475830 # Percentage of cache occupancy per task id
576 system.cpu.dcache.tags.tag_accesses 134176300 # Number of tag accesses
577 system.cpu.dcache.tags.data_accesses 134176300 # Number of data accesses
578 system.cpu.dcache.ReadReq_hits::cpu.data 46570369 # number of ReadReq hits
579 system.cpu.dcache.ReadReq_hits::total 46570369 # number of ReadReq hits
580 system.cpu.dcache.WriteReq_hits::cpu.data 20513845 # number of WriteReq hits
581 system.cpu.dcache.WriteReq_hits::total 20513845 # number of WriteReq hits
582 system.cpu.dcache.demand_hits::cpu.data 67084214 # number of demand (read+write) hits
583 system.cpu.dcache.demand_hits::total 67084214 # number of demand (read+write) hits
584 system.cpu.dcache.overall_hits::cpu.data 67084214 # number of overall hits
585 system.cpu.dcache.overall_hits::total 67084214 # number of overall hits
586 system.cpu.dcache.ReadReq_misses::cpu.data 1050 # number of ReadReq misses
587 system.cpu.dcache.ReadReq_misses::total 1050 # number of ReadReq misses
588 system.cpu.dcache.WriteReq_misses::cpu.data 1886 # number of WriteReq misses
589 system.cpu.dcache.WriteReq_misses::total 1886 # number of WriteReq misses
590 system.cpu.dcache.demand_misses::cpu.data 2936 # number of demand (read+write) misses
591 system.cpu.dcache.demand_misses::total 2936 # number of demand (read+write) misses
592 system.cpu.dcache.overall_misses::cpu.data 2936 # number of overall misses
593 system.cpu.dcache.overall_misses::total 2936 # number of overall misses
594 system.cpu.dcache.ReadReq_miss_latency::cpu.data 66068903 # number of ReadReq miss cycles
595 system.cpu.dcache.ReadReq_miss_latency::total 66068903 # number of ReadReq miss cycles
596 system.cpu.dcache.WriteReq_miss_latency::cpu.data 130813345 # number of WriteReq miss cycles
597 system.cpu.dcache.WriteReq_miss_latency::total 130813345 # number of WriteReq miss cycles
598 system.cpu.dcache.demand_miss_latency::cpu.data 196882248 # number of demand (read+write) miss cycles
599 system.cpu.dcache.demand_miss_latency::total 196882248 # number of demand (read+write) miss cycles
600 system.cpu.dcache.overall_miss_latency::cpu.data 196882248 # number of overall miss cycles
601 system.cpu.dcache.overall_miss_latency::total 196882248 # number of overall miss cycles
602 system.cpu.dcache.ReadReq_accesses::cpu.data 46571419 # number of ReadReq accesses(hits+misses)
603 system.cpu.dcache.ReadReq_accesses::total 46571419 # number of ReadReq accesses(hits+misses)
604 system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
605 system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
606 system.cpu.dcache.demand_accesses::cpu.data 67087150 # number of demand (read+write) accesses
607 system.cpu.dcache.demand_accesses::total 67087150 # number of demand (read+write) accesses
608 system.cpu.dcache.overall_accesses::cpu.data 67087150 # number of overall (read+write) accesses
609 system.cpu.dcache.overall_accesses::total 67087150 # number of overall (read+write) accesses
610 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000023 # miss rate for ReadReq accesses
611 system.cpu.dcache.ReadReq_miss_rate::total 0.000023 # miss rate for ReadReq accesses
612 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000092 # miss rate for WriteReq accesses
613 system.cpu.dcache.WriteReq_miss_rate::total 0.000092 # miss rate for WriteReq accesses
614 system.cpu.dcache.demand_miss_rate::cpu.data 0.000044 # miss rate for demand accesses
615 system.cpu.dcache.demand_miss_rate::total 0.000044 # miss rate for demand accesses
616 system.cpu.dcache.overall_miss_rate::cpu.data 0.000044 # miss rate for overall accesses
617 system.cpu.dcache.overall_miss_rate::total 0.000044 # miss rate for overall accesses
618 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62922.764762 # average ReadReq miss latency
619 system.cpu.dcache.ReadReq_avg_miss_latency::total 62922.764762 # average ReadReq miss latency
620 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69360.204136 # average WriteReq miss latency
621 system.cpu.dcache.WriteReq_avg_miss_latency::total 69360.204136 # average WriteReq miss latency
622 system.cpu.dcache.demand_avg_miss_latency::cpu.data 67057.986376 # average overall miss latency
623 system.cpu.dcache.demand_avg_miss_latency::total 67057.986376 # average overall miss latency
624 system.cpu.dcache.overall_avg_miss_latency::cpu.data 67057.986376 # average overall miss latency
625 system.cpu.dcache.overall_avg_miss_latency::total 67057.986376 # average overall miss latency
626 system.cpu.dcache.blocked_cycles::no_mshrs 241 # number of cycles access was blocked
627 system.cpu.dcache.blocked_cycles::no_targets 39 # number of cycles access was blocked
628 system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked
629 system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
630 system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.200000 # average number of cycles each access was blocked
631 system.cpu.dcache.avg_blocked_cycles::no_targets 19.500000 # average number of cycles each access was blocked
632 system.cpu.dcache.fast_writes 0 # number of fast writes performed
633 system.cpu.dcache.cache_copies 0 # number of cache copies performed
634 system.cpu.dcache.writebacks::writebacks 10 # number of writebacks
635 system.cpu.dcache.writebacks::total 10 # number of writebacks
636 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 588 # number of ReadReq MSHR hits
637 system.cpu.dcache.ReadReq_mshr_hits::total 588 # number of ReadReq MSHR hits
638 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1 # number of WriteReq MSHR hits
639 system.cpu.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits
640 system.cpu.dcache.demand_mshr_hits::cpu.data 589 # number of demand (read+write) MSHR hits
641 system.cpu.dcache.demand_mshr_hits::total 589 # number of demand (read+write) MSHR hits
642 system.cpu.dcache.overall_mshr_hits::cpu.data 589 # number of overall MSHR hits
643 system.cpu.dcache.overall_mshr_hits::total 589 # number of overall MSHR hits
644 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 462 # number of ReadReq MSHR misses
645 system.cpu.dcache.ReadReq_mshr_misses::total 462 # number of ReadReq MSHR misses
646 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1885 # number of WriteReq MSHR misses
647 system.cpu.dcache.WriteReq_mshr_misses::total 1885 # number of WriteReq MSHR misses
648 system.cpu.dcache.demand_mshr_misses::cpu.data 2347 # number of demand (read+write) MSHR misses
649 system.cpu.dcache.demand_mshr_misses::total 2347 # number of demand (read+write) MSHR misses
650 system.cpu.dcache.overall_mshr_misses::cpu.data 2347 # number of overall MSHR misses
651 system.cpu.dcache.overall_mshr_misses::total 2347 # number of overall MSHR misses
652 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36319250 # number of ReadReq MSHR miss cycles
653 system.cpu.dcache.ReadReq_mshr_miss_latency::total 36319250 # number of ReadReq MSHR miss cycles
654 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 127241905 # number of WriteReq MSHR miss cycles
655 system.cpu.dcache.WriteReq_mshr_miss_latency::total 127241905 # number of WriteReq MSHR miss cycles
656 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 163561155 # number of demand (read+write) MSHR miss cycles
657 system.cpu.dcache.demand_mshr_miss_latency::total 163561155 # number of demand (read+write) MSHR miss cycles
658 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 163561155 # number of overall MSHR miss cycles
659 system.cpu.dcache.overall_mshr_miss_latency::total 163561155 # number of overall MSHR miss cycles
660 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
661 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
662 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000092 # mshr miss rate for WriteReq accesses
663 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000092 # mshr miss rate for WriteReq accesses
664 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for demand accesses
665 system.cpu.dcache.demand_mshr_miss_rate::total 0.000035 # mshr miss rate for demand accesses
666 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for overall accesses
667 system.cpu.dcache.overall_mshr_miss_rate::total 0.000035 # mshr miss rate for overall accesses
668 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78613.095238 # average ReadReq mshr miss latency
669 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78613.095238 # average ReadReq mshr miss latency
670 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67502.336870 # average WriteReq mshr miss latency
671 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67502.336870 # average WriteReq mshr miss latency
672 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 69689.456753 # average overall mshr miss latency
673 system.cpu.dcache.demand_avg_mshr_miss_latency::total 69689.456753 # average overall mshr miss latency
674 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 69689.456753 # average overall mshr miss latency
675 system.cpu.dcache.overall_avg_mshr_miss_latency::total 69689.456753 # average overall mshr miss latency
676 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
677 system.cpu.icache.tags.replacements 5861 # number of replacements
678 system.cpu.icache.tags.tagsinuse 1662.434995 # Cycle average of tags in use
679 system.cpu.icache.tags.total_refs 26645946 # Total number of references to valid blocks.
680 system.cpu.icache.tags.sampled_refs 7838 # Sample count of references to valid blocks.
681 system.cpu.icache.tags.avg_refs 3399.584843 # Average number of references to valid blocks.
682 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
683 system.cpu.icache.tags.occ_blocks::cpu.inst 1662.434995 # Average occupied blocks per requestor
684 system.cpu.icache.tags.occ_percent::cpu.inst 0.811736 # Average percentage of cache occupancy
685 system.cpu.icache.tags.occ_percent::total 0.811736 # Average percentage of cache occupancy
686 system.cpu.icache.tags.occ_task_id_blocks::1024 1977 # Occupied blocks per task id
687 system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id
688 system.cpu.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id
689 system.cpu.icache.tags.age_task_id_blocks_1024::2 756 # Occupied blocks per task id
690 system.cpu.icache.tags.age_task_id_blocks_1024::3 135 # Occupied blocks per task id
691 system.cpu.icache.tags.age_task_id_blocks_1024::4 777 # Occupied blocks per task id
692 system.cpu.icache.tags.occ_task_id_percent::1024 0.965332 # Percentage of cache occupancy per task id
693 system.cpu.icache.tags.tag_accesses 53321296 # Number of tag accesses
694 system.cpu.icache.tags.data_accesses 53321296 # Number of data accesses
695 system.cpu.icache.ReadReq_hits::cpu.inst 26645946 # number of ReadReq hits
696 system.cpu.icache.ReadReq_hits::total 26645946 # number of ReadReq hits
697 system.cpu.icache.demand_hits::cpu.inst 26645946 # number of demand (read+write) hits
698 system.cpu.icache.demand_hits::total 26645946 # number of demand (read+write) hits
699 system.cpu.icache.overall_hits::cpu.inst 26645946 # number of overall hits
700 system.cpu.icache.overall_hits::total 26645946 # number of overall hits
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702 system.cpu.icache.ReadReq_misses::total 10610 # number of ReadReq misses
703 system.cpu.icache.demand_misses::cpu.inst 10610 # number of demand (read+write) misses
704 system.cpu.icache.demand_misses::total 10610 # number of demand (read+write) misses
705 system.cpu.icache.overall_misses::cpu.inst 10610 # number of overall misses
706 system.cpu.icache.overall_misses::total 10610 # number of overall misses
707 system.cpu.icache.ReadReq_miss_latency::cpu.inst 431026999 # number of ReadReq miss cycles
708 system.cpu.icache.ReadReq_miss_latency::total 431026999 # number of ReadReq miss cycles
709 system.cpu.icache.demand_miss_latency::cpu.inst 431026999 # number of demand (read+write) miss cycles
710 system.cpu.icache.demand_miss_latency::total 431026999 # number of demand (read+write) miss cycles
711 system.cpu.icache.overall_miss_latency::cpu.inst 431026999 # number of overall miss cycles
712 system.cpu.icache.overall_miss_latency::total 431026999 # number of overall miss cycles
713 system.cpu.icache.ReadReq_accesses::cpu.inst 26656556 # number of ReadReq accesses(hits+misses)
714 system.cpu.icache.ReadReq_accesses::total 26656556 # number of ReadReq accesses(hits+misses)
715 system.cpu.icache.demand_accesses::cpu.inst 26656556 # number of demand (read+write) accesses
716 system.cpu.icache.demand_accesses::total 26656556 # number of demand (read+write) accesses
717 system.cpu.icache.overall_accesses::cpu.inst 26656556 # number of overall (read+write) accesses
718 system.cpu.icache.overall_accesses::total 26656556 # number of overall (read+write) accesses
719 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000398 # miss rate for ReadReq accesses
720 system.cpu.icache.ReadReq_miss_rate::total 0.000398 # miss rate for ReadReq accesses
721 system.cpu.icache.demand_miss_rate::cpu.inst 0.000398 # miss rate for demand accesses
722 system.cpu.icache.demand_miss_rate::total 0.000398 # miss rate for demand accesses
723 system.cpu.icache.overall_miss_rate::cpu.inst 0.000398 # miss rate for overall accesses
724 system.cpu.icache.overall_miss_rate::total 0.000398 # miss rate for overall accesses
725 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40624.599340 # average ReadReq miss latency
726 system.cpu.icache.ReadReq_avg_miss_latency::total 40624.599340 # average ReadReq miss latency
727 system.cpu.icache.demand_avg_miss_latency::cpu.inst 40624.599340 # average overall miss latency
728 system.cpu.icache.demand_avg_miss_latency::total 40624.599340 # average overall miss latency
729 system.cpu.icache.overall_avg_miss_latency::cpu.inst 40624.599340 # average overall miss latency
730 system.cpu.icache.overall_avg_miss_latency::total 40624.599340 # average overall miss latency
731 system.cpu.icache.blocked_cycles::no_mshrs 1664 # number of cycles access was blocked
732 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
733 system.cpu.icache.blocked::no_mshrs 27 # number of cycles access was blocked
734 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
735 system.cpu.icache.avg_blocked_cycles::no_mshrs 61.629630 # average number of cycles each access was blocked
736 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
737 system.cpu.icache.fast_writes 0 # number of fast writes performed
738 system.cpu.icache.cache_copies 0 # number of cache copies performed
739 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2425 # number of ReadReq MSHR hits
740 system.cpu.icache.ReadReq_mshr_hits::total 2425 # number of ReadReq MSHR hits
741 system.cpu.icache.demand_mshr_hits::cpu.inst 2425 # number of demand (read+write) MSHR hits
742 system.cpu.icache.demand_mshr_hits::total 2425 # number of demand (read+write) MSHR hits
743 system.cpu.icache.overall_mshr_hits::cpu.inst 2425 # number of overall MSHR hits
744 system.cpu.icache.overall_mshr_hits::total 2425 # number of overall MSHR hits
745 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8185 # number of ReadReq MSHR misses
746 system.cpu.icache.ReadReq_mshr_misses::total 8185 # number of ReadReq MSHR misses
747 system.cpu.icache.demand_mshr_misses::cpu.inst 8185 # number of demand (read+write) MSHR misses
748 system.cpu.icache.demand_mshr_misses::total 8185 # number of demand (read+write) MSHR misses
749 system.cpu.icache.overall_mshr_misses::cpu.inst 8185 # number of overall MSHR misses
750 system.cpu.icache.overall_mshr_misses::total 8185 # number of overall MSHR misses
751 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 323320999 # number of ReadReq MSHR miss cycles
752 system.cpu.icache.ReadReq_mshr_miss_latency::total 323320999 # number of ReadReq MSHR miss cycles
753 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 323320999 # number of demand (read+write) MSHR miss cycles
754 system.cpu.icache.demand_mshr_miss_latency::total 323320999 # number of demand (read+write) MSHR miss cycles
755 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 323320999 # number of overall MSHR miss cycles
756 system.cpu.icache.overall_mshr_miss_latency::total 323320999 # number of overall MSHR miss cycles
757 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000307 # mshr miss rate for ReadReq accesses
758 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000307 # mshr miss rate for ReadReq accesses
759 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000307 # mshr miss rate for demand accesses
760 system.cpu.icache.demand_mshr_miss_rate::total 0.000307 # mshr miss rate for demand accesses
761 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000307 # mshr miss rate for overall accesses
762 system.cpu.icache.overall_mshr_miss_rate::total 0.000307 # mshr miss rate for overall accesses
763 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39501.649236 # average ReadReq mshr miss latency
764 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39501.649236 # average ReadReq mshr miss latency
765 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39501.649236 # average overall mshr miss latency
766 system.cpu.icache.demand_avg_mshr_miss_latency::total 39501.649236 # average overall mshr miss latency
767 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39501.649236 # average overall mshr miss latency
768 system.cpu.icache.overall_avg_mshr_miss_latency::total 39501.649236 # average overall mshr miss latency
769 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
770 system.cpu.l2cache.tags.replacements 0 # number of replacements
771 system.cpu.l2cache.tags.tagsinuse 2641.798011 # Cycle average of tags in use
772 system.cpu.l2cache.tags.total_refs 4354 # Total number of references to valid blocks.
773 system.cpu.l2cache.tags.sampled_refs 3951 # Sample count of references to valid blocks.
774 system.cpu.l2cache.tags.avg_refs 1.101999 # Average number of references to valid blocks.
775 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
776 system.cpu.l2cache.tags.occ_blocks::writebacks 1.181969 # Average occupied blocks per requestor
777 system.cpu.l2cache.tags.occ_blocks::cpu.inst 2328.091219 # Average occupied blocks per requestor
778 system.cpu.l2cache.tags.occ_blocks::cpu.data 312.524822 # Average occupied blocks per requestor
779 system.cpu.l2cache.tags.occ_percent::writebacks 0.000036 # Average percentage of cache occupancy
780 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.071048 # Average percentage of cache occupancy
781 system.cpu.l2cache.tags.occ_percent::cpu.data 0.009538 # Average percentage of cache occupancy
782 system.cpu.l2cache.tags.occ_percent::total 0.080621 # Average percentage of cache occupancy
783 system.cpu.l2cache.tags.occ_task_id_blocks::1024 3951 # Occupied blocks per task id
784 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
785 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id
786 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 894 # Occupied blocks per task id
787 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 157 # Occupied blocks per task id
788 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2664 # Occupied blocks per task id
789 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.120575 # Percentage of cache occupancy per task id
790 system.cpu.l2cache.tags.tag_accesses 87043 # Number of tag accesses
791 system.cpu.l2cache.tags.data_accesses 87043 # Number of data accesses
792 system.cpu.l2cache.ReadReq_hits::cpu.inst 4315 # number of ReadReq hits
793 system.cpu.l2cache.ReadReq_hits::cpu.data 34 # number of ReadReq hits
794 system.cpu.l2cache.ReadReq_hits::total 4349 # number of ReadReq hits
795 system.cpu.l2cache.Writeback_hits::writebacks 10 # number of Writeback hits
796 system.cpu.l2cache.Writeback_hits::total 10 # number of Writeback hits
797 system.cpu.l2cache.UpgradeReq_hits::cpu.data 2 # number of UpgradeReq hits
798 system.cpu.l2cache.UpgradeReq_hits::total 2 # number of UpgradeReq hits
799 system.cpu.l2cache.ReadExReq_hits::cpu.data 5 # number of ReadExReq hits
800 system.cpu.l2cache.ReadExReq_hits::total 5 # number of ReadExReq hits
801 system.cpu.l2cache.demand_hits::cpu.inst 4315 # number of demand (read+write) hits
802 system.cpu.l2cache.demand_hits::cpu.data 39 # number of demand (read+write) hits
803 system.cpu.l2cache.demand_hits::total 4354 # number of demand (read+write) hits
804 system.cpu.l2cache.overall_hits::cpu.inst 4315 # number of overall hits
805 system.cpu.l2cache.overall_hits::cpu.data 39 # number of overall hits
806 system.cpu.l2cache.overall_hits::total 4354 # number of overall hits
807 system.cpu.l2cache.ReadReq_misses::cpu.inst 3522 # number of ReadReq misses
808 system.cpu.l2cache.ReadReq_misses::cpu.data 428 # number of ReadReq misses
809 system.cpu.l2cache.ReadReq_misses::total 3950 # number of ReadReq misses
810 system.cpu.l2cache.UpgradeReq_misses::cpu.data 345 # number of UpgradeReq misses
811 system.cpu.l2cache.UpgradeReq_misses::total 345 # number of UpgradeReq misses
812 system.cpu.l2cache.ReadExReq_misses::cpu.data 1533 # number of ReadExReq misses
813 system.cpu.l2cache.ReadExReq_misses::total 1533 # number of ReadExReq misses
814 system.cpu.l2cache.demand_misses::cpu.inst 3522 # number of demand (read+write) misses
815 system.cpu.l2cache.demand_misses::cpu.data 1961 # number of demand (read+write) misses
816 system.cpu.l2cache.demand_misses::total 5483 # number of demand (read+write) misses
817 system.cpu.l2cache.overall_misses::cpu.inst 3522 # number of overall misses
818 system.cpu.l2cache.overall_misses::cpu.data 1961 # number of overall misses
819 system.cpu.l2cache.overall_misses::total 5483 # number of overall misses
820 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 269302250 # number of ReadReq miss cycles
821 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35486250 # number of ReadReq miss cycles
822 system.cpu.l2cache.ReadReq_miss_latency::total 304788500 # number of ReadReq miss cycles
823 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 114514250 # number of ReadExReq miss cycles
824 system.cpu.l2cache.ReadExReq_miss_latency::total 114514250 # number of ReadExReq miss cycles
825 system.cpu.l2cache.demand_miss_latency::cpu.inst 269302250 # number of demand (read+write) miss cycles
826 system.cpu.l2cache.demand_miss_latency::cpu.data 150000500 # number of demand (read+write) miss cycles
827 system.cpu.l2cache.demand_miss_latency::total 419302750 # number of demand (read+write) miss cycles
828 system.cpu.l2cache.overall_miss_latency::cpu.inst 269302250 # number of overall miss cycles
829 system.cpu.l2cache.overall_miss_latency::cpu.data 150000500 # number of overall miss cycles
830 system.cpu.l2cache.overall_miss_latency::total 419302750 # number of overall miss cycles
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833 system.cpu.l2cache.ReadReq_accesses::total 8299 # number of ReadReq accesses(hits+misses)
834 system.cpu.l2cache.Writeback_accesses::writebacks 10 # number of Writeback accesses(hits+misses)
835 system.cpu.l2cache.Writeback_accesses::total 10 # number of Writeback accesses(hits+misses)
836 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 347 # number of UpgradeReq accesses(hits+misses)
837 system.cpu.l2cache.UpgradeReq_accesses::total 347 # number of UpgradeReq accesses(hits+misses)
838 system.cpu.l2cache.ReadExReq_accesses::cpu.data 1538 # number of ReadExReq accesses(hits+misses)
839 system.cpu.l2cache.ReadExReq_accesses::total 1538 # number of ReadExReq accesses(hits+misses)
840 system.cpu.l2cache.demand_accesses::cpu.inst 7837 # number of demand (read+write) accesses
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843 system.cpu.l2cache.overall_accesses::cpu.inst 7837 # number of overall (read+write) accesses
844 system.cpu.l2cache.overall_accesses::cpu.data 2000 # number of overall (read+write) accesses
845 system.cpu.l2cache.overall_accesses::total 9837 # number of overall (read+write) accesses
846 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.449407 # miss rate for ReadReq accesses
847 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.926407 # miss rate for ReadReq accesses
848 system.cpu.l2cache.ReadReq_miss_rate::total 0.475961 # miss rate for ReadReq accesses
849 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.994236 # miss rate for UpgradeReq accesses
850 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.994236 # miss rate for UpgradeReq accesses
851 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.996749 # miss rate for ReadExReq accesses
852 system.cpu.l2cache.ReadExReq_miss_rate::total 0.996749 # miss rate for ReadExReq accesses
853 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.449407 # miss rate for demand accesses
854 system.cpu.l2cache.demand_miss_rate::cpu.data 0.980500 # miss rate for demand accesses
855 system.cpu.l2cache.demand_miss_rate::total 0.557385 # miss rate for demand accesses
856 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.449407 # miss rate for overall accesses
857 system.cpu.l2cache.overall_miss_rate::cpu.data 0.980500 # miss rate for overall accesses
858 system.cpu.l2cache.overall_miss_rate::total 0.557385 # miss rate for overall accesses
859 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76462.876207 # average ReadReq miss latency
860 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82911.799065 # average ReadReq miss latency
861 system.cpu.l2cache.ReadReq_avg_miss_latency::total 77161.645570 # average ReadReq miss latency
862 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74699.445532 # average ReadExReq miss latency
863 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74699.445532 # average ReadExReq miss latency
864 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76462.876207 # average overall miss latency
865 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76491.840898 # average overall miss latency
866 system.cpu.l2cache.demand_avg_miss_latency::total 76473.235455 # average overall miss latency
867 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76462.876207 # average overall miss latency
868 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76491.840898 # average overall miss latency
869 system.cpu.l2cache.overall_avg_miss_latency::total 76473.235455 # average overall miss latency
870 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
871 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
872 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
873 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
874 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
875 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
876 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
877 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
878 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3522 # number of ReadReq MSHR misses
879 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 428 # number of ReadReq MSHR misses
880 system.cpu.l2cache.ReadReq_mshr_misses::total 3950 # number of ReadReq MSHR misses
881 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 345 # number of UpgradeReq MSHR misses
882 system.cpu.l2cache.UpgradeReq_mshr_misses::total 345 # number of UpgradeReq MSHR misses
883 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1533 # number of ReadExReq MSHR misses
884 system.cpu.l2cache.ReadExReq_mshr_misses::total 1533 # number of ReadExReq MSHR misses
885 system.cpu.l2cache.demand_mshr_misses::cpu.inst 3522 # number of demand (read+write) MSHR misses
886 system.cpu.l2cache.demand_mshr_misses::cpu.data 1961 # number of demand (read+write) MSHR misses
887 system.cpu.l2cache.demand_mshr_misses::total 5483 # number of demand (read+write) MSHR misses
888 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3522 # number of overall MSHR misses
889 system.cpu.l2cache.overall_mshr_misses::cpu.data 1961 # number of overall MSHR misses
890 system.cpu.l2cache.overall_mshr_misses::total 5483 # number of overall MSHR misses
891 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 225343750 # number of ReadReq MSHR miss cycles
892 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 30127250 # number of ReadReq MSHR miss cycles
893 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 255471000 # number of ReadReq MSHR miss cycles
894 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6111844 # number of UpgradeReq MSHR miss cycles
895 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6111844 # number of UpgradeReq MSHR miss cycles
896 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 95336750 # number of ReadExReq MSHR miss cycles
897 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 95336750 # number of ReadExReq MSHR miss cycles
898 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 225343750 # number of demand (read+write) MSHR miss cycles
899 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 125464000 # number of demand (read+write) MSHR miss cycles
900 system.cpu.l2cache.demand_mshr_miss_latency::total 350807750 # number of demand (read+write) MSHR miss cycles
901 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 225343750 # number of overall MSHR miss cycles
902 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 125464000 # number of overall MSHR miss cycles
903 system.cpu.l2cache.overall_mshr_miss_latency::total 350807750 # number of overall MSHR miss cycles
904 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.449407 # mshr miss rate for ReadReq accesses
905 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.926407 # mshr miss rate for ReadReq accesses
906 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.475961 # mshr miss rate for ReadReq accesses
907 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.994236 # mshr miss rate for UpgradeReq accesses
908 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.994236 # mshr miss rate for UpgradeReq accesses
909 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.996749 # mshr miss rate for ReadExReq accesses
910 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.996749 # mshr miss rate for ReadExReq accesses
911 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.449407 # mshr miss rate for demand accesses
912 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980500 # mshr miss rate for demand accesses
913 system.cpu.l2cache.demand_mshr_miss_rate::total 0.557385 # mshr miss rate for demand accesses
914 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.449407 # mshr miss rate for overall accesses
915 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980500 # mshr miss rate for overall accesses
916 system.cpu.l2cache.overall_mshr_miss_rate::total 0.557385 # mshr miss rate for overall accesses
917 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63981.757524 # average ReadReq mshr miss latency
918 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70390.771028 # average ReadReq mshr miss latency
919 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64676.202532 # average ReadReq mshr miss latency
920 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17715.489855 # average UpgradeReq mshr miss latency
921 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17715.489855 # average UpgradeReq mshr miss latency
922 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62189.660796 # average ReadExReq mshr miss latency
923 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62189.660796 # average ReadExReq mshr miss latency
924 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63981.757524 # average overall mshr miss latency
925 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63979.602244 # average overall mshr miss latency
926 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63980.986686 # average overall mshr miss latency
927 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63981.757524 # average overall mshr miss latency
928 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63979.602244 # average overall mshr miss latency
929 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63980.986686 # average overall mshr miss latency
930 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
931 system.cpu.toL2Bus.trans_dist::ReadReq 8647 # Transaction distribution
932 system.cpu.toL2Bus.trans_dist::ReadResp 8646 # Transaction distribution
933 system.cpu.toL2Bus.trans_dist::Writeback 10 # Transaction distribution
934 system.cpu.toL2Bus.trans_dist::UpgradeReq 347 # Transaction distribution
935 system.cpu.toL2Bus.trans_dist::UpgradeResp 347 # Transaction distribution
936 system.cpu.toL2Bus.trans_dist::ReadExReq 1538 # Transaction distribution
937 system.cpu.toL2Bus.trans_dist::ReadExResp 1538 # Transaction distribution
938 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16021 # Packet count per connected master and slave (bytes)
939 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4704 # Packet count per connected master and slave (bytes)
940 system.cpu.toL2Bus.pkt_count::total 20725 # Packet count per connected master and slave (bytes)
941 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 501504 # Cumulative packet size per connected master and slave (bytes)
942 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128640 # Cumulative packet size per connected master and slave (bytes)
943 system.cpu.toL2Bus.pkt_size::total 630144 # Cumulative packet size per connected master and slave (bytes)
944 system.cpu.toL2Bus.snoops 348 # Total snoops (count)
945 system.cpu.toL2Bus.snoop_fanout::samples 10542 # Request fanout histogram
946 system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
947 system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
948 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
949 system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
950 system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
951 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
952 system.cpu.toL2Bus.snoop_fanout::3 10542 100.00% 100.00% # Request fanout histogram
953 system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
954 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
955 system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
956 system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
957 system.cpu.toL2Bus.snoop_fanout::total 10542 # Request fanout histogram
958 system.cpu.toL2Bus.reqLayer0.occupancy 5281499 # Layer occupancy (ticks)
959 system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
960 system.cpu.toL2Bus.respLayer0.occupancy 12941000 # Layer occupancy (ticks)
961 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
962 system.cpu.toL2Bus.respLayer1.occupancy 3566845 # Layer occupancy (ticks)
963 system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
964 system.membus.trans_dist::ReadReq 3949 # Transaction distribution
965 system.membus.trans_dist::ReadResp 3949 # Transaction distribution
966 system.membus.trans_dist::UpgradeReq 345 # Transaction distribution
967 system.membus.trans_dist::UpgradeResp 345 # Transaction distribution
968 system.membus.trans_dist::ReadExReq 1533 # Transaction distribution
969 system.membus.trans_dist::ReadExResp 1533 # Transaction distribution
970 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11654 # Packet count per connected master and slave (bytes)
971 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11654 # Packet count per connected master and slave (bytes)
972 system.membus.pkt_count::total 11654 # Packet count per connected master and slave (bytes)
973 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 350848 # Cumulative packet size per connected master and slave (bytes)
974 system.membus.pkt_size_system.cpu.l2cache.mem_side::total 350848 # Cumulative packet size per connected master and slave (bytes)
975 system.membus.pkt_size::total 350848 # Cumulative packet size per connected master and slave (bytes)
976 system.membus.snoops 0 # Total snoops (count)
977 system.membus.snoop_fanout::samples 5827 # Request fanout histogram
978 system.membus.snoop_fanout::mean 0 # Request fanout histogram
979 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
980 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
981 system.membus.snoop_fanout::0 5827 100.00% 100.00% # Request fanout histogram
982 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
983 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
984 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
985 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
986 system.membus.snoop_fanout::total 5827 # Request fanout histogram
987 system.membus.reqLayer0.occupancy 7212001 # Layer occupancy (ticks)
988 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
989 system.membus.respLayer1.occupancy 29752405 # Layer occupancy (ticks)
990 system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
992 ---------- End Simulation Statistics ----------
projects / gem5.git / blob