368cbf9300bd6f0a0ac3570a12918f94de0b6882
6 time_sync_period=100000000000
7 time_sync_spin_threshold=100000000
11 children=cpu membus physmem
16 load_addr_mask=1099511627775
19 memories=system.physmem
23 work_begin_ckpt_count=0
24 work_begin_cpu_id_exit=-1
25 work_begin_exit_count=0
26 work_cpus_ckpt_count=0
30 system_port=system.membus.slave[0]
34 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
39 do_checkpoint_insts=true
41 do_statistics_insts=true
44 function_trace_start=0
45 interrupts=system.cpu.interrupts
48 max_insts_all_threads=0
49 max_insts_any_thread=0
50 max_loads_all_threads=0
51 max_loads_any_thread=0
57 tracer=system.cpu.tracer
58 workload=system.cpu.workload
59 dcache_port=system.cpu.dcache.cpu_side
60 icache_port=system.cpu.icache.cpu_side
64 addr_ranges=0:18446744073709551615
73 prefetch_on_access=false
81 cpu_side=system.cpu.dcache_port
82 mem_side=system.cpu.toL2Bus.slave[1]
88 walker=system.cpu.dtb.walker
90 [system.cpu.dtb.walker]
91 type=X86PagetableWalker
94 port=system.cpu.toL2Bus.slave[3]
98 addr_ranges=0:18446744073709551615
107 prefetch_on_access=false
115 cpu_side=system.cpu.icache_port
116 mem_side=system.cpu.toL2Bus.slave[0]
118 [system.cpu.interrupts]
122 pio_addr=2305843009213693952
125 int_master=system.membus.slave[2]
126 int_slave=system.membus.master[2]
127 pio=system.membus.master[1]
136 walker=system.cpu.itb.walker
138 [system.cpu.itb.walker]
139 type=X86PagetableWalker
142 port=system.cpu.toL2Bus.slave[2]
146 addr_ranges=0:18446744073709551615
155 prefetch_on_access=false
163 cpu_side=system.cpu.toL2Bus.master[0]
164 mem_side=system.membus.slave[1]
171 use_default_range=false
173 master=system.cpu.l2cache.cpu_side
174 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
179 [system.cpu.workload]
182 cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing
187 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
190 max_stack_size=67108864
203 use_default_range=false
205 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
206 slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
212 conf_table_reported=false
219 port=system.membus.master[0]