2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.250954 # Number of seconds simulated
4 sim_ticks 250953957000 # Number of ticks simulated
5 final_tick 250953957000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 881800 # Simulator instruction rate (inst/s)
8 host_op_rate 1477977 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 1675544377 # Simulator tick rate (ticks/s)
10 host_mem_usage 333860 # Number of bytes of host memory used
11 host_seconds 149.77 # Real time elapsed on the host
12 sim_insts 132071193 # Number of instructions simulated
13 sim_ops 221363385 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 121280 # Number of bytes read from this memory
18 system.physmem.bytes_read::total 303040 # Number of bytes read from this memory
19 system.physmem.bytes_inst_read::cpu.inst 181760 # Number of instructions bytes read from this memory
20 system.physmem.bytes_inst_read::total 181760 # Number of instructions bytes read from this memory
21 system.physmem.num_reads::cpu.inst 2840 # Number of read requests responded to by this memory
22 system.physmem.num_reads::cpu.data 1895 # Number of read requests responded to by this memory
23 system.physmem.num_reads::total 4735 # Number of read requests responded to by this memory
24 system.physmem.bw_read::cpu.inst 724276 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_read::cpu.data 483276 # Total read bandwidth from this memory (bytes/s)
26 system.physmem.bw_read::total 1207552 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_inst_read::cpu.inst 724276 # Instruction read bandwidth from this memory (bytes/s)
28 system.physmem.bw_inst_read::total 724276 # Instruction read bandwidth from this memory (bytes/s)
29 system.physmem.bw_total::cpu.inst 724276 # Total bandwidth to/from this memory (bytes/s)
30 system.physmem.bw_total::cpu.data 483276 # Total bandwidth to/from this memory (bytes/s)
31 system.physmem.bw_total::total 1207552 # Total bandwidth to/from this memory (bytes/s)
32 system.membus.trans_dist::ReadReq 3160 # Transaction distribution
33 system.membus.trans_dist::ReadResp 3160 # Transaction distribution
34 system.membus.trans_dist::ReadExReq 1575 # Transaction distribution
35 system.membus.trans_dist::ReadExResp 1575 # Transaction distribution
36 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 # Packet count per connected master and slave (bytes)
37 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 # Packet count per connected master and slave (bytes)
38 system.membus.pkt_count::total 9470 # Packet count per connected master and slave (bytes)
39 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes)
40 system.membus.pkt_size_system.cpu.l2cache.mem_side::total 303040 # Cumulative packet size per connected master and slave (bytes)
41 system.membus.pkt_size::total 303040 # Cumulative packet size per connected master and slave (bytes)
42 system.membus.snoops 0 # Total snoops (count)
43 system.membus.snoop_fanout::samples 4735 # Request fanout histogram
44 system.membus.snoop_fanout::mean 0 # Request fanout histogram
45 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
46 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
47 system.membus.snoop_fanout::0 4735 100.00% 100.00% # Request fanout histogram
48 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
49 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
50 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
51 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
52 system.membus.snoop_fanout::total 4735 # Request fanout histogram
53 system.membus.reqLayer0.occupancy 4753500 # Layer occupancy (ticks)
54 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
55 system.membus.respLayer1.occupancy 42633500 # Layer occupancy (ticks)
56 system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
57 system.cpu_clk_domain.clock 500 # Clock period in ticks
58 system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
59 system.cpu.workload.num_syscalls 400 # Number of system calls
60 system.cpu.numCycles 501907914 # number of cpu cycles simulated
61 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
62 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
63 system.cpu.committedInsts 132071193 # Number of instructions committed
64 system.cpu.committedOps 221363385 # Number of ops (including micro ops) committed
65 system.cpu.num_int_alu_accesses 219019986 # Number of integer alu accesses
66 system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses
67 system.cpu.num_func_calls 1595632 # number of times a function call or return occured
68 system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls
69 system.cpu.num_int_insts 219019986 # number of integer instructions
70 system.cpu.num_fp_insts 2162459 # number of float instructions
71 system.cpu.num_int_register_reads 519996939 # number of times the integer registers were read
72 system.cpu.num_int_register_writes 201355989 # number of times the integer registers were written
73 system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read
74 system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written
75 system.cpu.num_cc_register_reads 96962463 # number of times the CC registers were read
76 system.cpu.num_cc_register_writes 56242058 # number of times the CC registers were written
77 system.cpu.num_mem_refs 77165304 # number of memory refs
78 system.cpu.num_load_insts 56649587 # Number of load instructions
79 system.cpu.num_store_insts 20515717 # Number of store instructions
80 system.cpu.num_idle_cycles 0 # Number of idle cycles
81 system.cpu.num_busy_cycles 501907914 # Number of busy cycles
82 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
83 system.cpu.idle_fraction 0 # Percentage of idle cycles
84 system.cpu.Branches 12326938 # Number of branches fetched
85 system.cpu.op_class::No_OpClass 1176721 0.53% 0.53% # Class of executed instruction
86 system.cpu.op_class::IntAlu 134111833 60.58% 61.12% # Class of executed instruction
87 system.cpu.op_class::IntMult 772953 0.35% 61.47% # Class of executed instruction
88 system.cpu.op_class::IntDiv 7031501 3.18% 64.64% # Class of executed instruction
89 system.cpu.op_class::FloatAdd 1105073 0.50% 65.14% # Class of executed instruction
90 system.cpu.op_class::FloatCmp 0 0.00% 65.14% # Class of executed instruction
91 system.cpu.op_class::FloatCvt 0 0.00% 65.14% # Class of executed instruction
92 system.cpu.op_class::FloatMult 0 0.00% 65.14% # Class of executed instruction
93 system.cpu.op_class::FloatDiv 0 0.00% 65.14% # Class of executed instruction
94 system.cpu.op_class::FloatSqrt 0 0.00% 65.14% # Class of executed instruction
95 system.cpu.op_class::SimdAdd 0 0.00% 65.14% # Class of executed instruction
96 system.cpu.op_class::SimdAddAcc 0 0.00% 65.14% # Class of executed instruction
97 system.cpu.op_class::SimdAlu 0 0.00% 65.14% # Class of executed instruction
98 system.cpu.op_class::SimdCmp 0 0.00% 65.14% # Class of executed instruction
99 system.cpu.op_class::SimdCvt 0 0.00% 65.14% # Class of executed instruction
100 system.cpu.op_class::SimdMisc 0 0.00% 65.14% # Class of executed instruction
101 system.cpu.op_class::SimdMult 0 0.00% 65.14% # Class of executed instruction
102 system.cpu.op_class::SimdMultAcc 0 0.00% 65.14% # Class of executed instruction
103 system.cpu.op_class::SimdShift 0 0.00% 65.14% # Class of executed instruction
104 system.cpu.op_class::SimdShiftAcc 0 0.00% 65.14% # Class of executed instruction
105 system.cpu.op_class::SimdSqrt 0 0.00% 65.14% # Class of executed instruction
106 system.cpu.op_class::SimdFloatAdd 0 0.00% 65.14% # Class of executed instruction
107 system.cpu.op_class::SimdFloatAlu 0 0.00% 65.14% # Class of executed instruction
108 system.cpu.op_class::SimdFloatCmp 0 0.00% 65.14% # Class of executed instruction
109 system.cpu.op_class::SimdFloatCvt 0 0.00% 65.14% # Class of executed instruction
110 system.cpu.op_class::SimdFloatDiv 0 0.00% 65.14% # Class of executed instruction
111 system.cpu.op_class::SimdFloatMisc 0 0.00% 65.14% # Class of executed instruction
112 system.cpu.op_class::SimdFloatMult 0 0.00% 65.14% # Class of executed instruction
113 system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.14% # Class of executed instruction
114 system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.14% # Class of executed instruction
115 system.cpu.op_class::MemRead 56649587 25.59% 90.73% # Class of executed instruction
116 system.cpu.op_class::MemWrite 20515717 9.27% 100.00% # Class of executed instruction
117 system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
118 system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
119 system.cpu.op_class::total 221363385 # Class of executed instruction
120 system.cpu.icache.tags.replacements 2836 # number of replacements
121 system.cpu.icache.tags.tagsinuse 1455.296642 # Cycle average of tags in use
122 system.cpu.icache.tags.total_refs 173489674 # Total number of references to valid blocks.
123 system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks.
124 system.cpu.icache.tags.avg_refs 36959.879421 # Average number of references to valid blocks.
125 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
126 system.cpu.icache.tags.occ_blocks::cpu.inst 1455.296642 # Average occupied blocks per requestor
127 system.cpu.icache.tags.occ_percent::cpu.inst 0.710594 # Average percentage of cache occupancy
128 system.cpu.icache.tags.occ_percent::total 0.710594 # Average percentage of cache occupancy
129 system.cpu.icache.tags.occ_task_id_blocks::1024 1858 # Occupied blocks per task id
130 system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
131 system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id
132 system.cpu.icache.tags.age_task_id_blocks_1024::2 498 # Occupied blocks per task id
133 system.cpu.icache.tags.age_task_id_blocks_1024::3 394 # Occupied blocks per task id
134 system.cpu.icache.tags.age_task_id_blocks_1024::4 869 # Occupied blocks per task id
135 system.cpu.icache.tags.occ_task_id_percent::1024 0.907227 # Percentage of cache occupancy per task id
136 system.cpu.icache.tags.tag_accesses 346993430 # Number of tag accesses
137 system.cpu.icache.tags.data_accesses 346993430 # Number of data accesses
138 system.cpu.icache.ReadReq_hits::cpu.inst 173489674 # number of ReadReq hits
139 system.cpu.icache.ReadReq_hits::total 173489674 # number of ReadReq hits
140 system.cpu.icache.demand_hits::cpu.inst 173489674 # number of demand (read+write) hits
141 system.cpu.icache.demand_hits::total 173489674 # number of demand (read+write) hits
142 system.cpu.icache.overall_hits::cpu.inst 173489674 # number of overall hits
143 system.cpu.icache.overall_hits::total 173489674 # number of overall hits
144 system.cpu.icache.ReadReq_misses::cpu.inst 4694 # number of ReadReq misses
145 system.cpu.icache.ReadReq_misses::total 4694 # number of ReadReq misses
146 system.cpu.icache.demand_misses::cpu.inst 4694 # number of demand (read+write) misses
147 system.cpu.icache.demand_misses::total 4694 # number of demand (read+write) misses
148 system.cpu.icache.overall_misses::cpu.inst 4694 # number of overall misses
149 system.cpu.icache.overall_misses::total 4694 # number of overall misses
150 system.cpu.icache.ReadReq_miss_latency::cpu.inst 180319000 # number of ReadReq miss cycles
151 system.cpu.icache.ReadReq_miss_latency::total 180319000 # number of ReadReq miss cycles
152 system.cpu.icache.demand_miss_latency::cpu.inst 180319000 # number of demand (read+write) miss cycles
153 system.cpu.icache.demand_miss_latency::total 180319000 # number of demand (read+write) miss cycles
154 system.cpu.icache.overall_miss_latency::cpu.inst 180319000 # number of overall miss cycles
155 system.cpu.icache.overall_miss_latency::total 180319000 # number of overall miss cycles
156 system.cpu.icache.ReadReq_accesses::cpu.inst 173494368 # number of ReadReq accesses(hits+misses)
157 system.cpu.icache.ReadReq_accesses::total 173494368 # number of ReadReq accesses(hits+misses)
158 system.cpu.icache.demand_accesses::cpu.inst 173494368 # number of demand (read+write) accesses
159 system.cpu.icache.demand_accesses::total 173494368 # number of demand (read+write) accesses
160 system.cpu.icache.overall_accesses::cpu.inst 173494368 # number of overall (read+write) accesses
161 system.cpu.icache.overall_accesses::total 173494368 # number of overall (read+write) accesses
162 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000027 # miss rate for ReadReq accesses
163 system.cpu.icache.ReadReq_miss_rate::total 0.000027 # miss rate for ReadReq accesses
164 system.cpu.icache.demand_miss_rate::cpu.inst 0.000027 # miss rate for demand accesses
165 system.cpu.icache.demand_miss_rate::total 0.000027 # miss rate for demand accesses
166 system.cpu.icache.overall_miss_rate::cpu.inst 0.000027 # miss rate for overall accesses
167 system.cpu.icache.overall_miss_rate::total 0.000027 # miss rate for overall accesses
168 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38414.784832 # average ReadReq miss latency
169 system.cpu.icache.ReadReq_avg_miss_latency::total 38414.784832 # average ReadReq miss latency
170 system.cpu.icache.demand_avg_miss_latency::cpu.inst 38414.784832 # average overall miss latency
171 system.cpu.icache.demand_avg_miss_latency::total 38414.784832 # average overall miss latency
172 system.cpu.icache.overall_avg_miss_latency::cpu.inst 38414.784832 # average overall miss latency
173 system.cpu.icache.overall_avg_miss_latency::total 38414.784832 # average overall miss latency
174 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
175 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
176 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
177 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
178 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
179 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
180 system.cpu.icache.fast_writes 0 # number of fast writes performed
181 system.cpu.icache.cache_copies 0 # number of cache copies performed
182 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4694 # number of ReadReq MSHR misses
183 system.cpu.icache.ReadReq_mshr_misses::total 4694 # number of ReadReq MSHR misses
184 system.cpu.icache.demand_mshr_misses::cpu.inst 4694 # number of demand (read+write) MSHR misses
185 system.cpu.icache.demand_mshr_misses::total 4694 # number of demand (read+write) MSHR misses
186 system.cpu.icache.overall_mshr_misses::cpu.inst 4694 # number of overall MSHR misses
187 system.cpu.icache.overall_mshr_misses::total 4694 # number of overall MSHR misses
188 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 170931000 # number of ReadReq MSHR miss cycles
189 system.cpu.icache.ReadReq_mshr_miss_latency::total 170931000 # number of ReadReq MSHR miss cycles
190 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 170931000 # number of demand (read+write) MSHR miss cycles
191 system.cpu.icache.demand_mshr_miss_latency::total 170931000 # number of demand (read+write) MSHR miss cycles
192 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 170931000 # number of overall MSHR miss cycles
193 system.cpu.icache.overall_mshr_miss_latency::total 170931000 # number of overall MSHR miss cycles
194 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for ReadReq accesses
195 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000027 # mshr miss rate for ReadReq accesses
196 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses
197 system.cpu.icache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
198 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses
199 system.cpu.icache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
200 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36414.784832 # average ReadReq mshr miss latency
201 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36414.784832 # average ReadReq mshr miss latency
202 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36414.784832 # average overall mshr miss latency
203 system.cpu.icache.demand_avg_mshr_miss_latency::total 36414.784832 # average overall mshr miss latency
204 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36414.784832 # average overall mshr miss latency
205 system.cpu.icache.overall_avg_mshr_miss_latency::total 36414.784832 # average overall mshr miss latency
206 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
207 system.cpu.l2cache.tags.replacements 0 # number of replacements
208 system.cpu.l2cache.tags.tagsinuse 2058.178686 # Cycle average of tags in use
209 system.cpu.l2cache.tags.total_refs 1862 # Total number of references to valid blocks.
210 system.cpu.l2cache.tags.sampled_refs 3164 # Sample count of references to valid blocks.
211 system.cpu.l2cache.tags.avg_refs 0.588496 # Average number of references to valid blocks.
212 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
213 system.cpu.l2cache.tags.occ_blocks::writebacks 0.021744 # Average occupied blocks per requestor
214 system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.978580 # Average occupied blocks per requestor
215 system.cpu.l2cache.tags.occ_blocks::cpu.data 228.178362 # Average occupied blocks per requestor
216 system.cpu.l2cache.tags.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy
217 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055847 # Average percentage of cache occupancy
218 system.cpu.l2cache.tags.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy
219 system.cpu.l2cache.tags.occ_percent::total 0.062811 # Average percentage of cache occupancy
220 system.cpu.l2cache.tags.occ_task_id_blocks::1024 3164 # Occupied blocks per task id
221 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
222 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id
223 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 513 # Occupied blocks per task id
224 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 516 # Occupied blocks per task id
225 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2064 # Occupied blocks per task id
226 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.096558 # Percentage of cache occupancy per task id
227 system.cpu.l2cache.tags.tag_accesses 57590 # Number of tag accesses
228 system.cpu.l2cache.tags.data_accesses 57590 # Number of data accesses
229 system.cpu.l2cache.ReadReq_hits::cpu.inst 1854 # number of ReadReq hits
230 system.cpu.l2cache.ReadReq_hits::cpu.data 7 # number of ReadReq hits
231 system.cpu.l2cache.ReadReq_hits::total 1861 # number of ReadReq hits
232 system.cpu.l2cache.Writeback_hits::writebacks 7 # number of Writeback hits
233 system.cpu.l2cache.Writeback_hits::total 7 # number of Writeback hits
234 system.cpu.l2cache.ReadExReq_hits::cpu.data 3 # number of ReadExReq hits
235 system.cpu.l2cache.ReadExReq_hits::total 3 # number of ReadExReq hits
236 system.cpu.l2cache.demand_hits::cpu.inst 1854 # number of demand (read+write) hits
237 system.cpu.l2cache.demand_hits::cpu.data 10 # number of demand (read+write) hits
238 system.cpu.l2cache.demand_hits::total 1864 # number of demand (read+write) hits
239 system.cpu.l2cache.overall_hits::cpu.inst 1854 # number of overall hits
240 system.cpu.l2cache.overall_hits::cpu.data 10 # number of overall hits
241 system.cpu.l2cache.overall_hits::total 1864 # number of overall hits
242 system.cpu.l2cache.ReadReq_misses::cpu.inst 2840 # number of ReadReq misses
243 system.cpu.l2cache.ReadReq_misses::cpu.data 320 # number of ReadReq misses
244 system.cpu.l2cache.ReadReq_misses::total 3160 # number of ReadReq misses
245 system.cpu.l2cache.ReadExReq_misses::cpu.data 1575 # number of ReadExReq misses
246 system.cpu.l2cache.ReadExReq_misses::total 1575 # number of ReadExReq misses
247 system.cpu.l2cache.demand_misses::cpu.inst 2840 # number of demand (read+write) misses
248 system.cpu.l2cache.demand_misses::cpu.data 1895 # number of demand (read+write) misses
249 system.cpu.l2cache.demand_misses::total 4735 # number of demand (read+write) misses
250 system.cpu.l2cache.overall_misses::cpu.inst 2840 # number of overall misses
251 system.cpu.l2cache.overall_misses::cpu.data 1895 # number of overall misses
252 system.cpu.l2cache.overall_misses::total 4735 # number of overall misses
253 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 147697000 # number of ReadReq miss cycles
254 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16641500 # number of ReadReq miss cycles
255 system.cpu.l2cache.ReadReq_miss_latency::total 164338500 # number of ReadReq miss cycles
256 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 81900000 # number of ReadExReq miss cycles
257 system.cpu.l2cache.ReadExReq_miss_latency::total 81900000 # number of ReadExReq miss cycles
258 system.cpu.l2cache.demand_miss_latency::cpu.inst 147697000 # number of demand (read+write) miss cycles
259 system.cpu.l2cache.demand_miss_latency::cpu.data 98541500 # number of demand (read+write) miss cycles
260 system.cpu.l2cache.demand_miss_latency::total 246238500 # number of demand (read+write) miss cycles
261 system.cpu.l2cache.overall_miss_latency::cpu.inst 147697000 # number of overall miss cycles
262 system.cpu.l2cache.overall_miss_latency::cpu.data 98541500 # number of overall miss cycles
263 system.cpu.l2cache.overall_miss_latency::total 246238500 # number of overall miss cycles
264 system.cpu.l2cache.ReadReq_accesses::cpu.inst 4694 # number of ReadReq accesses(hits+misses)
265 system.cpu.l2cache.ReadReq_accesses::cpu.data 327 # number of ReadReq accesses(hits+misses)
266 system.cpu.l2cache.ReadReq_accesses::total 5021 # number of ReadReq accesses(hits+misses)
267 system.cpu.l2cache.Writeback_accesses::writebacks 7 # number of Writeback accesses(hits+misses)
268 system.cpu.l2cache.Writeback_accesses::total 7 # number of Writeback accesses(hits+misses)
269 system.cpu.l2cache.ReadExReq_accesses::cpu.data 1578 # number of ReadExReq accesses(hits+misses)
270 system.cpu.l2cache.ReadExReq_accesses::total 1578 # number of ReadExReq accesses(hits+misses)
271 system.cpu.l2cache.demand_accesses::cpu.inst 4694 # number of demand (read+write) accesses
272 system.cpu.l2cache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses
273 system.cpu.l2cache.demand_accesses::total 6599 # number of demand (read+write) accesses
274 system.cpu.l2cache.overall_accesses::cpu.inst 4694 # number of overall (read+write) accesses
275 system.cpu.l2cache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses
276 system.cpu.l2cache.overall_accesses::total 6599 # number of overall (read+write) accesses
277 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.605028 # miss rate for ReadReq accesses
278 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.978593 # miss rate for ReadReq accesses
279 system.cpu.l2cache.ReadReq_miss_rate::total 0.629357 # miss rate for ReadReq accesses
280 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.998099 # miss rate for ReadExReq accesses
281 system.cpu.l2cache.ReadExReq_miss_rate::total 0.998099 # miss rate for ReadExReq accesses
282 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.605028 # miss rate for demand accesses
283 system.cpu.l2cache.demand_miss_rate::cpu.data 0.994751 # miss rate for demand accesses
284 system.cpu.l2cache.demand_miss_rate::total 0.717533 # miss rate for demand accesses
285 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.605028 # miss rate for overall accesses
286 system.cpu.l2cache.overall_miss_rate::cpu.data 0.994751 # miss rate for overall accesses
287 system.cpu.l2cache.overall_miss_rate::total 0.717533 # miss rate for overall accesses
288 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52005.985915 # average ReadReq miss latency
289 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52004.687500 # average ReadReq miss latency
290 system.cpu.l2cache.ReadReq_avg_miss_latency::total 52005.854430 # average ReadReq miss latency
291 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
292 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
293 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52005.985915 # average overall miss latency
294 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.791557 # average overall miss latency
295 system.cpu.l2cache.demand_avg_miss_latency::total 52003.907075 # average overall miss latency
296 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52005.985915 # average overall miss latency
297 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.791557 # average overall miss latency
298 system.cpu.l2cache.overall_avg_miss_latency::total 52003.907075 # average overall miss latency
299 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
300 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
301 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
302 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
303 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
304 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
305 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
306 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
307 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2840 # number of ReadReq MSHR misses
308 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 320 # number of ReadReq MSHR misses
309 system.cpu.l2cache.ReadReq_mshr_misses::total 3160 # number of ReadReq MSHR misses
310 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1575 # number of ReadExReq MSHR misses
311 system.cpu.l2cache.ReadExReq_mshr_misses::total 1575 # number of ReadExReq MSHR misses
312 system.cpu.l2cache.demand_mshr_misses::cpu.inst 2840 # number of demand (read+write) MSHR misses
313 system.cpu.l2cache.demand_mshr_misses::cpu.data 1895 # number of demand (read+write) MSHR misses
314 system.cpu.l2cache.demand_mshr_misses::total 4735 # number of demand (read+write) MSHR misses
315 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2840 # number of overall MSHR misses
316 system.cpu.l2cache.overall_mshr_misses::cpu.data 1895 # number of overall MSHR misses
317 system.cpu.l2cache.overall_mshr_misses::total 4735 # number of overall MSHR misses
318 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 113600000 # number of ReadReq MSHR miss cycles
319 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12800000 # number of ReadReq MSHR miss cycles
320 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 126400000 # number of ReadReq MSHR miss cycles
321 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 63000000 # number of ReadExReq MSHR miss cycles
322 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 63000000 # number of ReadExReq MSHR miss cycles
323 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 113600000 # number of demand (read+write) MSHR miss cycles
324 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 75800000 # number of demand (read+write) MSHR miss cycles
325 system.cpu.l2cache.demand_mshr_miss_latency::total 189400000 # number of demand (read+write) MSHR miss cycles
326 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 113600000 # number of overall MSHR miss cycles
327 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 75800000 # number of overall MSHR miss cycles
328 system.cpu.l2cache.overall_mshr_miss_latency::total 189400000 # number of overall MSHR miss cycles
329 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for ReadReq accesses
330 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.978593 # mshr miss rate for ReadReq accesses
331 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.629357 # mshr miss rate for ReadReq accesses
332 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.998099 # mshr miss rate for ReadExReq accesses
333 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.998099 # mshr miss rate for ReadExReq accesses
334 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for demand accesses
335 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for demand accesses
336 system.cpu.l2cache.demand_mshr_miss_rate::total 0.717533 # mshr miss rate for demand accesses
337 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for overall accesses
338 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for overall accesses
339 system.cpu.l2cache.overall_mshr_miss_rate::total 0.717533 # mshr miss rate for overall accesses
340 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
341 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
342 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
343 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
344 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
345 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
346 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
347 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
348 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
349 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
350 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
351 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
352 system.cpu.dcache.tags.replacements 41 # number of replacements
353 system.cpu.dcache.tags.tagsinuse 1363.457571 # Cycle average of tags in use
354 system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks.
355 system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks.
356 system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks.
357 system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
358 system.cpu.dcache.tags.occ_blocks::cpu.data 1363.457571 # Average occupied blocks per requestor
359 system.cpu.dcache.tags.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy
360 system.cpu.dcache.tags.occ_percent::total 0.332875 # Average percentage of cache occupancy
361 system.cpu.dcache.tags.occ_task_id_blocks::1024 1864 # Occupied blocks per task id
362 system.cpu.dcache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id
363 system.cpu.dcache.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id
364 system.cpu.dcache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id
365 system.cpu.dcache.tags.age_task_id_blocks_1024::3 471 # Occupied blocks per task id
366 system.cpu.dcache.tags.age_task_id_blocks_1024::4 1328 # Occupied blocks per task id
367 system.cpu.dcache.tags.occ_task_id_percent::1024 0.455078 # Percentage of cache occupancy per task id
368 system.cpu.dcache.tags.tag_accesses 154397377 # Number of tag accesses
369 system.cpu.dcache.tags.data_accesses 154397377 # Number of data accesses
370 system.cpu.dcache.ReadReq_hits::cpu.data 56681678 # number of ReadReq hits
371 system.cpu.dcache.ReadReq_hits::total 56681678 # number of ReadReq hits
372 system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits
373 system.cpu.dcache.WriteReq_hits::total 20514153 # number of WriteReq hits
374 system.cpu.dcache.demand_hits::cpu.data 77195831 # number of demand (read+write) hits
375 system.cpu.dcache.demand_hits::total 77195831 # number of demand (read+write) hits
376 system.cpu.dcache.overall_hits::cpu.data 77195831 # number of overall hits
377 system.cpu.dcache.overall_hits::total 77195831 # number of overall hits
378 system.cpu.dcache.ReadReq_misses::cpu.data 327 # number of ReadReq misses
379 system.cpu.dcache.ReadReq_misses::total 327 # number of ReadReq misses
380 system.cpu.dcache.WriteReq_misses::cpu.data 1578 # number of WriteReq misses
381 system.cpu.dcache.WriteReq_misses::total 1578 # number of WriteReq misses
382 system.cpu.dcache.demand_misses::cpu.data 1905 # number of demand (read+write) misses
383 system.cpu.dcache.demand_misses::total 1905 # number of demand (read+write) misses
384 system.cpu.dcache.overall_misses::cpu.data 1905 # number of overall misses
385 system.cpu.dcache.overall_misses::total 1905 # number of overall misses
386 system.cpu.dcache.ReadReq_miss_latency::cpu.data 17692500 # number of ReadReq miss cycles
387 system.cpu.dcache.ReadReq_miss_latency::total 17692500 # number of ReadReq miss cycles
388 system.cpu.dcache.WriteReq_miss_latency::cpu.data 86664000 # number of WriteReq miss cycles
389 system.cpu.dcache.WriteReq_miss_latency::total 86664000 # number of WriteReq miss cycles
390 system.cpu.dcache.demand_miss_latency::cpu.data 104356500 # number of demand (read+write) miss cycles
391 system.cpu.dcache.demand_miss_latency::total 104356500 # number of demand (read+write) miss cycles
392 system.cpu.dcache.overall_miss_latency::cpu.data 104356500 # number of overall miss cycles
393 system.cpu.dcache.overall_miss_latency::total 104356500 # number of overall miss cycles
394 system.cpu.dcache.ReadReq_accesses::cpu.data 56682005 # number of ReadReq accesses(hits+misses)
395 system.cpu.dcache.ReadReq_accesses::total 56682005 # number of ReadReq accesses(hits+misses)
396 system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
397 system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
398 system.cpu.dcache.demand_accesses::cpu.data 77197736 # number of demand (read+write) accesses
399 system.cpu.dcache.demand_accesses::total 77197736 # number of demand (read+write) accesses
400 system.cpu.dcache.overall_accesses::cpu.data 77197736 # number of overall (read+write) accesses
401 system.cpu.dcache.overall_accesses::total 77197736 # number of overall (read+write) accesses
402 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 # miss rate for ReadReq accesses
403 system.cpu.dcache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses
404 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 # miss rate for WriteReq accesses
405 system.cpu.dcache.WriteReq_miss_rate::total 0.000077 # miss rate for WriteReq accesses
406 system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses
407 system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses
408 system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses
409 system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses
410 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54105.504587 # average ReadReq miss latency
411 system.cpu.dcache.ReadReq_avg_miss_latency::total 54105.504587 # average ReadReq miss latency
412 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54920.152091 # average WriteReq miss latency
413 system.cpu.dcache.WriteReq_avg_miss_latency::total 54920.152091 # average WriteReq miss latency
414 system.cpu.dcache.demand_avg_miss_latency::cpu.data 54780.314961 # average overall miss latency
415 system.cpu.dcache.demand_avg_miss_latency::total 54780.314961 # average overall miss latency
416 system.cpu.dcache.overall_avg_miss_latency::cpu.data 54780.314961 # average overall miss latency
417 system.cpu.dcache.overall_avg_miss_latency::total 54780.314961 # average overall miss latency
418 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
419 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
420 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
421 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
422 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
423 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
424 system.cpu.dcache.fast_writes 0 # number of fast writes performed
425 system.cpu.dcache.cache_copies 0 # number of cache copies performed
426 system.cpu.dcache.writebacks::writebacks 7 # number of writebacks
427 system.cpu.dcache.writebacks::total 7 # number of writebacks
428 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 327 # number of ReadReq MSHR misses
429 system.cpu.dcache.ReadReq_mshr_misses::total 327 # number of ReadReq MSHR misses
430 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1578 # number of WriteReq MSHR misses
431 system.cpu.dcache.WriteReq_mshr_misses::total 1578 # number of WriteReq MSHR misses
432 system.cpu.dcache.demand_mshr_misses::cpu.data 1905 # number of demand (read+write) MSHR misses
433 system.cpu.dcache.demand_mshr_misses::total 1905 # number of demand (read+write) MSHR misses
434 system.cpu.dcache.overall_mshr_misses::cpu.data 1905 # number of overall MSHR misses
435 system.cpu.dcache.overall_mshr_misses::total 1905 # number of overall MSHR misses
436 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17038500 # number of ReadReq MSHR miss cycles
437 system.cpu.dcache.ReadReq_mshr_miss_latency::total 17038500 # number of ReadReq MSHR miss cycles
438 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83508000 # number of WriteReq MSHR miss cycles
439 system.cpu.dcache.WriteReq_mshr_miss_latency::total 83508000 # number of WriteReq MSHR miss cycles
440 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 100546500 # number of demand (read+write) MSHR miss cycles
441 system.cpu.dcache.demand_mshr_miss_latency::total 100546500 # number of demand (read+write) MSHR miss cycles
442 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 100546500 # number of overall MSHR miss cycles
443 system.cpu.dcache.overall_mshr_miss_latency::total 100546500 # number of overall MSHR miss cycles
444 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses
445 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses
446 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses
447 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000077 # mshr miss rate for WriteReq accesses
448 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
449 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
450 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
451 system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
452 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52105.504587 # average ReadReq mshr miss latency
453 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52105.504587 # average ReadReq mshr miss latency
454 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52920.152091 # average WriteReq mshr miss latency
455 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52920.152091 # average WriteReq mshr miss latency
456 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency
457 system.cpu.dcache.demand_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency
458 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency
459 system.cpu.dcache.overall_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency
460 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
461 system.cpu.toL2Bus.trans_dist::ReadReq 5021 # Transaction distribution
462 system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution
463 system.cpu.toL2Bus.trans_dist::Writeback 7 # Transaction distribution
464 system.cpu.toL2Bus.trans_dist::ReadExReq 1578 # Transaction distribution
465 system.cpu.toL2Bus.trans_dist::ReadExResp 1578 # Transaction distribution
466 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9388 # Packet count per connected master and slave (bytes)
467 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3817 # Packet count per connected master and slave (bytes)
468 system.cpu.toL2Bus.pkt_count::total 13205 # Packet count per connected master and slave (bytes)
469 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 300416 # Cumulative packet size per connected master and slave (bytes)
470 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 122368 # Cumulative packet size per connected master and slave (bytes)
471 system.cpu.toL2Bus.pkt_size::total 422784 # Cumulative packet size per connected master and slave (bytes)
472 system.cpu.toL2Bus.snoops 0 # Total snoops (count)
473 system.cpu.toL2Bus.snoop_fanout::samples 6606 # Request fanout histogram
474 system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
475 system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
476 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
477 system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
478 system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
479 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
480 system.cpu.toL2Bus.snoop_fanout::3 6606 100.00% 100.00% # Request fanout histogram
481 system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
482 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
483 system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
484 system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
485 system.cpu.toL2Bus.snoop_fanout::total 6606 # Request fanout histogram
486 system.cpu.toL2Bus.reqLayer0.occupancy 3310000 # Layer occupancy (ticks)
487 system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
488 system.cpu.toL2Bus.respLayer0.occupancy 7041000 # Layer occupancy (ticks)
489 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
490 system.cpu.toL2Bus.respLayer1.occupancy 2857500 # Layer occupancy (ticks)
491 system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
493 ---------- End Simulation Statistics ----------
projects / gem5.git / blob