2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.250954 # Number of seconds simulated
4 sim_ticks 250953957000 # Number of ticks simulated
5 final_tick 250953957000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 789102 # Simulator instruction rate (inst/s)
8 host_op_rate 1322606 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 1499404446 # Simulator tick rate (ticks/s)
10 host_mem_usage 274284 # Number of bytes of host memory used
11 host_seconds 167.37 # Real time elapsed on the host
12 sim_insts 132071193 # Number of instructions simulated
13 sim_ops 221363385 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 121280 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 303040 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 181760 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 181760 # Number of instructions bytes read from this memory
19 system.physmem.num_reads::cpu.inst 2840 # Number of read requests responded to by this memory
20 system.physmem.num_reads::cpu.data 1895 # Number of read requests responded to by this memory
21 system.physmem.num_reads::total 4735 # Number of read requests responded to by this memory
22 system.physmem.bw_read::cpu.inst 724276 # Total read bandwidth from this memory (bytes/s)
23 system.physmem.bw_read::cpu.data 483276 # Total read bandwidth from this memory (bytes/s)
24 system.physmem.bw_read::total 1207552 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_inst_read::cpu.inst 724276 # Instruction read bandwidth from this memory (bytes/s)
26 system.physmem.bw_inst_read::total 724276 # Instruction read bandwidth from this memory (bytes/s)
27 system.physmem.bw_total::cpu.inst 724276 # Total bandwidth to/from this memory (bytes/s)
28 system.physmem.bw_total::cpu.data 483276 # Total bandwidth to/from this memory (bytes/s)
29 system.physmem.bw_total::total 1207552 # Total bandwidth to/from this memory (bytes/s)
30 system.membus.throughput 1207552 # Throughput (bytes/s)
31 system.membus.trans_dist::ReadReq 3160 # Transaction distribution
32 system.membus.trans_dist::ReadResp 3160 # Transaction distribution
33 system.membus.trans_dist::ReadExReq 1575 # Transaction distribution
34 system.membus.trans_dist::ReadExResp 1575 # Transaction distribution
35 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 # Packet count per connected master and slave (bytes)
36 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 # Packet count per connected master and slave (bytes)
37 system.membus.pkt_count::total 9470 # Packet count per connected master and slave (bytes)
38 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes)
39 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 303040 # Cumulative packet size per connected master and slave (bytes)
40 system.membus.tot_pkt_size::total 303040 # Cumulative packet size per connected master and slave (bytes)
41 system.membus.data_through_bus 303040 # Total data (bytes)
42 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
43 system.membus.reqLayer0.occupancy 4753500 # Layer occupancy (ticks)
44 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
45 system.membus.respLayer1.occupancy 42633500 # Layer occupancy (ticks)
46 system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
47 system.cpu.workload.num_syscalls 400 # Number of system calls
48 system.cpu.numCycles 501907914 # number of cpu cycles simulated
49 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
50 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
51 system.cpu.committedInsts 132071193 # Number of instructions committed
52 system.cpu.committedOps 221363385 # Number of ops (including micro ops) committed
53 system.cpu.num_int_alu_accesses 219019986 # Number of integer alu accesses
54 system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses
55 system.cpu.num_func_calls 1595632 # number of times a function call or return occured
56 system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls
57 system.cpu.num_int_insts 219019986 # number of integer instructions
58 system.cpu.num_fp_insts 2162459 # number of float instructions
59 system.cpu.num_int_register_reads 519996939 # number of times the integer registers were read
60 system.cpu.num_int_register_writes 201355989 # number of times the integer registers were written
61 system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read
62 system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written
63 system.cpu.num_cc_register_reads 96962463 # number of times the CC registers were read
64 system.cpu.num_cc_register_writes 56242058 # number of times the CC registers were written
65 system.cpu.num_mem_refs 77165304 # number of memory refs
66 system.cpu.num_load_insts 56649587 # Number of load instructions
67 system.cpu.num_store_insts 20515717 # Number of store instructions
68 system.cpu.num_idle_cycles 0 # Number of idle cycles
69 system.cpu.num_busy_cycles 501907914 # Number of busy cycles
70 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
71 system.cpu.idle_fraction 0 # Percentage of idle cycles
72 system.cpu.icache.tags.replacements 2836 # number of replacements
73 system.cpu.icache.tags.tagsinuse 1455.296642 # Cycle average of tags in use
74 system.cpu.icache.tags.total_refs 173489674 # Total number of references to valid blocks.
75 system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks.
76 system.cpu.icache.tags.avg_refs 36959.879421 # Average number of references to valid blocks.
77 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
78 system.cpu.icache.tags.occ_blocks::cpu.inst 1455.296642 # Average occupied blocks per requestor
79 system.cpu.icache.tags.occ_percent::cpu.inst 0.710594 # Average percentage of cache occupancy
80 system.cpu.icache.tags.occ_percent::total 0.710594 # Average percentage of cache occupancy
81 system.cpu.icache.ReadReq_hits::cpu.inst 173489674 # number of ReadReq hits
82 system.cpu.icache.ReadReq_hits::total 173489674 # number of ReadReq hits
83 system.cpu.icache.demand_hits::cpu.inst 173489674 # number of demand (read+write) hits
84 system.cpu.icache.demand_hits::total 173489674 # number of demand (read+write) hits
85 system.cpu.icache.overall_hits::cpu.inst 173489674 # number of overall hits
86 system.cpu.icache.overall_hits::total 173489674 # number of overall hits
87 system.cpu.icache.ReadReq_misses::cpu.inst 4694 # number of ReadReq misses
88 system.cpu.icache.ReadReq_misses::total 4694 # number of ReadReq misses
89 system.cpu.icache.demand_misses::cpu.inst 4694 # number of demand (read+write) misses
90 system.cpu.icache.demand_misses::total 4694 # number of demand (read+write) misses
91 system.cpu.icache.overall_misses::cpu.inst 4694 # number of overall misses
92 system.cpu.icache.overall_misses::total 4694 # number of overall misses
93 system.cpu.icache.ReadReq_miss_latency::cpu.inst 180319000 # number of ReadReq miss cycles
94 system.cpu.icache.ReadReq_miss_latency::total 180319000 # number of ReadReq miss cycles
95 system.cpu.icache.demand_miss_latency::cpu.inst 180319000 # number of demand (read+write) miss cycles
96 system.cpu.icache.demand_miss_latency::total 180319000 # number of demand (read+write) miss cycles
97 system.cpu.icache.overall_miss_latency::cpu.inst 180319000 # number of overall miss cycles
98 system.cpu.icache.overall_miss_latency::total 180319000 # number of overall miss cycles
99 system.cpu.icache.ReadReq_accesses::cpu.inst 173494368 # number of ReadReq accesses(hits+misses)
100 system.cpu.icache.ReadReq_accesses::total 173494368 # number of ReadReq accesses(hits+misses)
101 system.cpu.icache.demand_accesses::cpu.inst 173494368 # number of demand (read+write) accesses
102 system.cpu.icache.demand_accesses::total 173494368 # number of demand (read+write) accesses
103 system.cpu.icache.overall_accesses::cpu.inst 173494368 # number of overall (read+write) accesses
104 system.cpu.icache.overall_accesses::total 173494368 # number of overall (read+write) accesses
105 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000027 # miss rate for ReadReq accesses
106 system.cpu.icache.ReadReq_miss_rate::total 0.000027 # miss rate for ReadReq accesses
107 system.cpu.icache.demand_miss_rate::cpu.inst 0.000027 # miss rate for demand accesses
108 system.cpu.icache.demand_miss_rate::total 0.000027 # miss rate for demand accesses
109 system.cpu.icache.overall_miss_rate::cpu.inst 0.000027 # miss rate for overall accesses
110 system.cpu.icache.overall_miss_rate::total 0.000027 # miss rate for overall accesses
111 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38414.784832 # average ReadReq miss latency
112 system.cpu.icache.ReadReq_avg_miss_latency::total 38414.784832 # average ReadReq miss latency
113 system.cpu.icache.demand_avg_miss_latency::cpu.inst 38414.784832 # average overall miss latency
114 system.cpu.icache.demand_avg_miss_latency::total 38414.784832 # average overall miss latency
115 system.cpu.icache.overall_avg_miss_latency::cpu.inst 38414.784832 # average overall miss latency
116 system.cpu.icache.overall_avg_miss_latency::total 38414.784832 # average overall miss latency
117 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
118 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
119 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
120 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
121 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
122 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
123 system.cpu.icache.fast_writes 0 # number of fast writes performed
124 system.cpu.icache.cache_copies 0 # number of cache copies performed
125 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4694 # number of ReadReq MSHR misses
126 system.cpu.icache.ReadReq_mshr_misses::total 4694 # number of ReadReq MSHR misses
127 system.cpu.icache.demand_mshr_misses::cpu.inst 4694 # number of demand (read+write) MSHR misses
128 system.cpu.icache.demand_mshr_misses::total 4694 # number of demand (read+write) MSHR misses
129 system.cpu.icache.overall_mshr_misses::cpu.inst 4694 # number of overall MSHR misses
130 system.cpu.icache.overall_mshr_misses::total 4694 # number of overall MSHR misses
131 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 170931000 # number of ReadReq MSHR miss cycles
132 system.cpu.icache.ReadReq_mshr_miss_latency::total 170931000 # number of ReadReq MSHR miss cycles
133 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 170931000 # number of demand (read+write) MSHR miss cycles
134 system.cpu.icache.demand_mshr_miss_latency::total 170931000 # number of demand (read+write) MSHR miss cycles
135 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 170931000 # number of overall MSHR miss cycles
136 system.cpu.icache.overall_mshr_miss_latency::total 170931000 # number of overall MSHR miss cycles
137 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for ReadReq accesses
138 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000027 # mshr miss rate for ReadReq accesses
139 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses
140 system.cpu.icache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
141 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses
142 system.cpu.icache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
143 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36414.784832 # average ReadReq mshr miss latency
144 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36414.784832 # average ReadReq mshr miss latency
145 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36414.784832 # average overall mshr miss latency
146 system.cpu.icache.demand_avg_mshr_miss_latency::total 36414.784832 # average overall mshr miss latency
147 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36414.784832 # average overall mshr miss latency
148 system.cpu.icache.overall_avg_mshr_miss_latency::total 36414.784832 # average overall mshr miss latency
149 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
150 system.cpu.l2cache.tags.replacements 0 # number of replacements
151 system.cpu.l2cache.tags.tagsinuse 2058.178686 # Cycle average of tags in use
152 system.cpu.l2cache.tags.total_refs 1862 # Total number of references to valid blocks.
153 system.cpu.l2cache.tags.sampled_refs 3164 # Sample count of references to valid blocks.
154 system.cpu.l2cache.tags.avg_refs 0.588496 # Average number of references to valid blocks.
155 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
156 system.cpu.l2cache.tags.occ_blocks::writebacks 0.021744 # Average occupied blocks per requestor
157 system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.978580 # Average occupied blocks per requestor
158 system.cpu.l2cache.tags.occ_blocks::cpu.data 228.178362 # Average occupied blocks per requestor
159 system.cpu.l2cache.tags.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy
160 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055847 # Average percentage of cache occupancy
161 system.cpu.l2cache.tags.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy
162 system.cpu.l2cache.tags.occ_percent::total 0.062811 # Average percentage of cache occupancy
163 system.cpu.l2cache.ReadReq_hits::cpu.inst 1854 # number of ReadReq hits
164 system.cpu.l2cache.ReadReq_hits::cpu.data 7 # number of ReadReq hits
165 system.cpu.l2cache.ReadReq_hits::total 1861 # number of ReadReq hits
166 system.cpu.l2cache.Writeback_hits::writebacks 7 # number of Writeback hits
167 system.cpu.l2cache.Writeback_hits::total 7 # number of Writeback hits
168 system.cpu.l2cache.ReadExReq_hits::cpu.data 3 # number of ReadExReq hits
169 system.cpu.l2cache.ReadExReq_hits::total 3 # number of ReadExReq hits
170 system.cpu.l2cache.demand_hits::cpu.inst 1854 # number of demand (read+write) hits
171 system.cpu.l2cache.demand_hits::cpu.data 10 # number of demand (read+write) hits
172 system.cpu.l2cache.demand_hits::total 1864 # number of demand (read+write) hits
173 system.cpu.l2cache.overall_hits::cpu.inst 1854 # number of overall hits
174 system.cpu.l2cache.overall_hits::cpu.data 10 # number of overall hits
175 system.cpu.l2cache.overall_hits::total 1864 # number of overall hits
176 system.cpu.l2cache.ReadReq_misses::cpu.inst 2840 # number of ReadReq misses
177 system.cpu.l2cache.ReadReq_misses::cpu.data 320 # number of ReadReq misses
178 system.cpu.l2cache.ReadReq_misses::total 3160 # number of ReadReq misses
179 system.cpu.l2cache.ReadExReq_misses::cpu.data 1575 # number of ReadExReq misses
180 system.cpu.l2cache.ReadExReq_misses::total 1575 # number of ReadExReq misses
181 system.cpu.l2cache.demand_misses::cpu.inst 2840 # number of demand (read+write) misses
182 system.cpu.l2cache.demand_misses::cpu.data 1895 # number of demand (read+write) misses
183 system.cpu.l2cache.demand_misses::total 4735 # number of demand (read+write) misses
184 system.cpu.l2cache.overall_misses::cpu.inst 2840 # number of overall misses
185 system.cpu.l2cache.overall_misses::cpu.data 1895 # number of overall misses
186 system.cpu.l2cache.overall_misses::total 4735 # number of overall misses
187 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 147697000 # number of ReadReq miss cycles
188 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16641500 # number of ReadReq miss cycles
189 system.cpu.l2cache.ReadReq_miss_latency::total 164338500 # number of ReadReq miss cycles
190 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 81900000 # number of ReadExReq miss cycles
191 system.cpu.l2cache.ReadExReq_miss_latency::total 81900000 # number of ReadExReq miss cycles
192 system.cpu.l2cache.demand_miss_latency::cpu.inst 147697000 # number of demand (read+write) miss cycles
193 system.cpu.l2cache.demand_miss_latency::cpu.data 98541500 # number of demand (read+write) miss cycles
194 system.cpu.l2cache.demand_miss_latency::total 246238500 # number of demand (read+write) miss cycles
195 system.cpu.l2cache.overall_miss_latency::cpu.inst 147697000 # number of overall miss cycles
196 system.cpu.l2cache.overall_miss_latency::cpu.data 98541500 # number of overall miss cycles
197 system.cpu.l2cache.overall_miss_latency::total 246238500 # number of overall miss cycles
198 system.cpu.l2cache.ReadReq_accesses::cpu.inst 4694 # number of ReadReq accesses(hits+misses)
199 system.cpu.l2cache.ReadReq_accesses::cpu.data 327 # number of ReadReq accesses(hits+misses)
200 system.cpu.l2cache.ReadReq_accesses::total 5021 # number of ReadReq accesses(hits+misses)
201 system.cpu.l2cache.Writeback_accesses::writebacks 7 # number of Writeback accesses(hits+misses)
202 system.cpu.l2cache.Writeback_accesses::total 7 # number of Writeback accesses(hits+misses)
203 system.cpu.l2cache.ReadExReq_accesses::cpu.data 1578 # number of ReadExReq accesses(hits+misses)
204 system.cpu.l2cache.ReadExReq_accesses::total 1578 # number of ReadExReq accesses(hits+misses)
205 system.cpu.l2cache.demand_accesses::cpu.inst 4694 # number of demand (read+write) accesses
206 system.cpu.l2cache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses
207 system.cpu.l2cache.demand_accesses::total 6599 # number of demand (read+write) accesses
208 system.cpu.l2cache.overall_accesses::cpu.inst 4694 # number of overall (read+write) accesses
209 system.cpu.l2cache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses
210 system.cpu.l2cache.overall_accesses::total 6599 # number of overall (read+write) accesses
211 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.605028 # miss rate for ReadReq accesses
212 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.978593 # miss rate for ReadReq accesses
213 system.cpu.l2cache.ReadReq_miss_rate::total 0.629357 # miss rate for ReadReq accesses
214 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.998099 # miss rate for ReadExReq accesses
215 system.cpu.l2cache.ReadExReq_miss_rate::total 0.998099 # miss rate for ReadExReq accesses
216 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.605028 # miss rate for demand accesses
217 system.cpu.l2cache.demand_miss_rate::cpu.data 0.994751 # miss rate for demand accesses
218 system.cpu.l2cache.demand_miss_rate::total 0.717533 # miss rate for demand accesses
219 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.605028 # miss rate for overall accesses
220 system.cpu.l2cache.overall_miss_rate::cpu.data 0.994751 # miss rate for overall accesses
221 system.cpu.l2cache.overall_miss_rate::total 0.717533 # miss rate for overall accesses
222 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52005.985915 # average ReadReq miss latency
223 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52004.687500 # average ReadReq miss latency
224 system.cpu.l2cache.ReadReq_avg_miss_latency::total 52005.854430 # average ReadReq miss latency
225 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
226 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
227 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52005.985915 # average overall miss latency
228 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.791557 # average overall miss latency
229 system.cpu.l2cache.demand_avg_miss_latency::total 52003.907075 # average overall miss latency
230 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52005.985915 # average overall miss latency
231 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.791557 # average overall miss latency
232 system.cpu.l2cache.overall_avg_miss_latency::total 52003.907075 # average overall miss latency
233 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
234 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
235 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
236 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
237 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
238 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
239 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
240 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
241 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2840 # number of ReadReq MSHR misses
242 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 320 # number of ReadReq MSHR misses
243 system.cpu.l2cache.ReadReq_mshr_misses::total 3160 # number of ReadReq MSHR misses
244 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1575 # number of ReadExReq MSHR misses
245 system.cpu.l2cache.ReadExReq_mshr_misses::total 1575 # number of ReadExReq MSHR misses
246 system.cpu.l2cache.demand_mshr_misses::cpu.inst 2840 # number of demand (read+write) MSHR misses
247 system.cpu.l2cache.demand_mshr_misses::cpu.data 1895 # number of demand (read+write) MSHR misses
248 system.cpu.l2cache.demand_mshr_misses::total 4735 # number of demand (read+write) MSHR misses
249 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2840 # number of overall MSHR misses
250 system.cpu.l2cache.overall_mshr_misses::cpu.data 1895 # number of overall MSHR misses
251 system.cpu.l2cache.overall_mshr_misses::total 4735 # number of overall MSHR misses
252 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 113600000 # number of ReadReq MSHR miss cycles
253 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12800000 # number of ReadReq MSHR miss cycles
254 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 126400000 # number of ReadReq MSHR miss cycles
255 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 63000000 # number of ReadExReq MSHR miss cycles
256 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 63000000 # number of ReadExReq MSHR miss cycles
257 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 113600000 # number of demand (read+write) MSHR miss cycles
258 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 75800000 # number of demand (read+write) MSHR miss cycles
259 system.cpu.l2cache.demand_mshr_miss_latency::total 189400000 # number of demand (read+write) MSHR miss cycles
260 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 113600000 # number of overall MSHR miss cycles
261 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 75800000 # number of overall MSHR miss cycles
262 system.cpu.l2cache.overall_mshr_miss_latency::total 189400000 # number of overall MSHR miss cycles
263 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for ReadReq accesses
264 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.978593 # mshr miss rate for ReadReq accesses
265 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.629357 # mshr miss rate for ReadReq accesses
266 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.998099 # mshr miss rate for ReadExReq accesses
267 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.998099 # mshr miss rate for ReadExReq accesses
268 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for demand accesses
269 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for demand accesses
270 system.cpu.l2cache.demand_mshr_miss_rate::total 0.717533 # mshr miss rate for demand accesses
271 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for overall accesses
272 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for overall accesses
273 system.cpu.l2cache.overall_mshr_miss_rate::total 0.717533 # mshr miss rate for overall accesses
274 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
275 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
276 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
277 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
278 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
279 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
280 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
281 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
282 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
283 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
284 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
285 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
286 system.cpu.dcache.tags.replacements 41 # number of replacements
287 system.cpu.dcache.tags.tagsinuse 1363.457571 # Cycle average of tags in use
288 system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks.
289 system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks.
290 system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks.
291 system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
292 system.cpu.dcache.tags.occ_blocks::cpu.data 1363.457571 # Average occupied blocks per requestor
293 system.cpu.dcache.tags.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy
294 system.cpu.dcache.tags.occ_percent::total 0.332875 # Average percentage of cache occupancy
295 system.cpu.dcache.ReadReq_hits::cpu.data 56681678 # number of ReadReq hits
296 system.cpu.dcache.ReadReq_hits::total 56681678 # number of ReadReq hits
297 system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits
298 system.cpu.dcache.WriteReq_hits::total 20514153 # number of WriteReq hits
299 system.cpu.dcache.demand_hits::cpu.data 77195831 # number of demand (read+write) hits
300 system.cpu.dcache.demand_hits::total 77195831 # number of demand (read+write) hits
301 system.cpu.dcache.overall_hits::cpu.data 77195831 # number of overall hits
302 system.cpu.dcache.overall_hits::total 77195831 # number of overall hits
303 system.cpu.dcache.ReadReq_misses::cpu.data 327 # number of ReadReq misses
304 system.cpu.dcache.ReadReq_misses::total 327 # number of ReadReq misses
305 system.cpu.dcache.WriteReq_misses::cpu.data 1578 # number of WriteReq misses
306 system.cpu.dcache.WriteReq_misses::total 1578 # number of WriteReq misses
307 system.cpu.dcache.demand_misses::cpu.data 1905 # number of demand (read+write) misses
308 system.cpu.dcache.demand_misses::total 1905 # number of demand (read+write) misses
309 system.cpu.dcache.overall_misses::cpu.data 1905 # number of overall misses
310 system.cpu.dcache.overall_misses::total 1905 # number of overall misses
311 system.cpu.dcache.ReadReq_miss_latency::cpu.data 17692500 # number of ReadReq miss cycles
312 system.cpu.dcache.ReadReq_miss_latency::total 17692500 # number of ReadReq miss cycles
313 system.cpu.dcache.WriteReq_miss_latency::cpu.data 86664000 # number of WriteReq miss cycles
314 system.cpu.dcache.WriteReq_miss_latency::total 86664000 # number of WriteReq miss cycles
315 system.cpu.dcache.demand_miss_latency::cpu.data 104356500 # number of demand (read+write) miss cycles
316 system.cpu.dcache.demand_miss_latency::total 104356500 # number of demand (read+write) miss cycles
317 system.cpu.dcache.overall_miss_latency::cpu.data 104356500 # number of overall miss cycles
318 system.cpu.dcache.overall_miss_latency::total 104356500 # number of overall miss cycles
319 system.cpu.dcache.ReadReq_accesses::cpu.data 56682005 # number of ReadReq accesses(hits+misses)
320 system.cpu.dcache.ReadReq_accesses::total 56682005 # number of ReadReq accesses(hits+misses)
321 system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
322 system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
323 system.cpu.dcache.demand_accesses::cpu.data 77197736 # number of demand (read+write) accesses
324 system.cpu.dcache.demand_accesses::total 77197736 # number of demand (read+write) accesses
325 system.cpu.dcache.overall_accesses::cpu.data 77197736 # number of overall (read+write) accesses
326 system.cpu.dcache.overall_accesses::total 77197736 # number of overall (read+write) accesses
327 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 # miss rate for ReadReq accesses
328 system.cpu.dcache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses
329 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 # miss rate for WriteReq accesses
330 system.cpu.dcache.WriteReq_miss_rate::total 0.000077 # miss rate for WriteReq accesses
331 system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses
332 system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses
333 system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses
334 system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses
335 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54105.504587 # average ReadReq miss latency
336 system.cpu.dcache.ReadReq_avg_miss_latency::total 54105.504587 # average ReadReq miss latency
337 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54920.152091 # average WriteReq miss latency
338 system.cpu.dcache.WriteReq_avg_miss_latency::total 54920.152091 # average WriteReq miss latency
339 system.cpu.dcache.demand_avg_miss_latency::cpu.data 54780.314961 # average overall miss latency
340 system.cpu.dcache.demand_avg_miss_latency::total 54780.314961 # average overall miss latency
341 system.cpu.dcache.overall_avg_miss_latency::cpu.data 54780.314961 # average overall miss latency
342 system.cpu.dcache.overall_avg_miss_latency::total 54780.314961 # average overall miss latency
343 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
344 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
345 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
346 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
347 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
348 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
349 system.cpu.dcache.fast_writes 0 # number of fast writes performed
350 system.cpu.dcache.cache_copies 0 # number of cache copies performed
351 system.cpu.dcache.writebacks::writebacks 7 # number of writebacks
352 system.cpu.dcache.writebacks::total 7 # number of writebacks
353 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 327 # number of ReadReq MSHR misses
354 system.cpu.dcache.ReadReq_mshr_misses::total 327 # number of ReadReq MSHR misses
355 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1578 # number of WriteReq MSHR misses
356 system.cpu.dcache.WriteReq_mshr_misses::total 1578 # number of WriteReq MSHR misses
357 system.cpu.dcache.demand_mshr_misses::cpu.data 1905 # number of demand (read+write) MSHR misses
358 system.cpu.dcache.demand_mshr_misses::total 1905 # number of demand (read+write) MSHR misses
359 system.cpu.dcache.overall_mshr_misses::cpu.data 1905 # number of overall MSHR misses
360 system.cpu.dcache.overall_mshr_misses::total 1905 # number of overall MSHR misses
361 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17038500 # number of ReadReq MSHR miss cycles
362 system.cpu.dcache.ReadReq_mshr_miss_latency::total 17038500 # number of ReadReq MSHR miss cycles
363 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83508000 # number of WriteReq MSHR miss cycles
364 system.cpu.dcache.WriteReq_mshr_miss_latency::total 83508000 # number of WriteReq MSHR miss cycles
365 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 100546500 # number of demand (read+write) MSHR miss cycles
366 system.cpu.dcache.demand_mshr_miss_latency::total 100546500 # number of demand (read+write) MSHR miss cycles
367 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 100546500 # number of overall MSHR miss cycles
368 system.cpu.dcache.overall_mshr_miss_latency::total 100546500 # number of overall MSHR miss cycles
369 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses
370 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses
371 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses
372 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000077 # mshr miss rate for WriteReq accesses
373 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
374 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
375 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
376 system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
377 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52105.504587 # average ReadReq mshr miss latency
378 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52105.504587 # average ReadReq mshr miss latency
379 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52920.152091 # average WriteReq mshr miss latency
380 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52920.152091 # average WriteReq mshr miss latency
381 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency
382 system.cpu.dcache.demand_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency
383 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency
384 system.cpu.dcache.overall_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency
385 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
386 system.cpu.toL2Bus.throughput 1684707 # Throughput (bytes/s)
387 system.cpu.toL2Bus.trans_dist::ReadReq 5021 # Transaction distribution
388 system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution
389 system.cpu.toL2Bus.trans_dist::Writeback 7 # Transaction distribution
390 system.cpu.toL2Bus.trans_dist::ReadExReq 1578 # Transaction distribution
391 system.cpu.toL2Bus.trans_dist::ReadExResp 1578 # Transaction distribution
392 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9388 # Packet count per connected master and slave (bytes)
393 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3817 # Packet count per connected master and slave (bytes)
394 system.cpu.toL2Bus.pkt_count::total 13205 # Packet count per connected master and slave (bytes)
395 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 300416 # Cumulative packet size per connected master and slave (bytes)
396 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 122368 # Cumulative packet size per connected master and slave (bytes)
397 system.cpu.toL2Bus.tot_pkt_size::total 422784 # Cumulative packet size per connected master and slave (bytes)
398 system.cpu.toL2Bus.data_through_bus 422784 # Total data (bytes)
399 system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
400 system.cpu.toL2Bus.reqLayer0.occupancy 3310000 # Layer occupancy (ticks)
401 system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
402 system.cpu.toL2Bus.respLayer0.occupancy 7041000 # Layer occupancy (ticks)
403 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
404 system.cpu.toL2Bus.respLayer1.occupancy 2857500 # Layer occupancy (ticks)
405 system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
407 ---------- End Simulation Statistics ----------
projects / gem5.git / blob