2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.250961 # Number of seconds simulated
4 sim_ticks 250960631000 # Number of ticks simulated
5 final_tick 250960631000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 361817 # Simulator instruction rate (inst/s)
8 host_op_rate 606437 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 687521912 # Simulator tick rate (ticks/s)
10 host_mem_usage 255672 # Number of bytes of host memory used
11 host_seconds 365.02 # Real time elapsed on the host
12 sim_insts 132071228 # Number of instructions simulated
13 sim_ops 221363018 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read 303040 # Number of bytes read from this memory
15 system.physmem.bytes_inst_read 181760 # Number of instructions bytes read from this memory
16 system.physmem.bytes_written 0 # Number of bytes written to this memory
17 system.physmem.num_reads 4735 # Number of read requests responded to by this memory
18 system.physmem.num_writes 0 # Number of write requests responded to by this memory
19 system.physmem.num_other 0 # Number of other requests responded to by this memory
20 system.physmem.bw_read 1207520 # Total read bandwidth from this memory (bytes/s)
21 system.physmem.bw_inst_read 724257 # Instruction read bandwidth from this memory (bytes/s)
22 system.physmem.bw_total 1207520 # Total bandwidth to/from this memory (bytes/s)
23 system.cpu.workload.num_syscalls 400 # Number of system calls
24 system.cpu.numCycles 501921262 # number of cpu cycles simulated
25 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
26 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
27 system.cpu.committedInsts 132071228 # Number of instructions committed
28 system.cpu.committedOps 221363018 # Number of ops (including micro ops) committed
29 system.cpu.num_int_alu_accesses 220339607 # Number of integer alu accesses
30 system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses
31 system.cpu.num_func_calls 0 # number of times a function call or return occured
32 system.cpu.num_conditional_control_insts 8268471 # number of instructions that are conditional controls
33 system.cpu.num_int_insts 220339607 # number of integer instructions
34 system.cpu.num_fp_insts 2162459 # number of float instructions
35 system.cpu.num_int_register_reads 705008823 # number of times the integer registers were read
36 system.cpu.num_int_register_writes 318312586 # number of times the integer registers were written
37 system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read
38 system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written
39 system.cpu.num_mem_refs 77165306 # number of memory refs
40 system.cpu.num_load_insts 56649590 # Number of load instructions
41 system.cpu.num_store_insts 20515716 # Number of store instructions
42 system.cpu.num_idle_cycles 0 # Number of idle cycles
43 system.cpu.num_busy_cycles 501921262 # Number of busy cycles
44 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
45 system.cpu.idle_fraction 0 # Percentage of idle cycles
46 system.cpu.icache.replacements 2836 # number of replacements
47 system.cpu.icache.tagsinuse 1455.289108 # Cycle average of tags in use
48 system.cpu.icache.total_refs 173489718 # Total number of references to valid blocks.
49 system.cpu.icache.sampled_refs 4694 # Sample count of references to valid blocks.
50 system.cpu.icache.avg_refs 36959.888794 # Average number of references to valid blocks.
51 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
52 system.cpu.icache.occ_blocks::cpu.inst 1455.289108 # Average occupied blocks per requestor
53 system.cpu.icache.occ_percent::cpu.inst 0.710590 # Average percentage of cache occupancy
54 system.cpu.icache.occ_percent::total 0.710590 # Average percentage of cache occupancy
55 system.cpu.icache.ReadReq_hits::cpu.inst 173489718 # number of ReadReq hits
56 system.cpu.icache.ReadReq_hits::total 173489718 # number of ReadReq hits
57 system.cpu.icache.demand_hits::cpu.inst 173489718 # number of demand (read+write) hits
58 system.cpu.icache.demand_hits::total 173489718 # number of demand (read+write) hits
59 system.cpu.icache.overall_hits::cpu.inst 173489718 # number of overall hits
60 system.cpu.icache.overall_hits::total 173489718 # number of overall hits
61 system.cpu.icache.ReadReq_misses::cpu.inst 4694 # number of ReadReq misses
62 system.cpu.icache.ReadReq_misses::total 4694 # number of ReadReq misses
63 system.cpu.icache.demand_misses::cpu.inst 4694 # number of demand (read+write) misses
64 system.cpu.icache.demand_misses::total 4694 # number of demand (read+write) misses
65 system.cpu.icache.overall_misses::cpu.inst 4694 # number of overall misses
66 system.cpu.icache.overall_misses::total 4694 # number of overall misses
67 system.cpu.icache.ReadReq_miss_latency::cpu.inst 185041500 # number of ReadReq miss cycles
68 system.cpu.icache.ReadReq_miss_latency::total 185041500 # number of ReadReq miss cycles
69 system.cpu.icache.demand_miss_latency::cpu.inst 185041500 # number of demand (read+write) miss cycles
70 system.cpu.icache.demand_miss_latency::total 185041500 # number of demand (read+write) miss cycles
71 system.cpu.icache.overall_miss_latency::cpu.inst 185041500 # number of overall miss cycles
72 system.cpu.icache.overall_miss_latency::total 185041500 # number of overall miss cycles
73 system.cpu.icache.ReadReq_accesses::cpu.inst 173494412 # number of ReadReq accesses(hits+misses)
74 system.cpu.icache.ReadReq_accesses::total 173494412 # number of ReadReq accesses(hits+misses)
75 system.cpu.icache.demand_accesses::cpu.inst 173494412 # number of demand (read+write) accesses
76 system.cpu.icache.demand_accesses::total 173494412 # number of demand (read+write) accesses
77 system.cpu.icache.overall_accesses::cpu.inst 173494412 # number of overall (read+write) accesses
78 system.cpu.icache.overall_accesses::total 173494412 # number of overall (read+write) accesses
79 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000027 # miss rate for ReadReq accesses
80 system.cpu.icache.demand_miss_rate::cpu.inst 0.000027 # miss rate for demand accesses
81 system.cpu.icache.overall_miss_rate::cpu.inst 0.000027 # miss rate for overall accesses
82 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39420.856412 # average ReadReq miss latency
83 system.cpu.icache.demand_avg_miss_latency::cpu.inst 39420.856412 # average overall miss latency
84 system.cpu.icache.overall_avg_miss_latency::cpu.inst 39420.856412 # average overall miss latency
85 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
86 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
87 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
88 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
89 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
90 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
91 system.cpu.icache.fast_writes 0 # number of fast writes performed
92 system.cpu.icache.cache_copies 0 # number of cache copies performed
93 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4694 # number of ReadReq MSHR misses
94 system.cpu.icache.ReadReq_mshr_misses::total 4694 # number of ReadReq MSHR misses
95 system.cpu.icache.demand_mshr_misses::cpu.inst 4694 # number of demand (read+write) MSHR misses
96 system.cpu.icache.demand_mshr_misses::total 4694 # number of demand (read+write) MSHR misses
97 system.cpu.icache.overall_mshr_misses::cpu.inst 4694 # number of overall MSHR misses
98 system.cpu.icache.overall_mshr_misses::total 4694 # number of overall MSHR misses
99 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 170928000 # number of ReadReq MSHR miss cycles
100 system.cpu.icache.ReadReq_mshr_miss_latency::total 170928000 # number of ReadReq MSHR miss cycles
101 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 170928000 # number of demand (read+write) MSHR miss cycles
102 system.cpu.icache.demand_mshr_miss_latency::total 170928000 # number of demand (read+write) MSHR miss cycles
103 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 170928000 # number of overall MSHR miss cycles
104 system.cpu.icache.overall_mshr_miss_latency::total 170928000 # number of overall MSHR miss cycles
105 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for ReadReq accesses
106 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses
107 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses
108 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36414.145718 # average ReadReq mshr miss latency
109 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36414.145718 # average overall mshr miss latency
110 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36414.145718 # average overall mshr miss latency
111 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
112 system.cpu.dcache.replacements 41 # number of replacements
113 system.cpu.dcache.tagsinuse 1363.451495 # Cycle average of tags in use
114 system.cpu.dcache.total_refs 77195833 # Total number of references to valid blocks.
115 system.cpu.dcache.sampled_refs 1905 # Sample count of references to valid blocks.
116 system.cpu.dcache.avg_refs 40522.746982 # Average number of references to valid blocks.
117 system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
118 system.cpu.dcache.occ_blocks::cpu.data 1363.451495 # Average occupied blocks per requestor
119 system.cpu.dcache.occ_percent::cpu.data 0.332874 # Average percentage of cache occupancy
120 system.cpu.dcache.occ_percent::total 0.332874 # Average percentage of cache occupancy
121 system.cpu.dcache.ReadReq_hits::cpu.data 56681681 # number of ReadReq hits
122 system.cpu.dcache.ReadReq_hits::total 56681681 # number of ReadReq hits
123 system.cpu.dcache.WriteReq_hits::cpu.data 20514152 # number of WriteReq hits
124 system.cpu.dcache.WriteReq_hits::total 20514152 # number of WriteReq hits
125 system.cpu.dcache.demand_hits::cpu.data 77195833 # number of demand (read+write) hits
126 system.cpu.dcache.demand_hits::total 77195833 # number of demand (read+write) hits
127 system.cpu.dcache.overall_hits::cpu.data 77195833 # number of overall hits
128 system.cpu.dcache.overall_hits::total 77195833 # number of overall hits
129 system.cpu.dcache.ReadReq_misses::cpu.data 327 # number of ReadReq misses
130 system.cpu.dcache.ReadReq_misses::total 327 # number of ReadReq misses
131 system.cpu.dcache.WriteReq_misses::cpu.data 1578 # number of WriteReq misses
132 system.cpu.dcache.WriteReq_misses::total 1578 # number of WriteReq misses
133 system.cpu.dcache.demand_misses::cpu.data 1905 # number of demand (read+write) misses
134 system.cpu.dcache.demand_misses::total 1905 # number of demand (read+write) misses
135 system.cpu.dcache.overall_misses::cpu.data 1905 # number of overall misses
136 system.cpu.dcache.overall_misses::total 1905 # number of overall misses
137 system.cpu.dcache.ReadReq_miss_latency::cpu.data 18020000 # number of ReadReq miss cycles
138 system.cpu.dcache.ReadReq_miss_latency::total 18020000 # number of ReadReq miss cycles
139 system.cpu.dcache.WriteReq_miss_latency::cpu.data 88242000 # number of WriteReq miss cycles
140 system.cpu.dcache.WriteReq_miss_latency::total 88242000 # number of WriteReq miss cycles
141 system.cpu.dcache.demand_miss_latency::cpu.data 106262000 # number of demand (read+write) miss cycles
142 system.cpu.dcache.demand_miss_latency::total 106262000 # number of demand (read+write) miss cycles
143 system.cpu.dcache.overall_miss_latency::cpu.data 106262000 # number of overall miss cycles
144 system.cpu.dcache.overall_miss_latency::total 106262000 # number of overall miss cycles
145 system.cpu.dcache.ReadReq_accesses::cpu.data 56682008 # number of ReadReq accesses(hits+misses)
146 system.cpu.dcache.ReadReq_accesses::total 56682008 # number of ReadReq accesses(hits+misses)
147 system.cpu.dcache.WriteReq_accesses::cpu.data 20515730 # number of WriteReq accesses(hits+misses)
148 system.cpu.dcache.WriteReq_accesses::total 20515730 # number of WriteReq accesses(hits+misses)
149 system.cpu.dcache.demand_accesses::cpu.data 77197738 # number of demand (read+write) accesses
150 system.cpu.dcache.demand_accesses::total 77197738 # number of demand (read+write) accesses
151 system.cpu.dcache.overall_accesses::cpu.data 77197738 # number of overall (read+write) accesses
152 system.cpu.dcache.overall_accesses::total 77197738 # number of overall (read+write) accesses
153 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 # miss rate for ReadReq accesses
154 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 # miss rate for WriteReq accesses
155 system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses
156 system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses
157 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55107.033639 # average ReadReq miss latency
158 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55920.152091 # average WriteReq miss latency
159 system.cpu.dcache.demand_avg_miss_latency::cpu.data 55780.577428 # average overall miss latency
160 system.cpu.dcache.overall_avg_miss_latency::cpu.data 55780.577428 # average overall miss latency
161 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
162 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
163 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
164 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
165 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
166 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
167 system.cpu.dcache.fast_writes 0 # number of fast writes performed
168 system.cpu.dcache.cache_copies 0 # number of cache copies performed
169 system.cpu.dcache.writebacks::writebacks 7 # number of writebacks
170 system.cpu.dcache.writebacks::total 7 # number of writebacks
171 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 327 # number of ReadReq MSHR misses
172 system.cpu.dcache.ReadReq_mshr_misses::total 327 # number of ReadReq MSHR misses
173 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1578 # number of WriteReq MSHR misses
174 system.cpu.dcache.WriteReq_mshr_misses::total 1578 # number of WriteReq MSHR misses
175 system.cpu.dcache.demand_mshr_misses::cpu.data 1905 # number of demand (read+write) MSHR misses
176 system.cpu.dcache.demand_mshr_misses::total 1905 # number of demand (read+write) MSHR misses
177 system.cpu.dcache.overall_mshr_misses::cpu.data 1905 # number of overall MSHR misses
178 system.cpu.dcache.overall_mshr_misses::total 1905 # number of overall MSHR misses
179 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17038500 # number of ReadReq MSHR miss cycles
180 system.cpu.dcache.ReadReq_mshr_miss_latency::total 17038500 # number of ReadReq MSHR miss cycles
181 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83508000 # number of WriteReq MSHR miss cycles
182 system.cpu.dcache.WriteReq_mshr_miss_latency::total 83508000 # number of WriteReq MSHR miss cycles
183 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 100546500 # number of demand (read+write) MSHR miss cycles
184 system.cpu.dcache.demand_mshr_miss_latency::total 100546500 # number of demand (read+write) MSHR miss cycles
185 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 100546500 # number of overall MSHR miss cycles
186 system.cpu.dcache.overall_mshr_miss_latency::total 100546500 # number of overall MSHR miss cycles
187 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses
188 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses
189 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
190 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
191 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52105.504587 # average ReadReq mshr miss latency
192 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52920.152091 # average WriteReq mshr miss latency
193 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency
194 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency
195 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
196 system.cpu.l2cache.replacements 0 # number of replacements
197 system.cpu.l2cache.tagsinuse 2058.168190 # Cycle average of tags in use
198 system.cpu.l2cache.total_refs 1861 # Total number of references to valid blocks.
199 system.cpu.l2cache.sampled_refs 3164 # Sample count of references to valid blocks.
200 system.cpu.l2cache.avg_refs 0.588180 # Average number of references to valid blocks.
201 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
202 system.cpu.l2cache.occ_blocks::writebacks 0.021756 # Average occupied blocks per requestor
203 system.cpu.l2cache.occ_blocks::cpu.inst 1829.968899 # Average occupied blocks per requestor
204 system.cpu.l2cache.occ_blocks::cpu.data 228.177535 # Average occupied blocks per requestor
205 system.cpu.l2cache.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy
206 system.cpu.l2cache.occ_percent::cpu.inst 0.055846 # Average percentage of cache occupancy
207 system.cpu.l2cache.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy
208 system.cpu.l2cache.occ_percent::total 0.062810 # Average percentage of cache occupancy
209 system.cpu.l2cache.ReadReq_hits::cpu.inst 1854 # number of ReadReq hits
210 system.cpu.l2cache.ReadReq_hits::cpu.data 7 # number of ReadReq hits
211 system.cpu.l2cache.ReadReq_hits::total 1861 # number of ReadReq hits
212 system.cpu.l2cache.Writeback_hits::writebacks 7 # number of Writeback hits
213 system.cpu.l2cache.Writeback_hits::total 7 # number of Writeback hits
214 system.cpu.l2cache.ReadExReq_hits::cpu.data 3 # number of ReadExReq hits
215 system.cpu.l2cache.ReadExReq_hits::total 3 # number of ReadExReq hits
216 system.cpu.l2cache.demand_hits::cpu.inst 1854 # number of demand (read+write) hits
217 system.cpu.l2cache.demand_hits::cpu.data 10 # number of demand (read+write) hits
218 system.cpu.l2cache.demand_hits::total 1864 # number of demand (read+write) hits
219 system.cpu.l2cache.overall_hits::cpu.inst 1854 # number of overall hits
220 system.cpu.l2cache.overall_hits::cpu.data 10 # number of overall hits
221 system.cpu.l2cache.overall_hits::total 1864 # number of overall hits
222 system.cpu.l2cache.ReadReq_misses::cpu.inst 2840 # number of ReadReq misses
223 system.cpu.l2cache.ReadReq_misses::cpu.data 320 # number of ReadReq misses
224 system.cpu.l2cache.ReadReq_misses::total 3160 # number of ReadReq misses
225 system.cpu.l2cache.ReadExReq_misses::cpu.data 1575 # number of ReadExReq misses
226 system.cpu.l2cache.ReadExReq_misses::total 1575 # number of ReadExReq misses
227 system.cpu.l2cache.demand_misses::cpu.inst 2840 # number of demand (read+write) misses
228 system.cpu.l2cache.demand_misses::cpu.data 1895 # number of demand (read+write) misses
229 system.cpu.l2cache.demand_misses::total 4735 # number of demand (read+write) misses
230 system.cpu.l2cache.overall_misses::cpu.inst 2840 # number of overall misses
231 system.cpu.l2cache.overall_misses::cpu.data 1895 # number of overall misses
232 system.cpu.l2cache.overall_misses::total 4735 # number of overall misses
233 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 147694000 # number of ReadReq miss cycles
234 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16641500 # number of ReadReq miss cycles
235 system.cpu.l2cache.ReadReq_miss_latency::total 164335500 # number of ReadReq miss cycles
236 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 81900000 # number of ReadExReq miss cycles
237 system.cpu.l2cache.ReadExReq_miss_latency::total 81900000 # number of ReadExReq miss cycles
238 system.cpu.l2cache.demand_miss_latency::cpu.inst 147694000 # number of demand (read+write) miss cycles
239 system.cpu.l2cache.demand_miss_latency::cpu.data 98541500 # number of demand (read+write) miss cycles
240 system.cpu.l2cache.demand_miss_latency::total 246235500 # number of demand (read+write) miss cycles
241 system.cpu.l2cache.overall_miss_latency::cpu.inst 147694000 # number of overall miss cycles
242 system.cpu.l2cache.overall_miss_latency::cpu.data 98541500 # number of overall miss cycles
243 system.cpu.l2cache.overall_miss_latency::total 246235500 # number of overall miss cycles
244 system.cpu.l2cache.ReadReq_accesses::cpu.inst 4694 # number of ReadReq accesses(hits+misses)
245 system.cpu.l2cache.ReadReq_accesses::cpu.data 327 # number of ReadReq accesses(hits+misses)
246 system.cpu.l2cache.ReadReq_accesses::total 5021 # number of ReadReq accesses(hits+misses)
247 system.cpu.l2cache.Writeback_accesses::writebacks 7 # number of Writeback accesses(hits+misses)
248 system.cpu.l2cache.Writeback_accesses::total 7 # number of Writeback accesses(hits+misses)
249 system.cpu.l2cache.ReadExReq_accesses::cpu.data 1578 # number of ReadExReq accesses(hits+misses)
250 system.cpu.l2cache.ReadExReq_accesses::total 1578 # number of ReadExReq accesses(hits+misses)
251 system.cpu.l2cache.demand_accesses::cpu.inst 4694 # number of demand (read+write) accesses
252 system.cpu.l2cache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses
253 system.cpu.l2cache.demand_accesses::total 6599 # number of demand (read+write) accesses
254 system.cpu.l2cache.overall_accesses::cpu.inst 4694 # number of overall (read+write) accesses
255 system.cpu.l2cache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses
256 system.cpu.l2cache.overall_accesses::total 6599 # number of overall (read+write) accesses
257 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.605028 # miss rate for ReadReq accesses
258 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.978593 # miss rate for ReadReq accesses
259 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.998099 # miss rate for ReadExReq accesses
260 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.605028 # miss rate for demand accesses
261 system.cpu.l2cache.demand_miss_rate::cpu.data 0.994751 # miss rate for demand accesses
262 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.605028 # miss rate for overall accesses
263 system.cpu.l2cache.overall_miss_rate::cpu.data 0.994751 # miss rate for overall accesses
264 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52004.929577 # average ReadReq miss latency
265 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52004.687500 # average ReadReq miss latency
266 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
267 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52004.929577 # average overall miss latency
268 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.791557 # average overall miss latency
269 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52004.929577 # average overall miss latency
270 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.791557 # average overall miss latency
271 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
272 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
273 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
274 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
275 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
276 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
277 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
278 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
279 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2840 # number of ReadReq MSHR misses
280 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 320 # number of ReadReq MSHR misses
281 system.cpu.l2cache.ReadReq_mshr_misses::total 3160 # number of ReadReq MSHR misses
282 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1575 # number of ReadExReq MSHR misses
283 system.cpu.l2cache.ReadExReq_mshr_misses::total 1575 # number of ReadExReq MSHR misses
284 system.cpu.l2cache.demand_mshr_misses::cpu.inst 2840 # number of demand (read+write) MSHR misses
285 system.cpu.l2cache.demand_mshr_misses::cpu.data 1895 # number of demand (read+write) MSHR misses
286 system.cpu.l2cache.demand_mshr_misses::total 4735 # number of demand (read+write) MSHR misses
287 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2840 # number of overall MSHR misses
288 system.cpu.l2cache.overall_mshr_misses::cpu.data 1895 # number of overall MSHR misses
289 system.cpu.l2cache.overall_mshr_misses::total 4735 # number of overall MSHR misses
290 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 113600000 # number of ReadReq MSHR miss cycles
291 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12800000 # number of ReadReq MSHR miss cycles
292 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 126400000 # number of ReadReq MSHR miss cycles
293 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 63000000 # number of ReadExReq MSHR miss cycles
294 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 63000000 # number of ReadExReq MSHR miss cycles
295 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 113600000 # number of demand (read+write) MSHR miss cycles
296 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 75800000 # number of demand (read+write) MSHR miss cycles
297 system.cpu.l2cache.demand_mshr_miss_latency::total 189400000 # number of demand (read+write) MSHR miss cycles
298 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 113600000 # number of overall MSHR miss cycles
299 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 75800000 # number of overall MSHR miss cycles
300 system.cpu.l2cache.overall_mshr_miss_latency::total 189400000 # number of overall MSHR miss cycles
301 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for ReadReq accesses
302 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.978593 # mshr miss rate for ReadReq accesses
303 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.998099 # mshr miss rate for ReadExReq accesses
304 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for demand accesses
305 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for demand accesses
306 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for overall accesses
307 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for overall accesses
308 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
309 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
310 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
311 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
312 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
313 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
314 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
315 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
317 ---------- End Simulation Statistics ----------
projects / gem5.git / blob