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Add ability to override verilog mode for verific -f command
[yosys.git] / tests / lut / check_map.ys
1 simplemap
2 equiv_opt -assert techmap -D LUT_WIDTH=4 -map +/cmp2lut.v
3 design -load postopt
4 equiv_opt -assert techmap -D LUT_WIDTH=4 -map +/gate2lut.v
5 design -load postopt
6 select -assert-count 0 t:* t:$lut %d