Merge pull request #1143 from YosysHQ/clifford/fix1135
[yosys.git] / tests / lut / map_cmp.v
1 module top(...);
2 input [3:0] a;
3
4 output o1_1 = 4'b1010 <= a;
5 output o1_2 = 4'b1010 < a;
6 output o1_3 = 4'b1010 >= a;
7 output o1_4 = 4'b1010 > a;
8 output o1_5 = 4'b1010 == a;
9 output o1_6 = 4'b1010 != a;
10
11 output o2_1 = a <= 4'b1010;
12 output o2_2 = a < 4'b1010;
13 output o2_3 = a >= 4'b1010;
14 output o2_4 = a > 4'b1010;
15 output o2_5 = a == 4'b1010;
16 output o2_6 = a != 4'b1010;
17
18 output o3_1 = 4'sb0101 <= $signed(a);
19 output o3_2 = 4'sb0101 < $signed(a);
20 output o3_3 = 4'sb0101 >= $signed(a);
21 output o3_4 = 4'sb0101 > $signed(a);
22 output o3_5 = 4'sb0101 == $signed(a);
23 output o3_6 = 4'sb0101 != $signed(a);
24
25 output o4_1 = $signed(a) <= 4'sb0000;
26 output o4_2 = $signed(a) < 4'sb0000;
27 output o4_3 = $signed(a) >= 4'sb0000;
28 output o4_4 = $signed(a) > 4'sb0000;
29 endmodule