tests/memories/amber23_sram_byte_en.v

   1 //////////////////////////////////////////////////////////////////
   2 //                                                              //
   3 //  Generic Library SRAM with per byte write enable             //
   4 //                                                              //
   5 //  This file is part of the Amber project                      //
   6 //  http://www.opencores.org/project,amber                      //
   7 //                                                              //
   8 //  Description                                                 //
   9 //  Configurable depth and width. The DATA_WIDTH must be a      //
  10 //  multiple of 8.                                              //
  11 //                                                              //
  12 //  Author(s):                                                  //
  13 //      - Conor Santifort, csantifort.amber@gmail.com           //
  14 //                                                              //
  15 //////////////////////////////////////////////////////////////////
  16 //                                                              //
  17 // Copyright (C) 2010 Authors and OPENCORES.ORG                 //
  18 //                                                              //
  19 // This source file may be used and distributed without         //
  20 // restriction provided that this copyright statement is not    //
  21 // removed from the file and that any derivative work contains  //
  22 // the original copyright notice and the associated disclaimer. //
  23 //                                                              //
  24 // This source file is free software; you can redistribute it   //
  25 // and/or modify it under the terms of the GNU Lesser General   //
  26 // Public License as published by the Free Software Foundation; //
  27 // either version 2.1 of the License, or (at your option) any   //
  28 // later version.                                               //
  29 //                                                              //
  30 // This source is distributed in the hope that it will be       //
  31 // useful, but WITHOUT ANY WARRANTY; without even the implied   //
  32 // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
  33 // PURPOSE.  See the GNU Lesser General Public License for more //
  34 // details.                                                     //
  35 //                                                              //
  36 // You should have received a copy of the GNU Lesser General    //
  37 // Public License along with this source; if not, download it   //
  38 // from http://www.opencores.org/lgpl.shtml                     //
  39 //                                                              //
  40 //////////////////////////////////////////////////////////////////
  41
  42 // expect-wr-ports 1
  43 // expect-rd-ports 1
  44
  45 module generic_sram_byte_en
  46 #(
  47 parameter DATA_WIDTH    = 32,
  48 parameter ADDRESS_WIDTH = 4
  49 )
  50
  51 (
  52 input                           i_clk,
  53 input      [DATA_WIDTH-1:0]     i_write_data,
  54 input                           i_write_enable,
  55 input      [ADDRESS_WIDTH-1:0]  i_address,
  56 input      [DATA_WIDTH/8-1:0]   i_byte_enable,
  57 output reg [DATA_WIDTH-1:0]     o_read_data
  58     );
  59
  60 reg [DATA_WIDTH-1:0]   mem  [0:2**ADDRESS_WIDTH-1];
  61 integer i;
  62
  63 always @(posedge i_clk)
  64     begin
  65     // read
  66     o_read_data <= i_write_enable ? {DATA_WIDTH{1'd0}} : mem[i_address];
  67
  68     // write
  69     if (i_write_enable)
  70         for (i=0;i<DATA_WIDTH/8;i=i+1)
  71             begin
  72             mem[i_address][i*8+0] <= i_byte_enable[i] ? i_write_data[i*8+0] : mem[i_address][i*8+0] ;
  73             mem[i_address][i*8+1] <= i_byte_enable[i] ? i_write_data[i*8+1] : mem[i_address][i*8+1] ;
  74             mem[i_address][i*8+2] <= i_byte_enable[i] ? i_write_data[i*8+2] : mem[i_address][i*8+2] ;
  75             mem[i_address][i*8+3] <= i_byte_enable[i] ? i_write_data[i*8+3] : mem[i_address][i*8+3] ;
  76             mem[i_address][i*8+4] <= i_byte_enable[i] ? i_write_data[i*8+4] : mem[i_address][i*8+4] ;
  77             mem[i_address][i*8+5] <= i_byte_enable[i] ? i_write_data[i*8+5] : mem[i_address][i*8+5] ;
  78             mem[i_address][i*8+6] <= i_byte_enable[i] ? i_write_data[i*8+6] : mem[i_address][i*8+6] ;
  79             mem[i_address][i*8+7] <= i_byte_enable[i] ? i_write_data[i*8+7] : mem[i_address][i*8+7] ;
  80             end
  81     end
  82
  83 endmodule
  84