tests/memories/firrtl_938.v

   1 module top
   2 (
   3         input [7:0] data_a,
   4         input [6:1] addr_a,
   5         input we_a, clk,
   6         output reg [7:0] q_a
   7 );
   8         // Declare the RAM variable
   9         reg [7:0] ram[63:0];
  10
  11         // Port A
  12         always @ (posedge clk)
  13         begin
  14                 if (we_a)
  15                 begin
  16                         ram[addr_a] <= data_a;
  17                         q_a <= data_a;
  18                 end
  19                         q_a <= ram[addr_a];
  20         end
  21
  22 endmodule