tests/memories/no_implicit_en.v

   1 // expect-wr-ports 1
   2 // expect-rd-ports 2
   3
   4 module test(clk, rd_addr, rd_data, cp_addr, wr_addr, wr_en, wr_data);
   5
   6 input clk;
   7
   8 input [3:0] rd_addr;
   9 output reg [31:0] rd_data;
  10
  11 input [3:0] cp_addr, wr_addr, wr_en;
  12 input [31:0] wr_data;
  13
  14 reg [31:0] mem [0:15];
  15
  16 always @(posedge clk) begin
  17         mem[wr_addr][ 7: 0] <= wr_en[0] ? wr_data[ 7: 0] : mem[cp_addr][ 7: 0];
  18         mem[wr_addr][15: 8] <= wr_en[1] ? wr_data[15: 8] : mem[cp_addr][15: 8];
  19         mem[wr_addr][23:16] <= wr_en[2] ? wr_data[23:16] : mem[cp_addr][23:16];
  20         mem[wr_addr][31:24] <= wr_en[3] ? wr_data[31:24] : mem[cp_addr][31:24];
  21         rd_data <= mem[rd_addr];
  22 end
  23
  24 endmodule