tests/memories/shared_ports.v

   1 // expect-wr-ports 1
   2 // expect-rd-ports 1
   3
   4 module test(
   5         input clk,
   6         input wr_en1, wr_en2, wr_en3,
   7         input [3:0] wr_addr1, wr_addr2, wr_addr3,
   8         input [15:0] wr_data,
   9         input [3:0] rd_addr,
  10         output reg [31:0] rd_data
  11 );
  12
  13 reg [31:0] mem [0:15];
  14
  15 always @(posedge clk) begin
  16         if (wr_en1)
  17                 mem[wr_addr1][15:0] <= wr_data;
  18         else if (wr_en2)
  19                 mem[wr_addr2][23:8] <= wr_data;
  20         else if (wr_en3)
  21                 mem[wr_addr3][31:16] <= wr_data;
  22         rd_data <= mem[rd_addr];
  23 end
  24
  25 endmodule