tests/memories/simple_sram_byte_en.v

   1 // expect-wr-ports 1
   2 // expect-rd-ports 1
   3
   4 module generic_sram_byte_en #(
   5         parameter DATA_WIDTH    = 32,
   6         parameter ADDRESS_WIDTH = 4
   7 ) (
   8         input                           i_clk,
   9         input      [DATA_WIDTH-1:0]     i_write_data,
  10         input                           i_write_enable,
  11         input      [ADDRESS_WIDTH-1:0]  i_address,
  12         input      [DATA_WIDTH/8-1:0]   i_byte_enable,
  13         output reg [DATA_WIDTH-1:0]     o_read_data
  14 );
  15
  16 reg [DATA_WIDTH-1:0] mem [0:2**ADDRESS_WIDTH-1];
  17 integer i;
  18
  19 always @(posedge i_clk) begin
  20         for (i=0;i<DATA_WIDTH/8;i=i+1)
  21                 if (i_write_enable && i_byte_enable[i])
  22                         mem[i_address][i*8 +: 8] <= i_write_data[i*8 +: 8];
  23         o_read_data <= mem[i_address];
  24 end
  25
  26 endmodule