tests/memories/wide_read_trans.v

   1 // expect-wr-ports 1
   2 // expect-rd-ports 4
   3 // expect-rd-wide-continuation 4'1110
   4
   5 module test(
   6         input clk,
   7         input re,
   8         input we,
   9         input [5:0] ra,
  10         input [7:0] wa,
  11         input [7:0] wd,
  12         output reg [31:0] rd
  13 );
  14
  15 reg [7:0] mem[0:255];
  16
  17 always @(posedge clk) begin
  18         if (re) begin
  19                 rd[7:0] <= mem[{ra, 2'b00}];
  20                 rd[15:8] <= mem[{ra, 2'b01}];
  21                 rd[23:16] <= mem[{ra, 2'b10}];
  22                 rd[31:24] <= mem[{ra, 2'b11}];
  23                 if (we && wa == {ra, 2'b00})
  24                         rd [7:0] <= wd;
  25                 if (we && wa == {ra, 2'b01})
  26                         rd [15:8] <= wd;
  27                 if (we && wa == {ra, 2'b10})
  28                         rd [23:16] <= wd;
  29                 if (we && wa == {ra, 2'b11})
  30                         rd [31:24] <= wd;
  31         end
  32 end
  33
  34 always @(posedge clk) begin
  35         if (we)
  36                 mem[wa] <= wd;
  37 end
  38
  39 endmodule
  40