tests/opt/bug1525.ys

   1 read_verilog << EOF
   2 module top(...);
   3 input A1, A2, B, S;
   4 output O;
   5
   6 assign O = S ? (A1 & B) : (A2 & B);
   7
   8 endmodule
   9 EOF
  10
  11 simplemap
  12 opt_share
  13 dump